hd64465pcmcia.c revision 1.30
1 /* $NetBSD: hd64465pcmcia.c,v 1.30 2012/10/29 12:51:38 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.30 2012/10/29 12:51:38 chs Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kthread.h> 40 #include <sys/boot_flag.h> 41 #include <sys/bus.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 #include <sh3/mmu.h> 53 54 #include <hpcsh/dev/hd64465/hd64465reg.h> 55 #include <hpcsh/dev/hd64465/hd64465var.h> 56 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 58 59 #include "locators.h" 60 61 #ifdef HD64465PCMCIA_DEBUG 62 #define DPRINTF_ENABLE 63 #define DPRINTF_DEBUG hd64465pcmcia_debug 64 #endif 65 #include <machine/debug.h> 66 67 enum memory_window_16 { 68 MEMWIN_16M_COMMON_0, 69 MEMWIN_16M_COMMON_1, 70 MEMWIN_16M_COMMON_2, 71 MEMWIN_16M_COMMON_3, 72 }; 73 #define MEMWIN_16M_MAX 4 74 75 enum hd64465pcmcia_event_type { 76 EVENT_NONE, 77 EVENT_INSERT, 78 EVENT_REMOVE, 79 }; 80 #define EVENT_QUEUE_MAX 5 81 82 struct hd64465pcmcia_softc; /* forward declaration */ 83 84 struct hd64465pcmcia_window_cookie { 85 bus_space_tag_t wc_tag; 86 bus_space_handle_t wc_handle; 87 int wc_size; 88 int wc_window; 89 }; 90 91 struct hd64465pcmcia_channel { 92 struct hd64465pcmcia_softc *ch_parent; 93 device_t ch_pcmcia; 94 int ch_channel; 95 96 /* memory space */ 97 bus_space_tag_t ch_memt; 98 bus_space_handle_t ch_memh; 99 bus_addr_t ch_membase_addr; 100 bus_size_t ch_memsize; 101 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 102 103 /* I/O space */ 104 bus_space_tag_t ch_iot; 105 bus_addr_t ch_iobase; 106 bus_size_t ch_iosize; 107 108 /* card interrupt */ 109 int (*ch_ih_card_func)(void *); 110 void *ch_ih_card_arg; 111 int ch_attached; 112 }; 113 114 struct hd64465pcmcia_event { 115 int __queued; 116 enum hd64465pcmcia_event_type pe_type; 117 struct hd64465pcmcia_channel *pe_ch; 118 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 119 }; 120 121 struct hd64465pcmcia_softc { 122 enum hd64465_module_id sc_module_id; 123 int sc_shutdown; 124 125 /* kv mapped Area 5, 6 */ 126 vaddr_t sc_area5; 127 vaddr_t sc_area6; 128 129 /* CSC event */ 130 lwp_t *sc_event_thread; 131 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 132 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 133 134 struct hd64465pcmcia_channel sc_ch[2]; 135 }; 136 137 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 138 struct pcmcia_mem_handle *); 139 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 140 struct pcmcia_mem_handle *); 141 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 142 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 143 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 144 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 145 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 146 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 147 struct pcmcia_io_handle *); 148 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 149 bus_size_t, struct pcmcia_io_handle *, int *); 150 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 151 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 152 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 153 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 154 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 155 struct pcmcia_function *, int, int (*)(void *), void *); 156 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 157 void *); 158 159 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 160 hd64465pcmcia_chip_mem_alloc, 161 hd64465pcmcia_chip_mem_free, 162 hd64465pcmcia_chip_mem_map, 163 hd64465pcmcia_chip_mem_unmap, 164 hd64465pcmcia_chip_io_alloc, 165 hd64465pcmcia_chip_io_free, 166 hd64465pcmcia_chip_io_map, 167 hd64465pcmcia_chip_io_unmap, 168 hd64465pcmcia_chip_intr_establish, 169 hd64465pcmcia_chip_intr_disestablish, 170 hd64465pcmcia_chip_socket_enable, 171 hd64465pcmcia_chip_socket_disable, 172 hd64465pcmcia_chip_socket_settype, 173 }; 174 175 STATIC int hd64465pcmcia_match(device_t, cfdata_t, void *); 176 STATIC void hd64465pcmcia_attach(device_t, device_t, void *); 177 STATIC int hd64465pcmcia_print(void *, const char *); 178 STATIC int hd64465pcmcia_submatch(device_t, cfdata_t, const int *, void *); 179 180 CFATTACH_DECL_NEW(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 181 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 182 183 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 184 /* hot plug */ 185 STATIC void hd64465pcmcia_event_thread(void *); 186 STATIC void __queue_event(struct hd64465pcmcia_channel *, 187 enum hd64465pcmcia_event_type); 188 /* interrupt handler */ 189 STATIC int hd64465pcmcia_intr(void *); 190 /* card status */ 191 STATIC enum hd64465pcmcia_event_type __detect_card(int); 192 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 193 /* bus width */ 194 STATIC void __sh_set_bus_width(int, int); 195 /* bus space access */ 196 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, uint32_t); 197 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 198 199 #define DELAY_MS(x) delay((x) * 1000) 200 201 int 202 hd64465pcmcia_match(device_t parent, cfdata_t cf, void *aux) 203 { 204 struct hd64465_attach_args *ha = aux; 205 206 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 207 } 208 209 void 210 hd64465pcmcia_attach(device_t parent, device_t self, void *aux) 211 { 212 struct hd64465_attach_args *ha = aux; 213 struct hd64465pcmcia_softc *sc = device_private(self); 214 int error; 215 216 sc->sc_module_id = ha->ha_module_id; 217 218 printf("\n"); 219 220 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 221 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 222 223 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 224 printf("%s: can't map memory.\n", device_xname(self)); 225 if (sc->sc_area5) 226 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000, 227 UVM_KMF_VAONLY); 228 if (sc->sc_area6) 229 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000, 230 UVM_KMF_VAONLY); 231 232 return; 233 } 234 235 /* Channel 0/1 common CSC event queue */ 236 SIMPLEQ_INIT (&sc->sc_event_head); 237 238 error = kthread_create(PRI_NONE, 0, NULL, hd64465pcmcia_event_thread, 239 sc, &sc->sc_event_thread, "%s", device_xname(self)); 240 KASSERT(error == 0); 241 242 hd64465pcmcia_attach_channel(sc, 0); 243 hd64465pcmcia_attach_channel(sc, 1); 244 } 245 246 void 247 hd64465pcmcia_event_thread(void *arg) 248 { 249 struct hd64465pcmcia_softc *sc = arg; 250 struct hd64465pcmcia_event *pe; 251 int s; 252 253 while (!sc->sc_shutdown) { 254 tsleep(sc, PWAIT, "CSC wait", 0); 255 s = splhigh(); 256 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 257 splx(s); 258 switch (pe->pe_type) { 259 default: 260 printf("%s: unknown event.\n", __func__); 261 break; 262 case EVENT_INSERT: 263 DPRINTF("insert event.\n"); 264 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 265 break; 266 case EVENT_REMOVE: 267 DPRINTF("remove event.\n"); 268 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 269 DETACH_FORCE); 270 break; 271 } 272 s = splhigh(); 273 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 274 pe->__queued = 0; 275 } 276 splx(s); 277 } 278 /* NOTREACHED */ 279 } 280 281 int 282 hd64465pcmcia_print(void *arg, const char *pnp) 283 { 284 285 if (pnp) 286 aprint_normal("pcmcia at %s", pnp); 287 288 return (UNCONF); 289 } 290 291 int 292 hd64465pcmcia_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 293 { 294 struct pcmciabus_attach_args *paa = aux; 295 struct hd64465pcmcia_channel *ch = 296 (struct hd64465pcmcia_channel *)paa->pch; 297 298 if (ch->ch_channel == 0) { 299 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 300 PCMCIABUSCF_CONTROLLER_DEFAULT && 301 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 302 return 0; 303 } else { 304 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 305 PCMCIABUSCF_CONTROLLER_DEFAULT && 306 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 307 return 0; 308 } 309 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 310 311 return (config_match(parent, cf, aux)); 312 } 313 314 void 315 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 316 { 317 device_t parent = sc->sc_dev; 318 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 319 struct pcmciabus_attach_args paa; 320 bus_addr_t baseaddr; 321 uint8_t r; 322 int i; 323 324 ch->ch_parent = sc; 325 ch->ch_channel = channel; 326 327 /* 328 * Continuous 16-MB Area Mode 329 */ 330 /* set Continuous 16-MB Area Mode */ 331 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 332 r &= ~HD64461_PCCGCR_MMOD; 333 r |= HD64461_PCCGCR_MMOD_16M; 334 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 335 336 /* Attibute/Common memory extent */ 337 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 338 339 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 340 baseaddr, 0x01000000); /* 16MB */ 341 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 342 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 343 344 /* Common memory space extent */ 345 ch->ch_memsize = 0x01000000; 346 for (i = 0; i < MEMWIN_16M_MAX; i++) { 347 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 348 baseaddr + 0x01000000, ch->ch_memsize); 349 } 350 351 /* I/O port extent */ 352 ch->ch_iobase = 0; 353 ch->ch_iosize = 0x01000000; 354 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 355 baseaddr + 0x01000000 * 2, ch->ch_iosize); 356 357 /* Interrupt */ 358 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 359 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 360 361 paa.paa_busname = "pcmcia"; 362 paa.pch = (pcmcia_chipset_handle_t)ch; 363 364 ch->ch_pcmcia = config_found_sm_loc(parent, "pcmciabus", NULL, &paa, 365 hd64465pcmcia_print, hd64465pcmcia_submatch); 366 367 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 368 ch->ch_attached = 1; 369 pcmcia_card_attach(ch->ch_pcmcia); 370 } 371 } 372 373 int 374 hd64465pcmcia_intr(void *arg) 375 { 376 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 377 uint32_t cscr; 378 uint8_t r; 379 int ret = 0; 380 381 cscr = HD64461_PCCCSCR(ch->ch_channel); 382 r = hd64465_reg_read_1(cscr); 383 384 /* clear interrtupt (don't change power switch select) */ 385 hd64465_reg_write_1(cscr, r & ~0x40); 386 387 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 388 if (ch->ch_ih_card_func) { 389 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 390 } else { 391 DPRINTF("spurious IREQ interrupt.\n"); 392 } 393 } 394 395 if (r & HD64461_PCC0CSCR_P0CDC) 396 __queue_event(ch, __detect_card(ch->ch_channel)); 397 398 return (ret); 399 } 400 401 void 402 __queue_event(struct hd64465pcmcia_channel *ch, 403 enum hd64465pcmcia_event_type type) 404 { 405 struct hd64465pcmcia_event *pe, *pool; 406 struct hd64465pcmcia_softc *sc = ch->ch_parent; 407 int i; 408 int s = splhigh(); 409 410 if (type == EVENT_NONE) 411 goto out; 412 413 pe = 0; 414 pool = sc->sc_event_pool; 415 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 416 if (!pool[i].__queued) { 417 pe = &pool[i]; 418 break; 419 } 420 } 421 422 if (pe == 0) { 423 printf("%s: event FIFO overflow (max %d).\n", __func__, 424 EVENT_QUEUE_MAX); 425 goto out; 426 } 427 428 if ((ch->ch_attached && (type == EVENT_INSERT)) || 429 (!ch->ch_attached && (type == EVENT_REMOVE))) { 430 DPRINTF("spurious CSC interrupt.\n"); 431 goto out; 432 } 433 434 ch->ch_attached = (type == EVENT_INSERT); 435 pe->__queued = 1; 436 pe->pe_type = type; 437 pe->pe_ch = ch; 438 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 439 wakeup(sc); 440 out: 441 splx(s); 442 } 443 444 /* 445 * Interface for pcmcia driver. 446 */ 447 /* 448 * Interrupt. 449 */ 450 void * 451 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 452 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 453 { 454 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 455 int channel = ch->ch_channel; 456 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 457 uint8_t r; 458 int s = splhigh(); 459 460 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 461 ipl); 462 463 ch->ch_ih_card_func = ih_func; 464 ch->ch_ih_card_arg = ih_arg; 465 466 /* Enable card interrupt */ 467 r = hd64465_reg_read_1(cscier); 468 /* set level mode */ 469 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 470 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 471 hd64465_reg_write_1(cscier, r); 472 473 splx(s); 474 475 return (void *)ih_func; 476 } 477 478 void 479 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 480 { 481 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 482 int channel = ch->ch_channel; 483 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 484 int s = splhigh(); 485 uint8_t r; 486 487 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 488 IPL_TTY); 489 490 /* Disable card interrupt */ 491 r = hd64465_reg_read_1(cscier); 492 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 493 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 494 hd64465_reg_write_1(cscier, r); 495 496 ch->ch_ih_card_func = 0; 497 498 splx(s); 499 } 500 501 /* 502 * Bus resources. 503 */ 504 int 505 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 506 struct pcmcia_mem_handle *pcmhp) 507 { 508 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 509 510 pcmhp->memt = ch->ch_memt; 511 pcmhp->addr = ch->ch_membase_addr; 512 pcmhp->memh = ch->ch_memh; 513 pcmhp->size = size; 514 pcmhp->realsize = size; 515 516 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 517 518 return (0); 519 } 520 521 void 522 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 523 struct pcmcia_mem_handle *pcmhp) 524 { 525 /* NO-OP */ 526 } 527 528 int 529 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 530 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 531 bus_size_t *offsetp, int *windowp) 532 { 533 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 534 struct hd64465pcmcia_window_cookie *cookie; 535 bus_addr_t ofs; 536 537 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 538 M_DEVBUF, M_NOWAIT); 539 KASSERT(cookie); 540 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 541 542 /* Address */ 543 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 544 cookie->wc_tag = ch->ch_memt; 545 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 546 size, &cookie->wc_handle) != 0) 547 goto bad; 548 549 *offsetp = card_addr; 550 cookie->wc_window = -1; 551 } else { 552 int window = card_addr / ch->ch_memsize; 553 KASSERT(window < MEMWIN_16M_MAX); 554 555 cookie->wc_tag = ch->ch_cmemt[window]; 556 ofs = card_addr - window * ch->ch_memsize; 557 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 558 &cookie->wc_handle) != 0) 559 goto bad; 560 561 /* XXX bogus. check window per common memory access. */ 562 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 563 *offsetp = ofs + 0x01000000; /* skip attribute area */ 564 cookie->wc_window = window; 565 } 566 cookie->wc_size = size; 567 *windowp = (int)cookie; 568 569 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 570 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 571 572 return (0); 573 bad: 574 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 575 free(cookie, M_DEVBUF); 576 577 return (1); 578 } 579 580 void 581 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 582 { 583 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 584 585 if (cookie->wc_window != -1) 586 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 587 cookie->wc_size); 588 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 589 free(cookie, M_DEVBUF); 590 } 591 592 int 593 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 594 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 595 { 596 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 597 598 if (start) { 599 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 600 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 601 return (1); 602 } 603 pcihp->addr = pcihp->ioh; 604 DPRINTF("map %#lx+%#lx\n", start, size); 605 } else { 606 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 607 ch->ch_iobase + ch->ch_iosize - 1, 608 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 609 DPRINTF("couldn't allocate %#lx\n", size); 610 return (1); 611 } 612 pcihp->flags = PCMCIA_IO_ALLOCATED; 613 } 614 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 615 616 pcihp->iot = ch->ch_iot; 617 pcihp->size = size; 618 619 return (0); 620 } 621 622 int 623 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 624 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 625 int *windowp) 626 { 627 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 628 #ifdef HD64465PCMCIA_DEBUG 629 static const char *width_names[] = { "auto", "io8", "io16" }; 630 #endif 631 632 __sh_set_bus_width(ch->ch_channel, width); 633 634 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 635 width_names[width]); 636 637 return (0); 638 } 639 640 void 641 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 642 struct pcmcia_io_handle *pcihp) 643 { 644 645 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 646 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 647 else 648 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 649 650 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 651 } 652 653 void 654 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 655 { 656 /* nothing to do */ 657 } 658 659 /* 660 * Enable/Disable 661 */ 662 void 663 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 664 { 665 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 666 int channel = ch->ch_channel; 667 bus_addr_t gcr; 668 uint8_t r; 669 670 DPRINTF("enable channel %d\n", channel); 671 gcr = HD64461_PCCGCR(channel); 672 673 r = hd64465_reg_read_1(gcr); 674 r &= ~HD64461_PCC0GCR_P0PCCT; 675 hd64465_reg_write_1(gcr, r); 676 677 /* Set Common memory area #0. */ 678 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 679 680 DPRINTF("OK.\n"); 681 } 682 683 void 684 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 685 { 686 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 687 int channel = ch->ch_channel; 688 bus_addr_t gcr; 689 uint8_t r; 690 691 DPRINTF("settype channel %d\n", channel); 692 gcr = HD64461_PCCGCR(channel); 693 694 /* Set the card type */ 695 r = hd64465_reg_read_1(gcr); 696 if (type == PCMCIA_IFTYPE_IO) 697 r |= HD64461_PCC0GCR_P0PCCT; 698 else 699 r &= ~HD64461_PCC0GCR_P0PCCT; 700 hd64465_reg_write_1(gcr, r); 701 702 DPRINTF("OK.\n"); 703 } 704 705 void 706 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 707 { 708 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 709 int channel = ch->ch_channel; 710 711 /* dont' disable CSC interrupt */ 712 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 713 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 714 } 715 716 /* 717 * Card detect 718 */ 719 enum hd64465pcmcia_event_type 720 __detect_card(int channel) 721 { 722 uint8_t r; 723 724 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 725 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 726 727 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 728 DPRINTF("remove\n"); 729 return EVENT_REMOVE; 730 } 731 if (r == 0) { 732 DPRINTF("insert\n"); 733 return EVENT_INSERT; 734 } 735 DPRINTF("transition\n"); 736 737 return (EVENT_NONE); 738 } 739 740 /* 741 * Memory window access ops. 742 */ 743 void 744 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 745 { 746 bus_addr_t a = HD64461_PCCGCR(channel); 747 uint8_t r; 748 749 r = hd64465_reg_read_1(a); 750 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 751 752 switch (window) { 753 case MEMWIN_16M_COMMON_0: 754 break; 755 case MEMWIN_16M_COMMON_1: 756 r |= HD64461_PCCGCR_PA24; 757 break; 758 case MEMWIN_16M_COMMON_2: 759 r |= HD64461_PCCGCR_PA25; 760 break; 761 case MEMWIN_16M_COMMON_3: 762 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 763 break; 764 } 765 766 hd64465_reg_write_1(a, r); 767 } 768 769 /* 770 * SH interface. 771 */ 772 void 773 __sh_set_bus_width(int channel, int width) 774 { 775 uint16_t r16; 776 777 r16 = _reg_read_2(SH4_BCR2); 778 #ifdef HD64465PCMCIA_DEBUG 779 dbg_bit_print_msg(r16, "BCR2"); 780 #endif 781 if (channel == 0) { 782 r16 &= ~((1 << 13)|(1 << 12)); 783 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 784 } else { 785 r16 &= ~((1 << 11)|(1 << 10)); 786 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 787 } 788 _reg_write_2(SH4_BCR2, r16); 789 } 790 791 vaddr_t 792 __sh_hd64465_map_2page(paddr_t pa) 793 { 794 static const uint32_t mode[] = 795 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 796 vaddr_t va, v; 797 int i; 798 799 /* allocate kernel virtual */ 800 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY); 801 if (va == 0) { 802 PRINTF("can't allocate virtual for paddr 0x%08x\n", 803 (unsigned)pa); 804 805 return (0); 806 } 807 808 /* map to physical addreess with specified memory type. */ 809 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 810 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 811 pmap_kremove(v, 0x03000000); 812 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY); 813 return (0); 814 } 815 } 816 817 return (v); 818 } 819 820 int 821 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, uint32_t flags) 822 { 823 pt_entry_t *pte; 824 paddr_t epa; 825 826 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 827 ((sz & PAGE_MASK) == 0)); 828 829 epa = pa + sz; 830 while (pa < epa) { 831 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0); 832 pte = __pmap_kpte_lookup(va); 833 KDASSERT(pte); 834 *pte |= flags; /* PTEA PCMCIA assistant bit */ 835 sh_tlb_update(0, va, *pte); 836 pa += PAGE_SIZE; 837 va += PAGE_SIZE; 838 } 839 840 return (0); 841 } 842
Indexes created Fri Oct 03 02:09:57 GMT 2025