hd64465pcmcia.c revision 1.33.2.1
1 /* $NetBSD: hd64465pcmcia.c,v 1.33.2.1 2021/03/22 02:00:56 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: hd64465pcmcia.c,v 1.33.2.1 2021/03/22 02:00:56 thorpej Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/kmem.h> 39 #include <sys/kthread.h> 40 #include <sys/boot_flag.h> 41 #include <sys/bus.h> 42 43 #include <uvm/uvm_extern.h> 44 45 #include <machine/intr.h> 46 47 #include <dev/pcmcia/pcmciareg.h> 48 #include <dev/pcmcia/pcmciavar.h> 49 #include <dev/pcmcia/pcmciachip.h> 50 51 #include <sh3/bscreg.h> 52 #include <sh3/mmu.h> 53 54 #include <hpcsh/dev/hd64465/hd64465reg.h> 55 #include <hpcsh/dev/hd64465/hd64465var.h> 56 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 57 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 58 59 #include "locators.h" 60 61 #ifdef HD64465PCMCIA_DEBUG 62 #define DPRINTF_ENABLE 63 #define DPRINTF_DEBUG hd64465pcmcia_debug 64 #endif 65 #include <machine/debug.h> 66 67 enum memory_window_16 { 68 MEMWIN_16M_COMMON_0, 69 MEMWIN_16M_COMMON_1, 70 MEMWIN_16M_COMMON_2, 71 MEMWIN_16M_COMMON_3, 72 }; 73 #define MEMWIN_16M_MAX 4 74 75 enum hd64465pcmcia_event_type { 76 EVENT_NONE, 77 EVENT_INSERT, 78 EVENT_REMOVE, 79 }; 80 #define EVENT_QUEUE_MAX 5 81 82 struct hd64465pcmcia_softc; /* forward declaration */ 83 84 struct hd64465pcmcia_window_cookie { 85 bus_space_tag_t wc_tag; 86 bus_space_handle_t wc_handle; 87 int wc_size; 88 int wc_window; 89 }; 90 91 struct hd64465pcmcia_channel { 92 struct hd64465pcmcia_softc *ch_parent; 93 device_t ch_pcmcia; 94 int ch_channel; 95 96 /* memory space */ 97 bus_space_tag_t ch_memt; 98 bus_space_handle_t ch_memh; 99 bus_addr_t ch_membase_addr; 100 bus_size_t ch_memsize; 101 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 102 103 /* I/O space */ 104 bus_space_tag_t ch_iot; 105 bus_addr_t ch_iobase; 106 bus_size_t ch_iosize; 107 108 /* card interrupt */ 109 int (*ch_ih_card_func)(void *); 110 void *ch_ih_card_arg; 111 int ch_attached; 112 }; 113 114 struct hd64465pcmcia_event { 115 int __queued; 116 enum hd64465pcmcia_event_type pe_type; 117 struct hd64465pcmcia_channel *pe_ch; 118 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 119 }; 120 121 struct hd64465pcmcia_softc { 122 device_t sc_dev; 123 enum hd64465_module_id sc_module_id; 124 int sc_shutdown; 125 126 /* kv mapped Area 5, 6 */ 127 vaddr_t sc_area5; 128 vaddr_t sc_area6; 129 130 /* CSC event */ 131 lwp_t *sc_event_thread; 132 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 133 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 134 135 struct hd64465pcmcia_channel sc_ch[2]; 136 }; 137 138 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 139 struct pcmcia_mem_handle *); 140 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 141 struct pcmcia_mem_handle *); 142 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 143 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 144 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 145 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 146 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 147 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 148 struct pcmcia_io_handle *); 149 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 150 bus_size_t, struct pcmcia_io_handle *, int *); 151 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 152 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 153 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 154 STATIC void hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t, int); 155 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 156 struct pcmcia_function *, int, int (*)(void *), void *); 157 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 158 void *); 159 160 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 161 hd64465pcmcia_chip_mem_alloc, 162 hd64465pcmcia_chip_mem_free, 163 hd64465pcmcia_chip_mem_map, 164 hd64465pcmcia_chip_mem_unmap, 165 hd64465pcmcia_chip_io_alloc, 166 hd64465pcmcia_chip_io_free, 167 hd64465pcmcia_chip_io_map, 168 hd64465pcmcia_chip_io_unmap, 169 hd64465pcmcia_chip_intr_establish, 170 hd64465pcmcia_chip_intr_disestablish, 171 hd64465pcmcia_chip_socket_enable, 172 hd64465pcmcia_chip_socket_disable, 173 hd64465pcmcia_chip_socket_settype, 174 }; 175 176 STATIC int hd64465pcmcia_match(device_t, cfdata_t, void *); 177 STATIC void hd64465pcmcia_attach(device_t, device_t, void *); 178 STATIC int hd64465pcmcia_print(void *, const char *); 179 STATIC int hd64465pcmcia_submatch(device_t, cfdata_t, const int *, void *); 180 181 CFATTACH_DECL_NEW(hd64465pcmcia, sizeof(struct hd64465pcmcia_softc), 182 hd64465pcmcia_match, hd64465pcmcia_attach, NULL, NULL); 183 184 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 185 /* hot plug */ 186 STATIC void hd64465pcmcia_event_thread(void *); 187 STATIC void __queue_event(struct hd64465pcmcia_channel *, 188 enum hd64465pcmcia_event_type); 189 /* interrupt handler */ 190 STATIC int hd64465pcmcia_intr(void *); 191 /* card status */ 192 STATIC enum hd64465pcmcia_event_type __detect_card(int); 193 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 194 /* bus width */ 195 STATIC void __sh_set_bus_width(int, int); 196 /* bus space access */ 197 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, uint32_t); 198 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 199 200 #define DELAY_MS(x) delay((x) * 1000) 201 202 int 203 hd64465pcmcia_match(device_t parent, cfdata_t cf, void *aux) 204 { 205 struct hd64465_attach_args *ha = aux; 206 207 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 208 } 209 210 void 211 hd64465pcmcia_attach(device_t parent, device_t self, void *aux) 212 { 213 struct hd64465_attach_args *ha = aux; 214 struct hd64465pcmcia_softc *sc = device_private(self); 215 int error; 216 217 sc->sc_dev = self; 218 sc->sc_module_id = ha->ha_module_id; 219 220 printf("\n"); 221 222 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 223 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 224 225 if (sc->sc_area5 == 0 || sc->sc_area6 == 0) { 226 printf("%s: can't map memory.\n", device_xname(self)); 227 if (sc->sc_area5) 228 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000, 229 UVM_KMF_VAONLY); 230 if (sc->sc_area6) 231 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000, 232 UVM_KMF_VAONLY); 233 234 return; 235 } 236 237 /* Channel 0/1 common CSC event queue */ 238 SIMPLEQ_INIT (&sc->sc_event_head); 239 240 error = kthread_create(PRI_NONE, 0, NULL, hd64465pcmcia_event_thread, 241 sc, &sc->sc_event_thread, "%s", device_xname(self)); 242 KASSERT(error == 0); 243 244 hd64465pcmcia_attach_channel(sc, 0); 245 hd64465pcmcia_attach_channel(sc, 1); 246 } 247 248 void 249 hd64465pcmcia_event_thread(void *arg) 250 { 251 struct hd64465pcmcia_softc *sc = arg; 252 struct hd64465pcmcia_event *pe; 253 int s; 254 255 while (!sc->sc_shutdown) { 256 tsleep(sc, PWAIT, "CSC wait", 0); 257 s = splhigh(); 258 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 259 splx(s); 260 switch (pe->pe_type) { 261 default: 262 printf("%s: unknown event.\n", __func__); 263 break; 264 case EVENT_INSERT: 265 DPRINTF("insert event.\n"); 266 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 267 break; 268 case EVENT_REMOVE: 269 DPRINTF("remove event.\n"); 270 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 271 DETACH_FORCE); 272 break; 273 } 274 s = splhigh(); 275 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 276 pe->__queued = 0; 277 } 278 splx(s); 279 } 280 /* NOTREACHED */ 281 } 282 283 int 284 hd64465pcmcia_print(void *arg, const char *pnp) 285 { 286 287 if (pnp) 288 aprint_normal("pcmcia at %s", pnp); 289 290 return (UNCONF); 291 } 292 293 int 294 hd64465pcmcia_submatch(device_t parent, cfdata_t cf, const int *ldesc, void *aux) 295 { 296 struct pcmciabus_attach_args *paa = aux; 297 struct hd64465pcmcia_channel *ch = 298 (struct hd64465pcmcia_channel *)paa->pch; 299 300 if (ch->ch_channel == 0) { 301 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 302 PCMCIABUSCF_CONTROLLER_DEFAULT && 303 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 304 return 0; 305 } else { 306 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 307 PCMCIABUSCF_CONTROLLER_DEFAULT && 308 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 309 return 0; 310 } 311 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 312 313 return (config_match(parent, cf, aux)); 314 } 315 316 void 317 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 318 { 319 device_t parent = sc->sc_dev; 320 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 321 struct pcmciabus_attach_args paa; 322 bus_addr_t baseaddr; 323 uint8_t r; 324 int i; 325 326 ch->ch_parent = sc; 327 ch->ch_channel = channel; 328 329 /* 330 * Continuous 16-MB Area Mode 331 */ 332 /* set Continuous 16-MB Area Mode */ 333 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 334 r &= ~HD64461_PCCGCR_MMOD; 335 r |= HD64461_PCCGCR_MMOD_16M; 336 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 337 338 /* Attibute/Common memory extent */ 339 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 340 341 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 342 baseaddr, 0x01000000); /* 16MB */ 343 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 344 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 345 346 /* Common memory space extent */ 347 ch->ch_memsize = 0x01000000; 348 for (i = 0; i < MEMWIN_16M_MAX; i++) { 349 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 350 baseaddr + 0x01000000, ch->ch_memsize); 351 } 352 353 /* I/O port extent */ 354 ch->ch_iobase = 0; 355 ch->ch_iosize = 0x01000000; 356 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 357 baseaddr + 0x01000000 * 2, ch->ch_iosize); 358 359 /* Interrupt */ 360 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 361 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 362 363 paa.paa_busname = "pcmcia"; 364 paa.pch = (pcmcia_chipset_handle_t)ch; 365 366 ch->ch_pcmcia = config_found(parent, &paa, hd64465pcmcia_print, 367 CFARG_SUBMATCH, hd64465pcmcia_submatch, 368 CFARG_IATTR, "pcmciabus", 369 CFARG_EOL); 370 371 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 372 ch->ch_attached = 1; 373 pcmcia_card_attach(ch->ch_pcmcia); 374 } 375 } 376 377 int 378 hd64465pcmcia_intr(void *arg) 379 { 380 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 381 uint32_t cscr; 382 uint8_t r; 383 int ret = 0; 384 385 cscr = HD64461_PCCCSCR(ch->ch_channel); 386 r = hd64465_reg_read_1(cscr); 387 388 /* clear interrtupt (don't change power switch select) */ 389 hd64465_reg_write_1(cscr, r & ~0x40); 390 391 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 392 if (ch->ch_ih_card_func) { 393 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 394 } else { 395 DPRINTF("spurious IREQ interrupt.\n"); 396 } 397 } 398 399 if (r & HD64461_PCC0CSCR_P0CDC) 400 __queue_event(ch, __detect_card(ch->ch_channel)); 401 402 return (ret); 403 } 404 405 void 406 __queue_event(struct hd64465pcmcia_channel *ch, 407 enum hd64465pcmcia_event_type type) 408 { 409 struct hd64465pcmcia_event *pe, *pool; 410 struct hd64465pcmcia_softc *sc = ch->ch_parent; 411 int i; 412 int s = splhigh(); 413 414 if (type == EVENT_NONE) 415 goto out; 416 417 pe = 0; 418 pool = sc->sc_event_pool; 419 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 420 if (!pool[i].__queued) { 421 pe = &pool[i]; 422 break; 423 } 424 } 425 426 if (pe == 0) { 427 printf("%s: event FIFO overflow (max %d).\n", __func__, 428 EVENT_QUEUE_MAX); 429 goto out; 430 } 431 432 if ((ch->ch_attached && (type == EVENT_INSERT)) || 433 (!ch->ch_attached && (type == EVENT_REMOVE))) { 434 DPRINTF("spurious CSC interrupt.\n"); 435 goto out; 436 } 437 438 ch->ch_attached = (type == EVENT_INSERT); 439 pe->__queued = 1; 440 pe->pe_type = type; 441 pe->pe_ch = ch; 442 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 443 wakeup(sc); 444 out: 445 splx(s); 446 } 447 448 /* 449 * Interface for pcmcia driver. 450 */ 451 /* 452 * Interrupt. 453 */ 454 void * 455 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 456 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 457 { 458 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 459 int channel = ch->ch_channel; 460 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 461 uint8_t r; 462 int s = splhigh(); 463 464 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 465 ipl); 466 467 ch->ch_ih_card_func = ih_func; 468 ch->ch_ih_card_arg = ih_arg; 469 470 /* Enable card interrupt */ 471 r = hd64465_reg_read_1(cscier); 472 /* set level mode */ 473 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 474 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 475 hd64465_reg_write_1(cscier, r); 476 477 splx(s); 478 479 return (void *)ih_func; 480 } 481 482 void 483 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 484 { 485 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 486 int channel = ch->ch_channel; 487 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 488 int s = splhigh(); 489 uint8_t r; 490 491 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 492 IPL_TTY); 493 494 /* Disable card interrupt */ 495 r = hd64465_reg_read_1(cscier); 496 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 497 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 498 hd64465_reg_write_1(cscier, r); 499 500 ch->ch_ih_card_func = 0; 501 502 splx(s); 503 } 504 505 /* 506 * Bus resources. 507 */ 508 int 509 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 510 struct pcmcia_mem_handle *pcmhp) 511 { 512 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 513 514 pcmhp->memt = ch->ch_memt; 515 pcmhp->addr = ch->ch_membase_addr; 516 pcmhp->memh = ch->ch_memh; 517 pcmhp->size = size; 518 pcmhp->realsize = size; 519 520 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 521 522 return (0); 523 } 524 525 void 526 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 527 struct pcmcia_mem_handle *pcmhp) 528 { 529 /* NO-OP */ 530 } 531 532 int 533 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 534 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 535 bus_size_t *offsetp, int *windowp) 536 { 537 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 538 struct hd64465pcmcia_window_cookie *cookie; 539 bus_addr_t ofs; 540 541 cookie = kmem_zalloc(sizeof(struct hd64465pcmcia_window_cookie), 542 KM_SLEEP); 543 KASSERT(cookie); 544 545 /* Address */ 546 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 547 cookie->wc_tag = ch->ch_memt; 548 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 549 size, &cookie->wc_handle) != 0) 550 goto bad; 551 552 *offsetp = card_addr; 553 cookie->wc_window = -1; 554 } else { 555 int window = card_addr / ch->ch_memsize; 556 KASSERT(window < MEMWIN_16M_MAX); 557 558 cookie->wc_tag = ch->ch_cmemt[window]; 559 ofs = card_addr - window * ch->ch_memsize; 560 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 561 &cookie->wc_handle) != 0) 562 goto bad; 563 564 /* XXX bogus. check window per common memory access. */ 565 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 566 *offsetp = ofs + 0x01000000; /* skip attribute area */ 567 cookie->wc_window = window; 568 } 569 cookie->wc_size = size; 570 *windowp = (int)cookie; 571 572 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 573 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 574 575 return (0); 576 bad: 577 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 578 kmem_free(cookie, sizeof(*cookie)); 579 580 return (1); 581 } 582 583 void 584 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 585 { 586 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 587 588 if (cookie->wc_window != -1) 589 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 590 cookie->wc_size); 591 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 592 kmem_free(cookie, sizeof(*cookie)); 593 } 594 595 int 596 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 597 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 598 { 599 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 600 601 if (start) { 602 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 603 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 604 return (1); 605 } 606 pcihp->addr = pcihp->ioh; 607 DPRINTF("map %#lx+%#lx\n", start, size); 608 } else { 609 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 610 ch->ch_iobase + ch->ch_iosize - 1, 611 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 612 DPRINTF("couldn't allocate %#lx\n", size); 613 return (1); 614 } 615 pcihp->flags = PCMCIA_IO_ALLOCATED; 616 } 617 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 618 619 pcihp->iot = ch->ch_iot; 620 pcihp->size = size; 621 622 return (0); 623 } 624 625 int 626 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 627 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 628 int *windowp) 629 { 630 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 631 #ifdef HD64465PCMCIA_DEBUG 632 static const char *width_names[] = { "auto", "io8", "io16" }; 633 #endif 634 635 __sh_set_bus_width(ch->ch_channel, width); 636 637 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 638 width_names[width]); 639 640 return (0); 641 } 642 643 void 644 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 645 struct pcmcia_io_handle *pcihp) 646 { 647 648 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 649 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 650 else 651 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 652 653 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 654 } 655 656 void 657 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 658 { 659 /* nothing to do */ 660 } 661 662 /* 663 * Enable/Disable 664 */ 665 void 666 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 667 { 668 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 669 int channel = ch->ch_channel; 670 bus_addr_t gcr; 671 uint8_t r; 672 673 DPRINTF("enable channel %d\n", channel); 674 gcr = HD64461_PCCGCR(channel); 675 676 r = hd64465_reg_read_1(gcr); 677 r &= ~HD64461_PCC0GCR_P0PCCT; 678 hd64465_reg_write_1(gcr, r); 679 680 /* Set Common memory area #0. */ 681 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 682 683 DPRINTF("OK.\n"); 684 } 685 686 void 687 hd64465pcmcia_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 688 { 689 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 690 int channel = ch->ch_channel; 691 bus_addr_t gcr; 692 uint8_t r; 693 694 DPRINTF("settype channel %d\n", channel); 695 gcr = HD64461_PCCGCR(channel); 696 697 /* Set the card type */ 698 r = hd64465_reg_read_1(gcr); 699 if (type == PCMCIA_IFTYPE_IO) 700 r |= HD64461_PCC0GCR_P0PCCT; 701 else 702 r &= ~HD64461_PCC0GCR_P0PCCT; 703 hd64465_reg_write_1(gcr, r); 704 705 DPRINTF("OK.\n"); 706 } 707 708 void 709 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 710 { 711 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 712 int channel = ch->ch_channel; 713 714 /* dont' disable CSC interrupt */ 715 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 716 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 717 } 718 719 /* 720 * Card detect 721 */ 722 enum hd64465pcmcia_event_type 723 __detect_card(int channel) 724 { 725 uint8_t r; 726 727 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 728 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 729 730 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 731 DPRINTF("remove\n"); 732 return EVENT_REMOVE; 733 } 734 if (r == 0) { 735 DPRINTF("insert\n"); 736 return EVENT_INSERT; 737 } 738 DPRINTF("transition\n"); 739 740 return (EVENT_NONE); 741 } 742 743 /* 744 * Memory window access ops. 745 */ 746 void 747 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 748 { 749 bus_addr_t a = HD64461_PCCGCR(channel); 750 uint8_t r; 751 752 r = hd64465_reg_read_1(a); 753 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 754 755 switch (window) { 756 case MEMWIN_16M_COMMON_0: 757 break; 758 case MEMWIN_16M_COMMON_1: 759 r |= HD64461_PCCGCR_PA24; 760 break; 761 case MEMWIN_16M_COMMON_2: 762 r |= HD64461_PCCGCR_PA25; 763 break; 764 case MEMWIN_16M_COMMON_3: 765 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 766 break; 767 } 768 769 hd64465_reg_write_1(a, r); 770 } 771 772 /* 773 * SH interface. 774 */ 775 void 776 __sh_set_bus_width(int channel, int width) 777 { 778 uint16_t r16; 779 780 r16 = _reg_read_2(SH4_BCR2); 781 #ifdef HD64465PCMCIA_DEBUG 782 dbg_bit_print_msg(r16, "BCR2"); 783 #endif 784 if (channel == 0) { 785 r16 &= ~((1 << 13)|(1 << 12)); 786 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 787 } else { 788 r16 &= ~((1 << 11)|(1 << 10)); 789 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 790 } 791 _reg_write_2(SH4_BCR2, r16); 792 } 793 794 vaddr_t 795 __sh_hd64465_map_2page(paddr_t pa) 796 { 797 static const uint32_t mode[] = 798 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 799 vaddr_t va, v; 800 int i; 801 802 /* allocate kernel virtual */ 803 v = va = uvm_km_alloc(kernel_map, 0x03000000, 0, UVM_KMF_VAONLY); 804 if (va == 0) { 805 PRINTF("can't allocate virtual for paddr 0x%08x\n", 806 (unsigned)pa); 807 808 return (0); 809 } 810 811 /* map to physical addreess with specified memory type. */ 812 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 813 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 814 pmap_kremove(v, 0x03000000); 815 uvm_km_free(kernel_map, v, 0x03000000, UVM_KMF_VAONLY); 816 return (0); 817 } 818 } 819 820 return (v); 821 } 822 823 int 824 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, uint32_t flags) 825 { 826 pt_entry_t *pte; 827 paddr_t epa; 828 829 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 830 ((sz & PAGE_MASK) == 0)); 831 832 epa = pa + sz; 833 while (pa < epa) { 834 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE, 0); 835 pte = __pmap_kpte_lookup(va); 836 KDASSERT(pte); 837 *pte |= flags; /* PTEA PCMCIA assistant bit */ 838 sh_tlb_update(0, va, *pte); 839 pa += PAGE_SIZE; 840 va += PAGE_SIZE; 841 } 842 843 return (0); 844 } 845
Indexes created Sat Oct 18 08:10:09 GMT 2025