hd64465pcmcia.c revision 1.4
1 /* $NetBSD: hd64465pcmcia.c,v 1.4 2002/03/28 15:27:02 uch Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/kthread.h> 44 #include <sys/boot_flag.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 57 #include <hpcsh/dev/hd64465/hd64465reg.h> 58 #include <hpcsh/dev/hd64465/hd64465var.h> 59 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 60 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 61 62 #include "locators.h" 63 64 #ifdef HD64465PCMCIA_DEBUG 65 #define DPRINTF_ENABLE 66 #define DPRINTF_DEBUG hd64465pcmcia_debug 67 #endif 68 #include <machine/debug.h> 69 70 enum memory_window_16 { 71 MEMWIN_16M_COMMON_0, 72 MEMWIN_16M_COMMON_1, 73 MEMWIN_16M_COMMON_2, 74 MEMWIN_16M_COMMON_3, 75 }; 76 #define MEMWIN_16M_MAX 4 77 78 enum hd64465pcmcia_event_type { 79 EVENT_NONE, 80 EVENT_INSERT, 81 EVENT_REMOVE, 82 }; 83 #define EVENT_QUEUE_MAX 5 84 85 struct hd64465pcmcia_softc; /* forward declaration */ 86 87 struct hd64465pcmcia_window_cookie { 88 bus_space_tag_t wc_tag; 89 bus_space_handle_t wc_handle; 90 int wc_size; 91 int wc_window; 92 }; 93 94 struct hd64465pcmcia_channel { 95 struct hd64465pcmcia_softc *ch_parent; 96 struct device *ch_pcmcia; 97 int ch_channel; 98 99 /* memory space */ 100 bus_space_tag_t ch_memt; 101 bus_space_handle_t ch_memh; 102 bus_addr_t ch_membase_addr; 103 bus_size_t ch_memsize; 104 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 105 106 /* I/O space */ 107 bus_space_tag_t ch_iot; 108 bus_addr_t ch_iobase; 109 bus_size_t ch_iosize; 110 111 /* card interrupt */ 112 int (*ch_ih_card_func)(void *); 113 void *ch_ih_card_arg; 114 int ch_attached; 115 }; 116 117 struct hd64465pcmcia_event { 118 int __queued; 119 enum hd64465pcmcia_event_type pe_type; 120 struct hd64465pcmcia_channel *pe_ch; 121 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 122 }; 123 124 struct hd64465pcmcia_softc { 125 struct device sc_dev; 126 enum hd64465_module_id sc_module_id; 127 int sc_shutdown; 128 129 /* kv mapped Area 5, 6 */ 130 vaddr_t sc_area5; 131 vaddr_t sc_area6; 132 133 /* CSC event */ 134 struct proc *sc_event_thread; 135 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 136 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 137 138 struct hd64465pcmcia_channel sc_ch[2]; 139 }; 140 141 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 142 struct pcmcia_mem_handle *); 143 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 144 struct pcmcia_mem_handle *); 145 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 146 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 147 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 148 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 149 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 150 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 151 struct pcmcia_io_handle *); 152 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 153 bus_size_t, struct pcmcia_io_handle *, int *); 154 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 155 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 156 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 157 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 158 struct pcmcia_function *, int, int (*)(void *), void *); 159 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 160 void *); 161 162 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 163 hd64465pcmcia_chip_mem_alloc, 164 hd64465pcmcia_chip_mem_free, 165 hd64465pcmcia_chip_mem_map, 166 hd64465pcmcia_chip_mem_unmap, 167 hd64465pcmcia_chip_io_alloc, 168 hd64465pcmcia_chip_io_free, 169 hd64465pcmcia_chip_io_map, 170 hd64465pcmcia_chip_io_unmap, 171 hd64465pcmcia_chip_intr_establish, 172 hd64465pcmcia_chip_intr_disestablish, 173 hd64465pcmcia_chip_socket_enable, 174 hd64465pcmcia_chip_socket_disable, 175 }; 176 177 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 178 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 179 STATIC int hd64465pcmcia_print(void *, const char *); 180 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 181 182 struct cfattach hd64465pcmcia_ca = { 183 sizeof(struct hd64465pcmcia_softc), hd64465pcmcia_match, 184 hd64465pcmcia_attach 185 }; 186 187 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 188 /* hot plug */ 189 STATIC void hd64465pcmcia_create_event_thread(void *); 190 STATIC void hd64465pcmcia_event_thread(void *); 191 STATIC void __queue_event(struct hd64465pcmcia_channel *, 192 enum hd64465pcmcia_event_type); 193 /* interrupt handler */ 194 STATIC int hd64465pcmcia_intr(void *); 195 /* card status */ 196 STATIC enum hd64465pcmcia_event_type __detect_card(int); 197 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 198 /* bus width */ 199 STATIC void __sh_set_bus_width(int, int); 200 /* bus space access */ 201 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 202 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 203 204 #define DELAY_MS(x) delay((x) * 1000) 205 206 int 207 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 208 { 209 struct hd64465_attach_args *ha = aux; 210 211 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 212 } 213 214 void 215 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 216 { 217 struct hd64465_attach_args *ha = aux; 218 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 219 220 sc->sc_module_id = ha->ha_module_id; 221 222 printf("\n"); 223 224 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 225 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 226 227 if (sc->sc_area5 == NULL || sc->sc_area6 == NULL) { 228 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 229 if (sc->sc_area5) 230 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 231 if (sc->sc_area6) 232 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 233 234 return; 235 } 236 237 /* Channel 0/1 common CSC event queue */ 238 SIMPLEQ_INIT (&sc->sc_event_head); 239 kthread_create(hd64465pcmcia_create_event_thread, sc); 240 241 hd64465pcmcia_attach_channel(sc, 0); 242 hd64465pcmcia_attach_channel(sc, 1); 243 } 244 245 void 246 hd64465pcmcia_create_event_thread(void *arg) 247 { 248 struct hd64465pcmcia_softc *sc = arg; 249 int error; 250 251 error = kthread_create1(hd64465pcmcia_event_thread, sc, 252 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 253 254 KASSERT(error == 0); 255 } 256 257 void 258 hd64465pcmcia_event_thread(void *arg) 259 { 260 struct hd64465pcmcia_softc *sc = arg; 261 struct hd64465pcmcia_event *pe; 262 int s; 263 264 while (!sc->sc_shutdown) { 265 tsleep(sc, PWAIT, "CSC wait", 0); 266 s = splhigh(); 267 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 268 splx(s); 269 switch (pe->pe_type) { 270 default: 271 printf("%s: unknown event.\n", __FUNCTION__); 272 break; 273 case EVENT_INSERT: 274 DPRINTF("insert event.\n"); 275 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 276 break; 277 case EVENT_REMOVE: 278 DPRINTF("remove event.\n"); 279 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 280 DETACH_FORCE); 281 break; 282 } 283 s = splhigh(); 284 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe, pe_link); 285 pe->__queued = 0; 286 } 287 splx(s); 288 } 289 /* NOTREACHED */ 290 } 291 292 int 293 hd64465pcmcia_print(void *arg, const char *pnp) 294 { 295 296 if (pnp) 297 printf("pcmcia at %s", pnp); 298 299 return (UNCONF); 300 } 301 302 int 303 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 304 { 305 struct pcmciabus_attach_args *paa = aux; 306 struct hd64465pcmcia_channel *ch = 307 (struct hd64465pcmcia_channel *)paa->pch; 308 309 if (ch->ch_channel == 0) { 310 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 311 PCMCIABUSCF_CONTROLLER_DEFAULT && 312 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 313 return 0; 314 } else { 315 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 316 PCMCIABUSCF_CONTROLLER_DEFAULT && 317 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 318 return 0; 319 } 320 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 321 322 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 323 } 324 325 void 326 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 327 { 328 struct device *parent = (struct device *)sc; 329 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 330 struct pcmciabus_attach_args paa; 331 bus_addr_t baseaddr; 332 u_int8_t r; 333 int i; 334 335 ch->ch_parent = sc; 336 ch->ch_channel = channel; 337 338 /* 339 * Continuous 16-MB Area Mode 340 */ 341 /* set Continuous 16-MB Area Mode */ 342 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 343 r &= ~HD64461_PCCGCR_MMOD; 344 r |= HD64461_PCCGCR_MMOD_16M; 345 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 346 347 /* Attibute/Common memory extent */ 348 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 349 350 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 351 baseaddr, 0x01000000); /* 16MB */ 352 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 353 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 354 355 /* Common memory space extent */ 356 ch->ch_memsize = 0x01000000; 357 for (i = 0; i < MEMWIN_16M_MAX; i++) { 358 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 359 baseaddr + 0x01000000, ch->ch_memsize); 360 } 361 362 /* I/O port extent */ 363 ch->ch_iobase = 0; 364 ch->ch_iosize = 0x01000000; 365 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 366 baseaddr + 0x01000000 * 2, ch->ch_iosize); 367 368 /* Interrupt */ 369 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 370 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 371 372 paa.paa_busname = "pcmcia"; 373 paa.pch = (pcmcia_chipset_handle_t)ch; 374 paa.iobase = ch->ch_iobase; 375 paa.iosize = ch->ch_iosize; 376 377 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 378 hd64465pcmcia_submatch); 379 380 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 381 ch->ch_attached = 1; 382 pcmcia_card_attach(ch->ch_pcmcia); 383 } 384 } 385 386 int 387 hd64465pcmcia_intr(void *arg) 388 { 389 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 390 u_int32_t cscr; 391 u_int8_t r; 392 int ret = 0; 393 394 cscr = HD64461_PCCCSCR(ch->ch_channel); 395 r = hd64465_reg_read_1(cscr); 396 397 /* clear interrtupt (don't change power switch select) */ 398 hd64465_reg_write_1(cscr, r & ~0x40); 399 400 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 401 if (ch->ch_ih_card_func) { 402 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 403 } else { 404 DPRINTF("spurious IREQ interrupt.\n"); 405 } 406 } 407 408 if (r & HD64461_PCC0CSCR_P0CDC) 409 __queue_event(ch, __detect_card(ch->ch_channel)); 410 411 return (ret); 412 } 413 414 void 415 __queue_event(struct hd64465pcmcia_channel *ch, 416 enum hd64465pcmcia_event_type type) 417 { 418 struct hd64465pcmcia_event *pe, *pool; 419 struct hd64465pcmcia_softc *sc = ch->ch_parent; 420 int i; 421 int s = splhigh(); 422 423 if (type == EVENT_NONE) 424 goto out; 425 426 pe = 0; 427 pool = sc->sc_event_pool; 428 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 429 if (!pool[i].__queued) { 430 pe = &pool[i]; 431 break; 432 } 433 } 434 435 if (pe == 0) { 436 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 437 EVENT_QUEUE_MAX); 438 goto out; 439 } 440 441 if ((ch->ch_attached && (type == EVENT_INSERT)) || 442 (!ch->ch_attached && (type == EVENT_REMOVE))) { 443 DPRINTF("spurious CSC interrupt.\n"); 444 goto out; 445 } 446 447 ch->ch_attached = (type == EVENT_INSERT); 448 pe->__queued = 1; 449 pe->pe_type = type; 450 pe->pe_ch = ch; 451 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 452 wakeup(sc); 453 out: 454 splx(s); 455 } 456 457 /* 458 * Interface for pcmcia driver. 459 */ 460 /* 461 * Interrupt. 462 */ 463 void * 464 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 465 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 466 { 467 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 468 int channel = ch->ch_channel; 469 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 470 u_int8_t r; 471 int s = splhigh(); 472 473 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 474 ipl); 475 476 ch->ch_ih_card_func = ih_func; 477 ch->ch_ih_card_arg = ih_arg; 478 479 /* Enable card interrupt */ 480 r = hd64465_reg_read_1(cscier); 481 /* set level mode */ 482 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 483 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 484 hd64465_reg_write_1(cscier, r); 485 486 splx(s); 487 488 return (void *)ih_func; 489 } 490 491 void 492 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 493 { 494 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 495 int channel = ch->ch_channel; 496 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 497 int s = splhigh(); 498 u_int8_t r; 499 500 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 501 IPL_TTY); 502 503 /* Disable card interrupt */ 504 r = hd64465_reg_read_1(cscier); 505 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 506 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 507 hd64465_reg_write_1(cscier, r); 508 509 ch->ch_ih_card_func = 0; 510 511 splx(s); 512 } 513 514 /* 515 * Bus resources. 516 */ 517 int 518 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 519 struct pcmcia_mem_handle *pcmhp) 520 { 521 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 522 523 pcmhp->memt = ch->ch_memt; 524 pcmhp->addr = ch->ch_membase_addr; 525 pcmhp->memh = ch->ch_memh; 526 pcmhp->size = size; 527 pcmhp->realsize = size; 528 529 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 530 531 return (0); 532 } 533 534 void 535 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 536 struct pcmcia_mem_handle *pcmhp) 537 { 538 /* NO-OP */ 539 } 540 541 int 542 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 543 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 544 bus_size_t *offsetp, int *windowp) 545 { 546 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 547 struct hd64465pcmcia_window_cookie *cookie; 548 bus_addr_t ofs; 549 550 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 551 M_DEVBUF, M_NOWAIT); 552 KASSERT(cookie); 553 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 554 555 /* Address */ 556 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 557 cookie->wc_tag = ch->ch_memt; 558 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 559 size, &cookie->wc_handle) != 0) 560 goto bad; 561 562 *offsetp = card_addr; 563 cookie->wc_window = -1; 564 } else { 565 int window = card_addr / ch->ch_memsize; 566 KASSERT(window < MEMWIN_16M_MAX); 567 568 cookie->wc_tag = ch->ch_cmemt[window]; 569 ofs = card_addr - window * ch->ch_memsize; 570 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 571 &cookie->wc_handle) != 0) 572 goto bad; 573 574 /* XXX bogus. check window per common memory access. */ 575 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 576 *offsetp = ofs + 0x01000000; /* skip attribute area */ 577 cookie->wc_window = window; 578 } 579 cookie->wc_size = size; 580 *windowp = (int)cookie; 581 582 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 583 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 584 585 return (0); 586 bad: 587 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 588 free(cookie, M_DEVBUF); 589 590 return (1); 591 } 592 593 void 594 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 595 { 596 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 597 598 if (cookie->wc_window != -1) 599 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 600 cookie->wc_size); 601 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 602 free(cookie, M_DEVBUF); 603 } 604 605 int 606 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 607 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 608 { 609 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 610 611 if (start) { 612 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 613 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 614 return (1); 615 } 616 pcihp->addr = pcihp->ioh; 617 DPRINTF("map %#lx+%#lx\n", start, size); 618 } else { 619 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 620 ch->ch_iobase + ch->ch_iosize - 1, 621 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 622 DPRINTF("couldn't allocate %#lx\n", size); 623 return (1); 624 } 625 pcihp->flags = PCMCIA_IO_ALLOCATED; 626 } 627 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 628 629 pcihp->iot = ch->ch_iot; 630 pcihp->size = size; 631 632 return (0); 633 } 634 635 int 636 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 637 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 638 int *windowp) 639 { 640 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 641 #ifdef HD64465PCMCIA_DEBUG 642 static const char *width_names[] = { "auto", "io8", "io16" }; 643 #endif 644 645 __sh_set_bus_width(ch->ch_channel, width); 646 647 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 648 width_names[width]); 649 650 return (0); 651 } 652 653 void 654 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 655 struct pcmcia_io_handle *pcihp) 656 { 657 658 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 659 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 660 else 661 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 662 663 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 664 } 665 666 void 667 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 668 { 669 /* nothing to do */ 670 } 671 672 /* 673 * Enable/Disable 674 */ 675 void 676 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 677 { 678 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 679 int channel = ch->ch_channel; 680 bus_addr_t isr, gcr; 681 u_int8_t r; 682 int cardtype; 683 684 DPRINTF("enable channel %d\n", channel); 685 isr = HD64461_PCCISR(channel); 686 gcr = HD64461_PCCGCR(channel); 687 688 /* Set Common memory area #0. */ 689 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 690 691 /* Set the card type */ 692 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 693 694 r = hd64465_reg_read_1(gcr); 695 if (cardtype == PCMCIA_IFTYPE_IO) 696 r |= HD64461_PCC0GCR_P0PCCT; 697 else 698 r &= ~HD64461_PCC0GCR_P0PCCT; 699 hd64465_reg_write_1(gcr, r); 700 701 DPRINTF("OK.\n"); 702 } 703 704 void 705 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 706 { 707 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 708 int channel = ch->ch_channel; 709 710 /* dont' disable CSC interrupt */ 711 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 712 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 713 } 714 715 /* 716 * Card detect 717 */ 718 enum hd64465pcmcia_event_type 719 __detect_card(int channel) 720 { 721 u_int8_t r; 722 723 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 724 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 725 726 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 727 DPRINTF("remove\n"); 728 return EVENT_REMOVE; 729 } 730 if (r == 0) { 731 DPRINTF("insert\n"); 732 return EVENT_INSERT; 733 } 734 DPRINTF("transition\n"); 735 736 return (EVENT_NONE); 737 } 738 739 /* 740 * Memory window access ops. 741 */ 742 void 743 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 744 { 745 bus_addr_t a = HD64461_PCCGCR(channel); 746 u_int8_t r; 747 748 r = hd64465_reg_read_1(a); 749 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 750 751 switch (window) { 752 case MEMWIN_16M_COMMON_0: 753 break; 754 case MEMWIN_16M_COMMON_1: 755 r |= HD64461_PCCGCR_PA24; 756 break; 757 case MEMWIN_16M_COMMON_2: 758 r |= HD64461_PCCGCR_PA25; 759 break; 760 case MEMWIN_16M_COMMON_3: 761 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 762 break; 763 } 764 765 hd64465_reg_write_1(a, r); 766 } 767 768 /* 769 * SH interface. 770 */ 771 void 772 __sh_set_bus_width(int channel, int width) 773 { 774 u_int16_t r16; 775 776 r16 = _reg_read_2(SH4_BCR2); 777 #ifdef HD64465PCMCIA_DEBUG 778 dbg_bit_print_msg(r16, "BCR2"); 779 #endif 780 if (channel == 0) { 781 r16 &= ~((1 << 13)|(1 << 12)); 782 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 783 } else { 784 r16 &= ~((1 << 11)|(1 << 10)); 785 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 786 } 787 _reg_write_2(SH4_BCR2, r16); 788 } 789 790 vaddr_t 791 __sh_hd64465_map_2page(paddr_t pa) 792 { 793 static const u_int32_t mode[] = 794 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 795 vaddr_t va, v; 796 int i; 797 798 /* allocate kernel virtual */ 799 v = va = uvm_km_valloc(kernel_map, 0x03000000); 800 if (va == NULL) { 801 PRINTF("can't allocate virtual for paddr 0x%08x\n", 802 (unsigned)pa); 803 804 return (0); 805 } 806 807 /* map to physical addreess with specified memory type. */ 808 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 809 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 810 uvm_km_free(kernel_map, v, 0x03000000); 811 return (0); 812 } 813 } 814 815 return (v); 816 } 817 818 int 819 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 820 { 821 pt_entry_t *pte; 822 paddr_t epa; 823 824 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 825 ((sz & PAGE_MASK) == 0)); 826 827 epa = pa + sz; 828 while (pa < epa) { 829 if (pmap_enter(pmap_kernel(), va, pa, 830 VM_PROT_READ | VM_PROT_WRITE, PMAP_WIRED) != 0) { 831 PRINTF("can't map va 0x%08x -> pa 0x%08x\n", 832 (unsigned)va, (unsigned)pa); 833 return (1); 834 } 835 836 pte = kvtopte(va); 837 *pte &= ~PG_N; /* uncacheable */ 838 *pte |= flags; /* PTEA PCMCIA assistant bit */ 839 pmap_update_pg(va); 840 841 pa += NBPG; 842 va += NBPG; 843 } 844 845 pmap_update(pmap_kernel()); 846 847 return (0); 848 } 849
Indexes created Fri Oct 03 02:09:57 GMT 2025