hd64465pcmcia.c revision 1.7
1 /* $NetBSD: hd64465pcmcia.c,v 1.7 2002/09/27 03:17:56 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2001, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/malloc.h> 43 #include <sys/kthread.h> 44 #include <sys/boot_flag.h> 45 46 #include <uvm/uvm_extern.h> 47 48 #include <machine/bus.h> 49 #include <machine/intr.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <sh3/bscreg.h> 56 #include <sh3/mmu.h> 57 58 #include <hpcsh/dev/hd64465/hd64465reg.h> 59 #include <hpcsh/dev/hd64465/hd64465var.h> 60 #include <hpcsh/dev/hd64465/hd64465intcreg.h> 61 #include <hpcsh/dev/hd64461/hd64461pcmciareg.h> 62 63 #include "locators.h" 64 65 #ifdef HD64465PCMCIA_DEBUG 66 #define DPRINTF_ENABLE 67 #define DPRINTF_DEBUG hd64465pcmcia_debug 68 #endif 69 #include <machine/debug.h> 70 71 enum memory_window_16 { 72 MEMWIN_16M_COMMON_0, 73 MEMWIN_16M_COMMON_1, 74 MEMWIN_16M_COMMON_2, 75 MEMWIN_16M_COMMON_3, 76 }; 77 #define MEMWIN_16M_MAX 4 78 79 enum hd64465pcmcia_event_type { 80 EVENT_NONE, 81 EVENT_INSERT, 82 EVENT_REMOVE, 83 }; 84 #define EVENT_QUEUE_MAX 5 85 86 struct hd64465pcmcia_softc; /* forward declaration */ 87 88 struct hd64465pcmcia_window_cookie { 89 bus_space_tag_t wc_tag; 90 bus_space_handle_t wc_handle; 91 int wc_size; 92 int wc_window; 93 }; 94 95 struct hd64465pcmcia_channel { 96 struct hd64465pcmcia_softc *ch_parent; 97 struct device *ch_pcmcia; 98 int ch_channel; 99 100 /* memory space */ 101 bus_space_tag_t ch_memt; 102 bus_space_handle_t ch_memh; 103 bus_addr_t ch_membase_addr; 104 bus_size_t ch_memsize; 105 bus_space_tag_t ch_cmemt[MEMWIN_16M_MAX]; 106 107 /* I/O space */ 108 bus_space_tag_t ch_iot; 109 bus_addr_t ch_iobase; 110 bus_size_t ch_iosize; 111 112 /* card interrupt */ 113 int (*ch_ih_card_func)(void *); 114 void *ch_ih_card_arg; 115 int ch_attached; 116 }; 117 118 struct hd64465pcmcia_event { 119 int __queued; 120 enum hd64465pcmcia_event_type pe_type; 121 struct hd64465pcmcia_channel *pe_ch; 122 SIMPLEQ_ENTRY(hd64465pcmcia_event) pe_link; 123 }; 124 125 struct hd64465pcmcia_softc { 126 struct device sc_dev; 127 enum hd64465_module_id sc_module_id; 128 int sc_shutdown; 129 130 /* kv mapped Area 5, 6 */ 131 vaddr_t sc_area5; 132 vaddr_t sc_area6; 133 134 /* CSC event */ 135 struct proc *sc_event_thread; 136 struct hd64465pcmcia_event sc_event_pool[EVENT_QUEUE_MAX]; 137 SIMPLEQ_HEAD (, hd64465pcmcia_event) sc_event_head; 138 139 struct hd64465pcmcia_channel sc_ch[2]; 140 }; 141 142 STATIC int hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 143 struct pcmcia_mem_handle *); 144 STATIC void hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t, 145 struct pcmcia_mem_handle *); 146 STATIC int hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 147 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 148 STATIC void hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t, int); 149 STATIC int hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 150 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 151 STATIC void hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t, 152 struct pcmcia_io_handle *); 153 STATIC int hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 154 bus_size_t, struct pcmcia_io_handle *, int *); 155 STATIC void hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t, int); 156 STATIC void hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t); 157 STATIC void hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t); 158 STATIC void *hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t, 159 struct pcmcia_function *, int, int (*)(void *), void *); 160 STATIC void hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t, 161 void *); 162 163 STATIC struct pcmcia_chip_functions hd64465pcmcia_functions = { 164 hd64465pcmcia_chip_mem_alloc, 165 hd64465pcmcia_chip_mem_free, 166 hd64465pcmcia_chip_mem_map, 167 hd64465pcmcia_chip_mem_unmap, 168 hd64465pcmcia_chip_io_alloc, 169 hd64465pcmcia_chip_io_free, 170 hd64465pcmcia_chip_io_map, 171 hd64465pcmcia_chip_io_unmap, 172 hd64465pcmcia_chip_intr_establish, 173 hd64465pcmcia_chip_intr_disestablish, 174 hd64465pcmcia_chip_socket_enable, 175 hd64465pcmcia_chip_socket_disable, 176 }; 177 178 STATIC int hd64465pcmcia_match(struct device *, struct cfdata *, void *); 179 STATIC void hd64465pcmcia_attach(struct device *, struct device *, void *); 180 STATIC int hd64465pcmcia_print(void *, const char *); 181 STATIC int hd64465pcmcia_submatch(struct device *, struct cfdata *, void *); 182 183 struct cfattach hd64465pcmcia_ca = { 184 sizeof(struct hd64465pcmcia_softc), hd64465pcmcia_match, 185 hd64465pcmcia_attach 186 }; 187 188 STATIC void hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *, int); 189 /* hot plug */ 190 STATIC void hd64465pcmcia_create_event_thread(void *); 191 STATIC void hd64465pcmcia_event_thread(void *); 192 STATIC void __queue_event(struct hd64465pcmcia_channel *, 193 enum hd64465pcmcia_event_type); 194 /* interrupt handler */ 195 STATIC int hd64465pcmcia_intr(void *); 196 /* card status */ 197 STATIC enum hd64465pcmcia_event_type __detect_card(int); 198 STATIC void hd64465pcmcia_memory_window16_switch(int, enum memory_window_16); 199 /* bus width */ 200 STATIC void __sh_set_bus_width(int, int); 201 /* bus space access */ 202 STATIC int __sh_hd64465_map(vaddr_t, paddr_t, size_t, u_int32_t); 203 STATIC vaddr_t __sh_hd64465_map_2page(paddr_t); 204 205 #define DELAY_MS(x) delay((x) * 1000) 206 207 int 208 hd64465pcmcia_match(struct device *parent, struct cfdata *cf, void *aux) 209 { 210 struct hd64465_attach_args *ha = aux; 211 212 return (ha->ha_module_id == HD64465_MODULE_PCMCIA); 213 } 214 215 void 216 hd64465pcmcia_attach(struct device *parent, struct device *self, void *aux) 217 { 218 struct hd64465_attach_args *ha = aux; 219 struct hd64465pcmcia_softc *sc = (struct hd64465pcmcia_softc *)self; 220 221 sc->sc_module_id = ha->ha_module_id; 222 223 printf("\n"); 224 225 sc->sc_area5 = __sh_hd64465_map_2page(0x14000000); /* area 5 */ 226 sc->sc_area6 = __sh_hd64465_map_2page(0x18000000); /* area 6 */ 227 228 if (sc->sc_area5 == NULL || sc->sc_area6 == NULL) { 229 printf("%s: can't map memory.\n", sc->sc_dev.dv_xname); 230 if (sc->sc_area5) 231 uvm_km_free(kernel_map, sc->sc_area5, 0x03000000); 232 if (sc->sc_area6) 233 uvm_km_free(kernel_map, sc->sc_area6, 0x03000000); 234 235 return; 236 } 237 238 /* Channel 0/1 common CSC event queue */ 239 SIMPLEQ_INIT (&sc->sc_event_head); 240 kthread_create(hd64465pcmcia_create_event_thread, sc); 241 242 hd64465pcmcia_attach_channel(sc, 0); 243 hd64465pcmcia_attach_channel(sc, 1); 244 } 245 246 void 247 hd64465pcmcia_create_event_thread(void *arg) 248 { 249 struct hd64465pcmcia_softc *sc = arg; 250 int error; 251 252 error = kthread_create1(hd64465pcmcia_event_thread, sc, 253 &sc->sc_event_thread, "%s", sc->sc_dev.dv_xname); 254 255 KASSERT(error == 0); 256 } 257 258 void 259 hd64465pcmcia_event_thread(void *arg) 260 { 261 struct hd64465pcmcia_softc *sc = arg; 262 struct hd64465pcmcia_event *pe; 263 int s; 264 265 while (!sc->sc_shutdown) { 266 tsleep(sc, PWAIT, "CSC wait", 0); 267 s = splhigh(); 268 while ((pe = SIMPLEQ_FIRST(&sc->sc_event_head))) { 269 splx(s); 270 switch (pe->pe_type) { 271 default: 272 printf("%s: unknown event.\n", __FUNCTION__); 273 break; 274 case EVENT_INSERT: 275 DPRINTF("insert event.\n"); 276 pcmcia_card_attach(pe->pe_ch->ch_pcmcia); 277 break; 278 case EVENT_REMOVE: 279 DPRINTF("remove event.\n"); 280 pcmcia_card_detach(pe->pe_ch->ch_pcmcia, 281 DETACH_FORCE); 282 break; 283 } 284 s = splhigh(); 285 SIMPLEQ_REMOVE_HEAD(&sc->sc_event_head, pe_link); 286 pe->__queued = 0; 287 } 288 splx(s); 289 } 290 /* NOTREACHED */ 291 } 292 293 int 294 hd64465pcmcia_print(void *arg, const char *pnp) 295 { 296 297 if (pnp) 298 printf("pcmcia at %s", pnp); 299 300 return (UNCONF); 301 } 302 303 int 304 hd64465pcmcia_submatch(struct device *parent, struct cfdata *cf, void *aux) 305 { 306 struct pcmciabus_attach_args *paa = aux; 307 struct hd64465pcmcia_channel *ch = 308 (struct hd64465pcmcia_channel *)paa->pch; 309 310 if (ch->ch_channel == 0) { 311 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 312 PCMCIABUSCF_CONTROLLER_DEFAULT && 313 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 314 return 0; 315 } else { 316 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 317 PCMCIABUSCF_CONTROLLER_DEFAULT && 318 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 1) 319 return 0; 320 } 321 paa->pct = (pcmcia_chipset_tag_t)&hd64465pcmcia_functions; 322 323 return (config_match(parent, cf, aux)); 324 } 325 326 void 327 hd64465pcmcia_attach_channel(struct hd64465pcmcia_softc *sc, int channel) 328 { 329 struct device *parent = (struct device *)sc; 330 struct hd64465pcmcia_channel *ch = &sc->sc_ch[channel]; 331 struct pcmciabus_attach_args paa; 332 bus_addr_t baseaddr; 333 u_int8_t r; 334 int i; 335 336 ch->ch_parent = sc; 337 ch->ch_channel = channel; 338 339 /* 340 * Continuous 16-MB Area Mode 341 */ 342 /* set Continuous 16-MB Area Mode */ 343 r = hd64465_reg_read_1(HD64461_PCCGCR(channel)); 344 r &= ~HD64461_PCCGCR_MMOD; 345 r |= HD64461_PCCGCR_MMOD_16M; 346 hd64465_reg_write_1(HD64461_PCCGCR(channel), r); 347 348 /* Attibute/Common memory extent */ 349 baseaddr = (channel == 0) ? sc->sc_area6 : sc->sc_area5; 350 351 ch->ch_memt = bus_space_create(0, "PCMCIA attribute memory", 352 baseaddr, 0x01000000); /* 16MB */ 353 bus_space_alloc(ch->ch_memt, 0, 0x00ffffff, 0x0001000, 354 0x1000, 0x1000, 0, &ch->ch_membase_addr, &ch->ch_memh); 355 356 /* Common memory space extent */ 357 ch->ch_memsize = 0x01000000; 358 for (i = 0; i < MEMWIN_16M_MAX; i++) { 359 ch->ch_cmemt[i] = bus_space_create(0, "PCMCIA common memory", 360 baseaddr + 0x01000000, ch->ch_memsize); 361 } 362 363 /* I/O port extent */ 364 ch->ch_iobase = 0; 365 ch->ch_iosize = 0x01000000; 366 ch->ch_iot = bus_space_create(0, "PCMCIA I/O port", 367 baseaddr + 0x01000000 * 2, ch->ch_iosize); 368 369 /* Interrupt */ 370 hd64465_intr_establish(channel ? HD64465_PCC1 : HD64465_PCC0, 371 IST_LEVEL, IPL_TTY, hd64465pcmcia_intr, ch); 372 373 paa.paa_busname = "pcmcia"; 374 paa.pch = (pcmcia_chipset_handle_t)ch; 375 paa.iobase = ch->ch_iobase; 376 paa.iosize = ch->ch_iosize; 377 378 ch->ch_pcmcia = config_found_sm(parent, &paa, hd64465pcmcia_print, 379 hd64465pcmcia_submatch); 380 381 if (ch->ch_pcmcia && (__detect_card(ch->ch_channel) == EVENT_INSERT)) { 382 ch->ch_attached = 1; 383 pcmcia_card_attach(ch->ch_pcmcia); 384 } 385 } 386 387 int 388 hd64465pcmcia_intr(void *arg) 389 { 390 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)arg; 391 u_int32_t cscr; 392 u_int8_t r; 393 int ret = 0; 394 395 cscr = HD64461_PCCCSCR(ch->ch_channel); 396 r = hd64465_reg_read_1(cscr); 397 398 /* clear interrtupt (don't change power switch select) */ 399 hd64465_reg_write_1(cscr, r & ~0x40); 400 401 if (r & (0x60 | 0x04/* for memory mapped mode*/)) { 402 if (ch->ch_ih_card_func) { 403 ret = (*ch->ch_ih_card_func)(ch->ch_ih_card_arg); 404 } else { 405 DPRINTF("spurious IREQ interrupt.\n"); 406 } 407 } 408 409 if (r & HD64461_PCC0CSCR_P0CDC) 410 __queue_event(ch, __detect_card(ch->ch_channel)); 411 412 return (ret); 413 } 414 415 void 416 __queue_event(struct hd64465pcmcia_channel *ch, 417 enum hd64465pcmcia_event_type type) 418 { 419 struct hd64465pcmcia_event *pe, *pool; 420 struct hd64465pcmcia_softc *sc = ch->ch_parent; 421 int i; 422 int s = splhigh(); 423 424 if (type == EVENT_NONE) 425 goto out; 426 427 pe = 0; 428 pool = sc->sc_event_pool; 429 for (i = 0; i < EVENT_QUEUE_MAX; i++) { 430 if (!pool[i].__queued) { 431 pe = &pool[i]; 432 break; 433 } 434 } 435 436 if (pe == 0) { 437 printf("%s: event FIFO overflow (max %d).\n", __FUNCTION__, 438 EVENT_QUEUE_MAX); 439 goto out; 440 } 441 442 if ((ch->ch_attached && (type == EVENT_INSERT)) || 443 (!ch->ch_attached && (type == EVENT_REMOVE))) { 444 DPRINTF("spurious CSC interrupt.\n"); 445 goto out; 446 } 447 448 ch->ch_attached = (type == EVENT_INSERT); 449 pe->__queued = 1; 450 pe->pe_type = type; 451 pe->pe_ch = ch; 452 SIMPLEQ_INSERT_TAIL(&sc->sc_event_head, pe, pe_link); 453 wakeup(sc); 454 out: 455 splx(s); 456 } 457 458 /* 459 * Interface for pcmcia driver. 460 */ 461 /* 462 * Interrupt. 463 */ 464 void * 465 hd64465pcmcia_chip_intr_establish(pcmcia_chipset_handle_t pch, 466 struct pcmcia_function *pf, int ipl, int (*ih_func)(void *), void *ih_arg) 467 { 468 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 469 int channel = ch->ch_channel; 470 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 471 u_int8_t r; 472 int s = splhigh(); 473 474 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 475 ipl); 476 477 ch->ch_ih_card_func = ih_func; 478 ch->ch_ih_card_arg = ih_arg; 479 480 /* Enable card interrupt */ 481 r = hd64465_reg_read_1(cscier); 482 /* set level mode */ 483 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 484 r |= HD64461_PCC0CSCIER_P0IREQE_LEVEL; 485 hd64465_reg_write_1(cscier, r); 486 487 splx(s); 488 489 return (void *)ih_func; 490 } 491 492 void 493 hd64465pcmcia_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 494 { 495 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 496 int channel = ch->ch_channel; 497 bus_addr_t cscier = HD64461_PCCCSCIER(channel); 498 int s = splhigh(); 499 u_int8_t r; 500 501 hd6446x_intr_priority(ch->ch_channel == 0 ? HD64465_PCC0 : HD64465_PCC1, 502 IPL_TTY); 503 504 /* Disable card interrupt */ 505 r = hd64465_reg_read_1(cscier); 506 r &= ~HD64461_PCC0CSCIER_P0IREQE_MASK; 507 r |= HD64461_PCC0CSCIER_P0IREQE_NONE; 508 hd64465_reg_write_1(cscier, r); 509 510 ch->ch_ih_card_func = 0; 511 512 splx(s); 513 } 514 515 /* 516 * Bus resources. 517 */ 518 int 519 hd64465pcmcia_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, 520 struct pcmcia_mem_handle *pcmhp) 521 { 522 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 523 524 pcmhp->memt = ch->ch_memt; 525 pcmhp->addr = ch->ch_membase_addr; 526 pcmhp->memh = ch->ch_memh; 527 pcmhp->size = size; 528 pcmhp->realsize = size; 529 530 DPRINTF("base 0x%08lx size %#lx\n", pcmhp->addr, size); 531 532 return (0); 533 } 534 535 void 536 hd64465pcmcia_chip_mem_free(pcmcia_chipset_handle_t pch, 537 struct pcmcia_mem_handle *pcmhp) 538 { 539 /* NO-OP */ 540 } 541 542 int 543 hd64465pcmcia_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, 544 bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, 545 bus_size_t *offsetp, int *windowp) 546 { 547 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 548 struct hd64465pcmcia_window_cookie *cookie; 549 bus_addr_t ofs; 550 551 cookie = malloc(sizeof(struct hd64465pcmcia_window_cookie), 552 M_DEVBUF, M_NOWAIT); 553 KASSERT(cookie); 554 memset(cookie, 0, sizeof(struct hd64465pcmcia_window_cookie)); 555 556 /* Address */ 557 if ((kind & ~PCMCIA_WIDTH_MEM_MASK) == PCMCIA_MEM_ATTR) { 558 cookie->wc_tag = ch->ch_memt; 559 if (bus_space_subregion(ch->ch_memt, ch->ch_memh, card_addr, 560 size, &cookie->wc_handle) != 0) 561 goto bad; 562 563 *offsetp = card_addr; 564 cookie->wc_window = -1; 565 } else { 566 int window = card_addr / ch->ch_memsize; 567 KASSERT(window < MEMWIN_16M_MAX); 568 569 cookie->wc_tag = ch->ch_cmemt[window]; 570 ofs = card_addr - window * ch->ch_memsize; 571 if (bus_space_map(cookie->wc_tag, ofs, size, 0, 572 &cookie->wc_handle) != 0) 573 goto bad; 574 575 /* XXX bogus. check window per common memory access. */ 576 hd64465pcmcia_memory_window16_switch(ch->ch_channel, window); 577 *offsetp = ofs + 0x01000000; /* skip attribute area */ 578 cookie->wc_window = window; 579 } 580 cookie->wc_size = size; 581 *windowp = (int)cookie; 582 583 DPRINTF("(%s) %#lx+%#lx-> %#lx+%#lx\n", kind == PCMCIA_MEM_ATTR ? 584 "attribute" : "common", ch->ch_memh, card_addr, *offsetp, size); 585 586 return (0); 587 bad: 588 DPRINTF("%#lx-%#lx map failed.\n", card_addr, size); 589 free(cookie, M_DEVBUF); 590 591 return (1); 592 } 593 594 void 595 hd64465pcmcia_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 596 { 597 struct hd64465pcmcia_window_cookie *cookie = (void *)window; 598 599 if (cookie->wc_window != -1) 600 bus_space_unmap(cookie->wc_tag, cookie->wc_handle, 601 cookie->wc_size); 602 DPRINTF("%#lx-%#x\n", cookie->wc_handle, cookie->wc_size); 603 free(cookie, M_DEVBUF); 604 } 605 606 int 607 hd64465pcmcia_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, 608 bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 609 { 610 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 611 612 if (start) { 613 if (bus_space_map(ch->ch_iot, start, size, 0, &pcihp->ioh)) { 614 DPRINTF("couldn't map %#lx+%#lx\n", start, size); 615 return (1); 616 } 617 pcihp->addr = pcihp->ioh; 618 DPRINTF("map %#lx+%#lx\n", start, size); 619 } else { 620 if (bus_space_alloc(ch->ch_iot, ch->ch_iobase, 621 ch->ch_iobase + ch->ch_iosize - 1, 622 size, align, 0, 0, &pcihp->addr, &pcihp->ioh)) { 623 DPRINTF("couldn't allocate %#lx\n", size); 624 return (1); 625 } 626 pcihp->flags = PCMCIA_IO_ALLOCATED; 627 } 628 DPRINTF("%#lx from %#lx\n", size, pcihp->addr); 629 630 pcihp->iot = ch->ch_iot; 631 pcihp->size = size; 632 633 return (0); 634 } 635 636 int 637 hd64465pcmcia_chip_io_map(pcmcia_chipset_handle_t pch, int width, 638 bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, 639 int *windowp) 640 { 641 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 642 #ifdef HD64465PCMCIA_DEBUG 643 static const char *width_names[] = { "auto", "io8", "io16" }; 644 #endif 645 646 __sh_set_bus_width(ch->ch_channel, width); 647 648 DPRINTF("%#lx:%#lx+%#lx %s\n", pcihp->ioh, offset, size, 649 width_names[width]); 650 651 return (0); 652 } 653 654 void 655 hd64465pcmcia_chip_io_free(pcmcia_chipset_handle_t pch, 656 struct pcmcia_io_handle *pcihp) 657 { 658 659 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 660 bus_space_free(pcihp->iot, pcihp->ioh, pcihp->size); 661 else 662 bus_space_unmap(pcihp->iot, pcihp->ioh, pcihp->size); 663 664 DPRINTF("%#lx+%#lx\n", pcihp->ioh, pcihp->size); 665 } 666 667 void 668 hd64465pcmcia_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 669 { 670 /* nothing to do */ 671 } 672 673 /* 674 * Enable/Disable 675 */ 676 void 677 hd64465pcmcia_chip_socket_enable(pcmcia_chipset_handle_t pch) 678 { 679 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 680 int channel = ch->ch_channel; 681 bus_addr_t isr, gcr; 682 u_int8_t r; 683 int cardtype; 684 685 DPRINTF("enable channel %d\n", channel); 686 isr = HD64461_PCCISR(channel); 687 gcr = HD64461_PCCGCR(channel); 688 689 /* Set Common memory area #0. */ 690 hd64465pcmcia_memory_window16_switch(channel, MEMWIN_16M_COMMON_0); 691 692 /* Set the card type */ 693 cardtype = pcmcia_card_gettype(ch->ch_pcmcia); 694 695 r = hd64465_reg_read_1(gcr); 696 if (cardtype == PCMCIA_IFTYPE_IO) 697 r |= HD64461_PCC0GCR_P0PCCT; 698 else 699 r &= ~HD64461_PCC0GCR_P0PCCT; 700 hd64465_reg_write_1(gcr, r); 701 702 DPRINTF("OK.\n"); 703 } 704 705 void 706 hd64465pcmcia_chip_socket_disable(pcmcia_chipset_handle_t pch) 707 { 708 struct hd64465pcmcia_channel *ch = (struct hd64465pcmcia_channel *)pch; 709 int channel = ch->ch_channel; 710 711 /* dont' disable CSC interrupt */ 712 hd64465_reg_write_1(HD64461_PCCCSCIER(channel), HD64461_PCCCSCIER_CDE); 713 hd64465_reg_write_1(HD64461_PCCCSCR(channel), 0); 714 } 715 716 /* 717 * Card detect 718 */ 719 enum hd64465pcmcia_event_type 720 __detect_card(int channel) 721 { 722 u_int8_t r; 723 724 r = hd64465_reg_read_1(HD64461_PCCISR(channel)) & 725 (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1); 726 727 if (r == (HD64461_PCCISR_CD2 | HD64461_PCCISR_CD1)) { 728 DPRINTF("remove\n"); 729 return EVENT_REMOVE; 730 } 731 if (r == 0) { 732 DPRINTF("insert\n"); 733 return EVENT_INSERT; 734 } 735 DPRINTF("transition\n"); 736 737 return (EVENT_NONE); 738 } 739 740 /* 741 * Memory window access ops. 742 */ 743 void 744 hd64465pcmcia_memory_window16_switch(int channel, enum memory_window_16 window) 745 { 746 bus_addr_t a = HD64461_PCCGCR(channel); 747 u_int8_t r; 748 749 r = hd64465_reg_read_1(a); 750 r &= ~(HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 751 752 switch (window) { 753 case MEMWIN_16M_COMMON_0: 754 break; 755 case MEMWIN_16M_COMMON_1: 756 r |= HD64461_PCCGCR_PA24; 757 break; 758 case MEMWIN_16M_COMMON_2: 759 r |= HD64461_PCCGCR_PA25; 760 break; 761 case MEMWIN_16M_COMMON_3: 762 r |= (HD64461_PCCGCR_PA25 | HD64461_PCCGCR_PA24); 763 break; 764 } 765 766 hd64465_reg_write_1(a, r); 767 } 768 769 /* 770 * SH interface. 771 */ 772 void 773 __sh_set_bus_width(int channel, int width) 774 { 775 u_int16_t r16; 776 777 r16 = _reg_read_2(SH4_BCR2); 778 #ifdef HD64465PCMCIA_DEBUG 779 dbg_bit_print_msg(r16, "BCR2"); 780 #endif 781 if (channel == 0) { 782 r16 &= ~((1 << 13)|(1 << 12)); 783 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 12 : 13); 784 } else { 785 r16 &= ~((1 << 11)|(1 << 10)); 786 r16 |= 1 << (width == PCMCIA_WIDTH_IO8 ? 10 : 11); 787 } 788 _reg_write_2(SH4_BCR2, r16); 789 } 790 791 vaddr_t 792 __sh_hd64465_map_2page(paddr_t pa) 793 { 794 static const u_int32_t mode[] = 795 { _PG_PCMCIA_ATTR16, _PG_PCMCIA_MEM16, _PG_PCMCIA_IO }; 796 vaddr_t va, v; 797 int i; 798 799 /* allocate kernel virtual */ 800 v = va = uvm_km_valloc(kernel_map, 0x03000000); 801 if (va == NULL) { 802 PRINTF("can't allocate virtual for paddr 0x%08x\n", 803 (unsigned)pa); 804 805 return (0); 806 } 807 808 /* map to physical addreess with specified memory type. */ 809 for (i = 0; i < 3; i++, pa += 0x01000000, va += 0x01000000) { 810 if (__sh_hd64465_map(va, pa, 0x2000, mode[i]) != 0) { 811 uvm_km_free(kernel_map, v, 0x03000000); 812 return (0); 813 } 814 } 815 816 return (v); 817 } 818 819 int 820 __sh_hd64465_map(vaddr_t va, paddr_t pa, size_t sz, u_int32_t flags) 821 { 822 pt_entry_t *pte; 823 paddr_t epa; 824 825 KDASSERT(((pa & PAGE_MASK) == 0) && ((va & PAGE_MASK) == 0) && 826 ((sz & PAGE_MASK) == 0)); 827 828 epa = pa + sz; 829 while (pa < epa) { 830 pmap_kenter_pa(va, pa, VM_PROT_READ | VM_PROT_WRITE); 831 pte = __pmap_kpte_lookup(va); 832 KDASSERT(pte); 833 *pte |= flags; /* PTEA PCMCIA assistant bit */ 834 sh_tlb_update(0, va, *pte); 835 pa += NBPG; 836 va += NBPG; 837 } 838 839 return (0); 840 } 841
Indexes created Fri Oct 03 02:09:57 GMT 2025