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hd64465reg.h revision 1.1
      1  1.1  uch /*	$NetBSD: hd64465reg.h,v 1.1 2002/02/11 17:27:16 uch Exp $	*/
      2  1.1  uch 
      3  1.1  uch /*-
      4  1.1  uch  * Copyright (c) 2002 The NetBSD Foundation, Inc.
      5  1.1  uch  * All rights reserved.
      6  1.1  uch  *
      7  1.1  uch  * This code is derived from software contributed to The NetBSD Foundation
      8  1.1  uch  * by UCHIYAMA Yasushi.
      9  1.1  uch  *
     10  1.1  uch  * Redistribution and use in source and binary forms, with or without
     11  1.1  uch  * modification, are permitted provided that the following conditions
     12  1.1  uch  * are met:
     13  1.1  uch  * 1. Redistributions of source code must retain the above copyright
     14  1.1  uch  *    notice, this list of conditions and the following disclaimer.
     15  1.1  uch  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1  uch  *    notice, this list of conditions and the following disclaimer in the
     17  1.1  uch  *    documentation and/or other materials provided with the distribution.
     18  1.1  uch  * 3. All advertising materials mentioning features or use of this software
     19  1.1  uch  *    must display the following acknowledgement:
     20  1.1  uch  *        This product includes software developed by the NetBSD
     21  1.1  uch  *        Foundation, Inc. and its contributors.
     22  1.1  uch  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  1.1  uch  *    contributors may be used to endorse or promote products derived
     24  1.1  uch  *    from this software without specific prior written permission.
     25  1.1  uch  *
     26  1.1  uch  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  1.1  uch  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  1.1  uch  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  1.1  uch  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  1.1  uch  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  1.1  uch  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  1.1  uch  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  1.1  uch  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  1.1  uch  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  1.1  uch  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  1.1  uch  * POSSIBILITY OF SUCH DAMAGE.
     37  1.1  uch  */
     38  1.1  uch 
     39  1.1  uch /*
     40  1.1  uch  * HD64465 power managerment and system configuration register.
     41  1.1  uch  */
     42  1.1  uch /* System Module Standby Register */
     43  1.1  uch #define HD64465_SMSCR		0xb0000000
     44  1.1  uch #define   SMSCR_PS2ST		  0x4000
     45  1.1  uch #define   SMSCR_ADCST		  0x1000
     46  1.1  uch #define   SMSCR_UARTST		  0x0800
     47  1.1  uch #define   SMSCR_SCDIST		  0x0200
     48  1.1  uch #define   SMSCR_PPST		  0x0100
     49  1.1  uch #define   SMSCR_PC0ST		  0x0040
     50  1.1  uch #define   SMSCR_PC1ST		  0x0020
     51  1.1  uch #define   SMSCR_AFEST		  0x0010
     52  1.1  uch #define   SMSCR_TM0ST		  0x0008
     53  1.1  uch #define   SMSCR_TM1ST		  0x0004
     54  1.1  uch #define   SMSCR_IRDAST		  0x0002
     55  1.1  uch #define   SMSCR_KBCST		  0x0001
     56  1.1  uch 
     57  1.1  uch /* System Configuration Register */
     58  1.1  uch #define HD64465_SCONFR		0xb0000002
     59  1.1  uch /* System Bus Control Register */
     60  1.1  uch #define HD64465_SBCR		0xb0000004
     61  1.1  uch /* System Peripheral Clock Control Register */
     62  1.1  uch #define HD64465_SPCCR		0xb0000006
     63  1.1  uch #define   SPCCR_ADCCLK		  0x8000
     64  1.1  uch #define   SPCCR_UARTCLK		  0x2000
     65  1.1  uch #define   SPCCR_PPCLK		  0x1000
     66  1.1  uch #define   SPCCR_FIRCLK		  0x0800
     67  1.1  uch #define   SPCCR_SIRCLK		  0x0400
     68  1.1  uch #define   SPCCR_SCDICLK		  0x0200
     69  1.1  uch #define   SPCCR_KBCCLK		  0x0100
     70  1.1  uch #define   SPCCR_USBCLK		  0x0080
     71  1.1  uch #define   SPCCR_AFECLK		  0x0040
     72  1.1  uch #define   SPCCR_UCKOSC		  0x0002
     73  1.1  uch #define   SPCCR_AFEOSC		  0x0001
     74  1.1  uch 
     75  1.1  uch /* System Peripheral S/W Reset Control Register */
     76  1.1  uch #define HD64465_SPSRCR		0xb0000008
     77  1.1  uch /* System PLL Control Register */
     78  1.1  uch #define HD64465_SPLLCR		0xb000000a
     79  1.1  uch /* System Revision Register */
     80  1.1  uch #define HD64465_SRR		0xb000000c
     81  1.1  uch /* System Test Mode Control Register */
     82  1.1  uch #define HD64465_STMCR		0xb000000e
     83  1.1  uch /* System Device ID Register */
     84  1.1  uch #define HD64465_SDIDR		0xb0000010	/* ro 0x8122 */
     85  1.1  uch /* System Debug Port Control Register */
     86  1.1  uch #define HD64465_SDPCR		0xb0000ff0
     87