hd6446xintc.c revision 1.1 1 1.1 uch /* $NetBSD: hd6446xintc.c,v 1.1 2002/03/28 15:27:04 uch Exp $ */
2 1.1 uch
3 1.1 uch /*-
4 1.1 uch * Copyright (c) 2002 The NetBSD Foundation, Inc.
5 1.1 uch * All rights reserved.
6 1.1 uch *
7 1.1 uch * This code is derived from software contributed to The NetBSD Foundation
8 1.1 uch * by UCHIYAMA Yasushi.
9 1.1 uch *
10 1.1 uch * Redistribution and use in source and binary forms, with or without
11 1.1 uch * modification, are permitted provided that the following conditions
12 1.1 uch * are met:
13 1.1 uch * 1. Redistributions of source code must retain the above copyright
14 1.1 uch * notice, this list of conditions and the following disclaimer.
15 1.1 uch * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 uch * notice, this list of conditions and the following disclaimer in the
17 1.1 uch * documentation and/or other materials provided with the distribution.
18 1.1 uch * 3. All advertising materials mentioning features or use of this software
19 1.1 uch * must display the following acknowledgement:
20 1.1 uch * This product includes software developed by the NetBSD
21 1.1 uch * Foundation, Inc. and its contributors.
22 1.1 uch * 4. Neither the name of The NetBSD Foundation nor the names of its
23 1.1 uch * contributors may be used to endorse or promote products derived
24 1.1 uch * from this software without specific prior written permission.
25 1.1 uch *
26 1.1 uch * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 1.1 uch * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 1.1 uch * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 1.1 uch * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 1.1 uch * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 1.1 uch * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 1.1 uch * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 1.1 uch * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 1.1 uch * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 1.1 uch * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 1.1 uch * POSSIBILITY OF SUCH DAMAGE.
37 1.1 uch */
38 1.1 uch
39 1.1 uch #include <sys/param.h>
40 1.1 uch #include <sys/systm.h>
41 1.1 uch
42 1.1 uch #include <sh3/devreg.h>
43 1.1 uch #include <hpcsh/dev/hd6446x/hd6446xintcvar.h>
44 1.1 uch #include <hpcsh/dev/hd6446x/hd6446xintcreg.h>
45 1.1 uch
46 1.1 uch struct hd6446x_intrhand hd6446x_intrhand[_HD6446X_INTR_N];
47 1.1 uch u_int16_t hd6446x_imask[_IPL_N];
48 1.1 uch u_int16_t hd6446x_ienable;
49 1.1 uch void hd6446x_intr_priority_update(void);
50 1.1 uch
51 1.1 uch void
52 1.1 uch hd6446x_intr_init()
53 1.1 uch {
54 1.1 uch
55 1.1 uch /* Initialize interrupt priority masks. */
56 1.1 uch hd6446x_intr_priority_update();
57 1.1 uch }
58 1.1 uch
59 1.1 uch void *
60 1.1 uch hd6446x_intr_establish(int irq, int mode, int level,
61 1.1 uch int (*func)(void *), void *arg)
62 1.1 uch {
63 1.1 uch struct hd6446x_intrhand *hh = &hd6446x_intrhand[ffs(irq) - 1];
64 1.1 uch u_int16_t r;
65 1.1 uch int s;
66 1.1 uch
67 1.1 uch s = splhigh();
68 1.1 uch
69 1.1 uch /* Register interrupt handler */
70 1.1 uch hh->hh_func = func;
71 1.1 uch hh->hh_arg = arg;
72 1.1 uch hh->hh_ipl = level << 4;
73 1.1 uch hh->hh_imask = irq;
74 1.1 uch hd6446x_ienable |= hh->hh_imask;
75 1.1 uch
76 1.1 uch /* Update interrupt priority masks. */
77 1.1 uch hd6446x_intr_priority_update();
78 1.1 uch
79 1.1 uch /* Enable interrupt */
80 1.1 uch r = _reg_read_2(HD6446X_NIMR);
81 1.1 uch r &= ~hh->hh_imask;
82 1.1 uch _reg_write_2(HD6446X_NIMR, r);
83 1.1 uch
84 1.1 uch splx(s);
85 1.1 uch
86 1.1 uch return (hh);
87 1.1 uch }
88 1.1 uch
89 1.1 uch void
90 1.1 uch hd6446x_intr_disestablish(void *handle)
91 1.1 uch {
92 1.1 uch struct hd6446x_intrhand *hh = handle;
93 1.1 uch u_int16_t r;
94 1.1 uch int s;
95 1.1 uch
96 1.1 uch s = splhigh();
97 1.1 uch
98 1.1 uch /* Disable interrupt */
99 1.1 uch r = _reg_read_2(HD6446X_NIMR);
100 1.1 uch r |= hh->hh_imask;
101 1.1 uch _reg_write_2(HD6446X_NIMR, r);
102 1.1 uch
103 1.1 uch /* Update interrupt priority masks */
104 1.1 uch hd6446x_ienable &= ~hh->hh_imask;
105 1.1 uch memset(hh, 0, sizeof(*hh));
106 1.1 uch hd6446x_intr_priority_update();
107 1.1 uch
108 1.1 uch splx(s);
109 1.1 uch }
110 1.1 uch
111 1.1 uch void
112 1.1 uch hd6446x_intr_priority(int irq, int level)
113 1.1 uch {
114 1.1 uch struct hd6446x_intrhand *hh = &hd6446x_intrhand[ffs(irq) - 1];
115 1.1 uch int s;
116 1.1 uch
117 1.1 uch KDASSERT(hh->hh_func != NULL);
118 1.1 uch s = splhigh();
119 1.1 uch hh->hh_ipl = level << 4;
120 1.1 uch hd6446x_intr_priority_update();
121 1.1 uch splx(s);
122 1.1 uch }
123 1.1 uch
124 1.1 uch void
125 1.1 uch hd6446x_intr_priority_update()
126 1.1 uch {
127 1.1 uch struct hd6446x_intrhand *hh;
128 1.1 uch int irq, ipl;
129 1.1 uch u_int16_t mask;
130 1.1 uch
131 1.1 uch /* I assume interrupt level is splhigh */
132 1.1 uch for (ipl = 0; ipl < _IPL_N; ipl++) {
133 1.1 uch hh = hd6446x_intrhand;
134 1.1 uch mask = 0;
135 1.1 uch for (irq = 0; irq < _HD6446X_INTR_N; irq++, hh++) {
136 1.1 uch if (hh->hh_func == NULL)
137 1.1 uch continue;
138 1.1 uch if (hh->hh_ipl == (ipl << 4))
139 1.1 uch mask |= 1 << irq;
140 1.1 uch }
141 1.1 uch hd6446x_imask[ipl] = mask | ~hd6446x_ienable;
142 1.1 uch }
143 1.1 uch
144 1.1 uch for (ipl = 1; ipl < _IPL_N; ipl++)
145 1.1 uch hd6446x_imask[ipl] |= hd6446x_imask[ipl - 1];
146 1.1 uch }
147