j6x0lcd.c revision 1.3.2.3
1 /* $NetBSD: j6x0lcd.c,v 1.3.2.3 2004/09/18 14:35:07 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Valeriy E. Ushakov 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: j6x0lcd.c,v 1.3.2.3 2004/09/18 14:35:07 skrll Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/device.h> 36 #include <sys/malloc.h> 37 #include <sys/systm.h> 38 #include <sys/callout.h> 39 #ifdef GPROF 40 #include <sys/gmon.h> 41 #endif 42 43 #include <machine/platid.h> 44 #include <machine/platid_mask.h> 45 46 #include <machine/config_hook.h> 47 48 #include <sh3/dacreg.h> 49 #include <hpcsh/dev/hd64461/hd64461var.h> /* XXX: for hd64461_reg_read_2 &c */ 50 #include <hpcsh/dev/hd64461/hd64461reg.h> 51 #include <hpcsh/dev/hd64461/hd64461gpioreg.h> 52 53 54 /* 55 * LCD power: controlled by pin 0 in HD64461 GPIO port B. 56 * 0 - power on 57 * 1 - power off 58 */ 59 #define HD64461_GPBDR_J6X0LCD_OFF 0x01 60 61 #define HD64461_GPBCR_J6X0LCD_OFF_MASK 0xfffc 62 #define HD64461_GPBCR_J6X0LCD_OFF_BITS 0x0001 63 64 65 /* 66 * LCD brightness: controlled by DAC channel 0. Larger channel values 67 * mean dimmer. Values smaller (i.e. brighter) then 0x5e seems to 68 * result in no visible changes. 69 */ 70 #define J6X0LCD_BRIGHTNESS_DA_MAX 0x5e 71 #define J6X0LCD_BRIGHTNESS_DA_MIN 0xff 72 73 #define J6X0LCD_DA_TO_BRIGHTNESS(da) \ 74 (J6X0LCD_BRIGHTNESS_DA_MIN - (da)) 75 76 #define J6X0LCD_BRIGHTNESS_TO_DA(br) \ 77 (J6X0LCD_BRIGHTNESS_DA_MIN - (br)) 78 79 #define J6X0LCD_BRIGHTNESS_MAX \ 80 J6X0LCD_DA_TO_BRIGHTNESS(J6X0LCD_BRIGHTNESS_DA_MAX) 81 82 /* convenience macro to accesses DAC registers */ 83 #define DAC_(x) (*((volatile uint8_t *)SH7709_DA ## x)) 84 85 86 /* 87 * LCD contrast: controlled by pins 6,5,4,3 HD64461 GPIO port B. 88 * 6th is the least significant bit, 3rd is the most significant. 89 * The bits are inverted: .1111... = 0, .0111... = 1, etc. 90 * 91 * We control the contrast value by setting bits in the data register 92 * to all ones, and changing the mode of the bits in the control 93 * register, keeping "ones" in gpio output mode (1), and switching 94 * "zeros" to input mode (3). This is what WinCE also does. 95 * 96 * Alternative method is to set the mode of all bits to gpio output 97 * mode and then change the bits in the data register. This method 98 * results in significantly less contrast screen for the same values. 99 * E.g., WinCE default contrast value is 11 (in our numbering, 23 in 100 * WinCE's) - which is fine in the "tweak the control register" 101 * method, but is very blurry in the "tweak the data register" method. 102 * Subjectively, 15 in the "tweak control" method looks like 7 in the 103 * "tweak data" method. 104 * 105 * May be it's possible to control a wider range of contrast by 106 * combining the two methods, but values above 7 in the "tweak data" 107 * method are so blurry that they are next to unusable in practice. 108 */ 109 #define J6X0LCD_CONTRAST_MAX 15 110 111 #define HD64461_GPBDR_J6X0LCD_CONTRAST_MASK 0x87 112 #define HD64461_GPBDR_J6X0LCD_CONTRAST_BITS 0x78 113 114 #if 0 115 /* "tweak data" */ 116 static uint8_t j6x0lcd_contrast_data_bits[] = { 117 0x78, 0x38, 0x58, 0x18, 0x68, 0x28, 0x48, 0x08, 118 0x70, 0x30, 0x50, 0x10, 0x60, 0x20, 0x40, 0x00 119 }; 120 #endif 121 122 #define HD64461_GPBCR_J6X0LCD_CONTRAST_MASK 0xc03f 123 #define HD64461_GPBCR_J6X0LCD_CONTRAST_BITS 0x1540 124 125 /* "tweak control" */ 126 static uint16_t j6x0lcd_contrast_control_bits[] = { 127 0x1540, 0x3540, 0x1d40, 0x3d40, 0x1740, 0x3740, 0x1f40, 0x3f40, 128 0x15c0, 0x35c0, 0x1dc0, 0x3dc0, 0x17c0, 0x37c0, 0x1fc0, 0x3fc0 129 }; 130 131 132 struct j6x0lcd_softc { 133 struct device sc_dev; 134 int sc_brightness; 135 int sc_contrast; 136 }; 137 138 static int j6x0lcd_match(struct device *, struct cfdata *, void *); 139 static void j6x0lcd_attach(struct device *, struct device *, void *); 140 141 CFATTACH_DECL(j6x0lcd, sizeof(struct j6x0lcd_softc), 142 j6x0lcd_match, j6x0lcd_attach, NULL, NULL); 143 144 145 static int j6x0lcd_param(void *, int, long, void *); 146 static int j6x0lcd_power(void *, int, long, void *); 147 148 149 static int 150 j6x0lcd_match(struct device *parent, struct cfdata *cfp, void *aux) 151 { 152 153 /* 154 * XXX: does platid_mask_MACH_HP_LX matches _JORNADA_6XX too? 155 * Is 620 wired similarly? 156 */ 157 if (!platid_match(&platid, &platid_mask_MACH_HP_JORNADA_6XX)) 158 return (0); 159 160 if (strcmp(cfp->cf_name, "j6x0lcd") != 0) 161 return (0); 162 163 return (1); 164 } 165 166 167 static void 168 j6x0lcd_attach(struct device *parent, struct device *self, void *aux) 169 { 170 struct j6x0lcd_softc *sc = (struct j6x0lcd_softc *)self; 171 int contrast, i; 172 uint16_t bcr, bdr; 173 uint8_t dcr, ddr; 174 175 /* 176 * Brightness is controlled by DAC channel 0. 177 */ 178 dcr = DAC_(CR); 179 dcr &= ~SH7709_DACR_DAE; /* want to control each channel separately */ 180 dcr |= SH7709_DACR_DAOE0; /* enable channel 0 */ 181 DAC_(CR) = dcr; 182 183 ddr = DAC_(DR0); 184 sc->sc_brightness = J6X0LCD_DA_TO_BRIGHTNESS(ddr); 185 186 187 /* 188 * Contrast and power are controlled by HD64461 GPIO port B. 189 */ 190 bcr = hd64461_reg_read_2(HD64461_GPBCR_REG16); 191 bdr = hd64461_reg_read_2(HD64461_GPBDR_REG16); 192 193 contrast = 0xf; /* bits are inverted */ 194 for (i = 0; i < 4; ++i) { 195 unsigned int c, v; 196 c = (bcr >> ((6 - i) << 1)) & 0x3; 197 if (c == 1) /* gpio mode? */ 198 v = 1; 199 else 200 v = 0; 201 contrast &= ~(v << i); 202 } 203 204 sc->sc_contrast = contrast; 205 206 bdr &= ~HD64461_GPBDR_J6X0LCD_OFF; 207 bdr |= HD64461_GPBDR_J6X0LCD_CONTRAST_BITS; 208 hd64461_reg_write_2(HD64461_GPBDR_REG16, bdr); 209 210 bcr &= HD64461_GPBCR_J6X0LCD_OFF_MASK 211 & HD64461_GPBCR_J6X0LCD_CONTRAST_MASK; 212 bcr |= HD64461_GPBCR_J6X0LCD_OFF_BITS 213 | j6x0lcd_contrast_control_bits[contrast]; 214 hd64461_reg_write_2(HD64461_GPBCR_REG16, bcr); 215 216 printf(": brightness %d, contrast %d\n", 217 sc->sc_brightness, sc->sc_contrast); 218 219 220 /* LCD brightness hooks */ 221 config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_BRIGHTNESS_MAX, 222 CONFIG_HOOK_SHARE, 223 j6x0lcd_param, sc); 224 config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_BRIGHTNESS, 225 CONFIG_HOOK_SHARE, 226 j6x0lcd_param, sc); 227 config_hook(CONFIG_HOOK_SET, CONFIG_HOOK_BRIGHTNESS, 228 CONFIG_HOOK_SHARE, 229 j6x0lcd_param, sc); 230 231 /* LCD contrast hooks */ 232 config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_CONTRAST_MAX, 233 CONFIG_HOOK_SHARE, 234 j6x0lcd_param, sc); 235 config_hook(CONFIG_HOOK_GET, CONFIG_HOOK_CONTRAST, 236 CONFIG_HOOK_SHARE, 237 j6x0lcd_param, sc); 238 config_hook(CONFIG_HOOK_SET, CONFIG_HOOK_CONTRAST, 239 CONFIG_HOOK_SHARE, 240 j6x0lcd_param, sc); 241 242 /* LCD on/off hook */ 243 config_hook(CONFIG_HOOK_POWERCONTROL, 244 CONFIG_HOOK_POWERCONTROL_LCD, 245 CONFIG_HOOK_SHARE, 246 j6x0lcd_power, sc); 247 } 248 249 250 static int 251 j6x0lcd_param(ctx, type, id, msg) 252 void *ctx; 253 int type; 254 long id; 255 void *msg; 256 { 257 struct j6x0lcd_softc *sc = ctx; 258 int value; 259 uint16_t bcr; 260 uint8_t dr; 261 262 switch (type) { 263 case CONFIG_HOOK_GET: 264 switch (id) { 265 case CONFIG_HOOK_CONTRAST: 266 *(int *)msg = sc->sc_contrast; 267 return (0); 268 269 case CONFIG_HOOK_CONTRAST_MAX: 270 *(int *)msg = J6X0LCD_CONTRAST_MAX; 271 return (0); 272 273 case CONFIG_HOOK_BRIGHTNESS: 274 *(int *)msg = sc->sc_brightness; 275 return (0); 276 277 case CONFIG_HOOK_BRIGHTNESS_MAX: 278 *(int *)msg = J6X0LCD_BRIGHTNESS_MAX; 279 return (0); 280 } 281 break; 282 283 case CONFIG_HOOK_SET: 284 value = *(int *)msg; 285 if (value < 0) 286 value = 0; 287 288 switch (id) { 289 case CONFIG_HOOK_CONTRAST: 290 if (value > J6X0LCD_CONTRAST_MAX) 291 value = J6X0LCD_CONTRAST_MAX; 292 sc->sc_contrast = value; 293 294 bcr = hd64461_reg_read_2(HD64461_GPBCR_REG16); 295 bcr &= HD64461_GPBCR_J6X0LCD_CONTRAST_MASK; 296 bcr |= j6x0lcd_contrast_control_bits[value]; 297 hd64461_reg_write_2(HD64461_GPBCR_REG16, bcr); 298 return (0); 299 300 case CONFIG_HOOK_BRIGHTNESS: 301 if (value > J6X0LCD_BRIGHTNESS_MAX) 302 value = J6X0LCD_BRIGHTNESS_MAX; 303 sc->sc_brightness = value; 304 305 dr = J6X0LCD_BRIGHTNESS_TO_DA(value); 306 DAC_(DR0) = dr; 307 return (0); 308 } 309 break; 310 } 311 312 return (EINVAL); 313 } 314 315 316 static int 317 j6x0lcd_power(ctx, type, id, msg) 318 void *ctx; 319 int type; 320 long id; 321 void *msg; 322 { 323 int on; 324 uint16_t r; 325 326 if (type != CONFIG_HOOK_POWERCONTROL 327 || id != CONFIG_HOOK_POWERCONTROL_LCD) 328 return (EINVAL); 329 330 on = (int)msg; 331 332 r = hd64461_reg_read_2(HD64461_GPBDR_REG16); 333 if (on) 334 r &= ~HD64461_GPBDR_J6X0LCD_OFF; 335 else 336 r |= HD64461_GPBDR_J6X0LCD_OFF; 337 hd64461_reg_write_2(HD64461_GPBDR_REG16, r); 338 339 return (0); 340 } 341
Indexes created Tue Sep 30 20:09:53 GMT 2025