apic.c revision 1.1
1 /* $NetBSD: apic.c,v 1.1 2014/02/24 07:23:42 skrll Exp $ */ 2 3 /* $OpenBSD: apic.c,v 1.14 2011/05/01 21:59:39 kettenis Exp $ */ 4 5 /* 6 * Copyright (c) 2005 Michael Shalayeff 7 * Copyright (c) 2007 Mark Kettenis 8 * All rights reserved. 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 19 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 20 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 #include <sys/device.h> 25 #include <sys/malloc.h> 26 27 #include <machine/autoconf.h> 28 #include <machine/pdc.h> 29 #include <machine/intr.h> 30 31 #include <dev/pci/pcireg.h> 32 #include <dev/pci/pcivar.h> 33 #include <dev/pci/pcidevs.h> 34 35 #include <hppa/dev/elroyreg.h> 36 #include <hppa/dev/elroyvar.h> 37 38 #define APIC_INT_LINE_MASK 0x0000ff00 39 #define APIC_INT_LINE_SHIFT 8 40 #define APIC_INT_IRQ_MASK 0x0000001f 41 42 #define APIC_INT_LINE(x) (((x) & APIC_INT_LINE_MASK) >> APIC_INT_LINE_SHIFT) 43 #define APIC_INT_IRQ(x) ((x) & APIC_INT_IRQ_MASK) 44 45 /* 46 * Interrupt types match the Intel MP Specification. 47 */ 48 49 #define MPS_INTPO_DEF 0 50 #define MPS_INTPO_ACTHI 1 51 #define MPS_INTPO_ACTLO 3 52 #define MPS_INTPO_SHIFT 0 53 #define MPS_INTPO_MASK 3 54 55 #define MPS_INTTR_DEF 0 56 #define MPS_INTTR_EDGE 1 57 #define MPS_INTTR_LEVEL 3 58 #define MPS_INTTR_SHIFT 2 59 #define MPS_INTTR_MASK 3 60 61 #define MPS_INT(p,t) \ 62 ((((p) & MPS_INTPO_MASK) << MPS_INTPO_SHIFT) | \ 63 (((t) & MPS_INTTR_MASK) << MPS_INTTR_SHIFT)) 64 65 struct apic_iv { 66 struct elroy_softc *sc; 67 pci_intr_handle_t ih; 68 int (*handler)(void *); 69 void *arg; 70 struct apic_iv *next; 71 struct evcnt *cnt; 72 char aiv_name[32]; 73 }; 74 75 struct apic_iv *apic_intr_list[CPU_NINTS]; 76 77 void apic_write(volatile struct elroy_regs *, uint32_t, uint32_t); 78 uint32_t apic_read(volatile struct elroy_regs *, uint32_t reg); 79 80 void apic_get_int_tbl(struct elroy_softc *); 81 uint32_t apic_get_int_ent0(struct elroy_softc *, int); 82 #ifdef DEBUG 83 void apic_dump(struct elroy_softc *); 84 #endif 85 86 void 87 apic_write(volatile struct elroy_regs *r, uint32_t reg, uint32_t val) 88 { 89 elroy_write32(&r->apic_addr, htole32(reg)); 90 elroy_write32(&r->apic_data, htole32(val)); 91 elroy_read32(&r->apic_data); 92 } 93 94 uint32_t 95 apic_read(volatile struct elroy_regs *r, uint32_t reg) 96 { 97 elroy_write32(&r->apic_addr, htole32(reg)); 98 return le32toh(elroy_read32(&r->apic_data)); 99 } 100 101 void 102 apic_attach(struct elroy_softc *sc) 103 { 104 volatile struct elroy_regs *r = sc->sc_regs; 105 uint32_t data; 106 107 data = apic_read(r, APIC_VERSION); 108 sc->sc_nints = (data & APIC_VERSION_NENT) >> APIC_VERSION_NENT_SHIFT; 109 aprint_normal(" APIC ver %x, %d pins", 110 data & APIC_VERSION_MASK, sc->sc_nints); 111 112 sc->sc_irq = malloc(sc->sc_nints * sizeof(int), M_DEVBUF, 113 M_NOWAIT | M_ZERO); 114 if (sc->sc_irq == NULL) 115 panic("apic_attach: can't allocate irq table\n"); 116 117 apic_get_int_tbl(sc); 118 119 #ifdef DEBUG 120 apic_dump(sc); 121 #endif 122 } 123 124 int 125 apic_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 126 { 127 struct elroy_softc *sc = pa->pa_pc->_cookie; 128 struct cpu_info *ci = &cpus[0]; 129 pci_chipset_tag_t pc = pa->pa_pc; 130 pcitag_t tag = pa->pa_tag; 131 pcireg_t reg; 132 int line; 133 134 reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG); 135 #ifdef DEBUG 136 printf(" pin=%d line=%d ", PCI_INTERRUPT_PIN(reg), 137 PCI_INTERRUPT_LINE(reg)); 138 #endif 139 line = PCI_INTERRUPT_LINE(reg); 140 if (sc->sc_irq[line] == 0) 141 sc->sc_irq[line] = hppa_intr_allocate_bit(&ci->ci_ir, -1); 142 KASSERT(sc->sc_irq[line] != -1); 143 *ihp = (line << APIC_INT_LINE_SHIFT) | sc->sc_irq[line]; 144 145 return APIC_INT_IRQ(*ihp) == 0; 146 } 147 148 const char * 149 apic_intr_string(void *v, pci_intr_handle_t ih) 150 { 151 static char buf[32]; 152 153 snprintf(buf, sizeof(buf), "line %ld irq %ld", 154 APIC_INT_LINE(ih), APIC_INT_IRQ(ih)); 155 156 return buf; 157 } 158 159 void * 160 apic_intr_establish(void *v, pci_intr_handle_t ih, 161 int pri, int (*handler)(void *), void *arg) 162 { 163 struct elroy_softc *sc = v; 164 volatile struct elroy_regs *r = sc->sc_regs; 165 struct cpu_info *ci = &cpus[0]; 166 hppa_hpa_t hpa = ci->ci_hpa; 167 struct evcnt *cnt; 168 struct apic_iv *aiv, *biv; 169 void *iv; 170 int irq = APIC_INT_IRQ(ih); 171 int line = APIC_INT_LINE(ih); 172 uint32_t ent0; 173 174 /* no mapping or bogus */ 175 if (irq <= 0 || irq > 31) 176 return NULL; 177 178 aiv = malloc(sizeof(struct apic_iv), M_DEVBUF, M_NOWAIT); 179 if (aiv == NULL) 180 return NULL; 181 182 cnt = malloc(sizeof(struct evcnt), M_DEVBUF, M_NOWAIT); 183 if (cnt == NULL) { 184 free(aiv, M_DEVBUF); 185 return NULL; 186 } 187 188 aiv->sc = sc; 189 aiv->ih = ih; 190 aiv->handler = handler; 191 aiv->arg = arg; 192 aiv->next = NULL; 193 aiv->cnt = cnt; 194 195 biv = apic_intr_list[irq]; 196 if (biv == NULL) { 197 iv = hppa_intr_establish(pri, apic_intr, aiv, &ci->ci_ir, irq); 198 if (iv == NULL) { 199 free(aiv, M_DEVBUF); 200 free(cnt, M_DEVBUF); 201 202 return NULL; 203 } 204 } 205 206 snprintf(aiv->aiv_name, sizeof(aiv->aiv_name), "line %d irq %d", 207 line, irq); 208 209 evcnt_attach_dynamic(cnt, EVCNT_TYPE_INTR, NULL, 210 device_xname(sc->sc_dv), aiv->aiv_name); 211 212 if (biv) { 213 while (biv->next) 214 biv = biv->next; 215 biv->next = aiv; 216 return arg; 217 } 218 219 ent0 = (31 - irq) & APIC_ENT0_VEC; 220 ent0 |= apic_get_int_ent0(sc, line); 221 #if 0 222 if (cold) { 223 sc->sc_imr |= (1 << irq); 224 ent0 |= APIC_ENT0_MASK; 225 } 226 #endif 227 apic_write(sc->sc_regs, APIC_ENT0(line), APIC_ENT0_MASK); 228 apic_write(sc->sc_regs, APIC_ENT1(line), 229 ((hpa & 0x0ff00000) >> 4) | ((hpa & 0x000ff000) << 12)); 230 apic_write(sc->sc_regs, APIC_ENT0(line), ent0); 231 232 /* Signal EOI. */ 233 elroy_write32(&r->apic_eoi, 234 htole32((31 - irq) & APIC_ENT0_VEC)); 235 236 apic_intr_list[irq] = aiv; 237 238 return arg; 239 } 240 241 void 242 apic_intr_disestablish(void *v, void *cookie) 243 { 244 } 245 246 int 247 apic_intr(void *v) 248 { 249 struct apic_iv *iv = v; 250 struct elroy_softc *sc = iv->sc; 251 volatile struct elroy_regs *r = sc->sc_regs; 252 uint32_t irq = APIC_INT_IRQ(iv->ih); 253 int claimed = 0; 254 255 while (iv) { 256 claimed = iv->handler(iv->arg); 257 if (claimed && iv->cnt) 258 iv->cnt->ev_count++; 259 if (claimed) 260 break; 261 iv = iv->next; 262 } 263 /* Signal EOI. */ 264 elroy_write32(&r->apic_eoi, htole32((31 - irq) & APIC_ENT0_VEC)); 265 266 return claimed; 267 } 268 269 void 270 apic_get_int_tbl(struct elroy_softc *sc) 271 { 272 int nentries; 273 size_t size; 274 int err; 275 276 err = pdcproc_pci_inttblsz(&nentries); 277 if (err) 278 return; 279 280 size = nentries * sizeof(struct pdc_pat_pci_rt); 281 sc->sc_int_tbl_sz = nentries; 282 sc->sc_int_tbl = malloc(size, M_DEVBUF, M_NOWAIT); 283 if (sc->sc_int_tbl == NULL) 284 return; 285 286 pdcproc_pci_gettable(nentries, size, sc->sc_int_tbl); 287 } 288 289 uint32_t 290 apic_get_int_ent0(struct elroy_softc *sc, int line) 291 { 292 volatile struct elroy_regs *r = sc->sc_regs; 293 int trigger = MPS_INT(MPS_INTPO_DEF, MPS_INTTR_DEF); 294 uint32_t ent0 = APIC_ENT0_LOW | APIC_ENT0_LEV; 295 int bus, mpspo, mpstr; 296 int i; 297 298 bus = le32toh(elroy_read32(&r->busnum)) & 0xff; 299 for (i = 0; i < sc->sc_int_tbl_sz; i++) { 300 if (bus == sc->sc_int_tbl[i].bus && 301 line == sc->sc_int_tbl[i].line) 302 trigger = sc->sc_int_tbl[i].trigger; 303 } 304 305 mpspo = (trigger >> MPS_INTPO_SHIFT) & MPS_INTPO_MASK; 306 mpstr = (trigger >> MPS_INTTR_SHIFT) & MPS_INTTR_MASK; 307 308 switch (mpspo) { 309 case MPS_INTPO_DEF: 310 break; 311 case MPS_INTPO_ACTHI: 312 ent0 &= ~APIC_ENT0_LOW; 313 break; 314 case MPS_INTPO_ACTLO: 315 ent0 |= APIC_ENT0_LOW; 316 break; 317 default: 318 panic("unknown MPS interrupt polarity %d", mpspo); 319 } 320 321 switch(mpstr) { 322 case MPS_INTTR_DEF: 323 break; 324 case MPS_INTTR_LEVEL: 325 ent0 |= APIC_ENT0_LEV; 326 break; 327 case MPS_INTTR_EDGE: 328 ent0 &= ~APIC_ENT0_LEV; 329 break; 330 default: 331 panic("unknown MPS interrupt trigger %d", mpstr); 332 } 333 334 return ent0; 335 } 336 337 #ifdef DEBUG 338 void 339 apic_dump(struct elroy_softc *sc) 340 { 341 int i; 342 343 for (i = 0; i < sc->sc_nints; i++) 344 printf("0x%04x 0x%04x\n", apic_read(sc->sc_regs, APIC_ENT0(i)), 345 apic_read(sc->sc_regs, APIC_ENT1(i))); 346 347 for (i = 0; i < sc->sc_int_tbl_sz; i++) { 348 printf("type=%x ", sc->sc_int_tbl[i].type); 349 printf("len=%d ", sc->sc_int_tbl[i].len); 350 printf("itype=%d ", sc->sc_int_tbl[i].itype); 351 printf("trigger=%x ", sc->sc_int_tbl[i].trigger); 352 printf("pin=%x ", sc->sc_int_tbl[i].pin); 353 printf("bus=%d ", sc->sc_int_tbl[i].bus); 354 printf("line=%d ", sc->sc_int_tbl[i].line); 355 printf("addr=%llx\n", sc->sc_int_tbl[i].addr); 356 } 357 } 358 #endif 359
Indexes created Thu Oct 02 10:09:58 GMT 2025