1 1.18 riastrad /* $NetBSD: dino.c,v 1.18 2025/04/06 03:31:52 riastradh Exp $ */ 2 1.1 skrll 3 1.1 skrll /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ 4 1.1 skrll 5 1.1 skrll /* 6 1.1 skrll * Copyright (c) 2003 Michael Shalayeff 7 1.1 skrll * All rights reserved. 8 1.1 skrll * 9 1.1 skrll * Redistribution and use in source and binary forms, with or without 10 1.1 skrll * modification, are permitted provided that the following conditions 11 1.1 skrll * are met: 12 1.1 skrll * 1. Redistributions of source code must retain the above copyright 13 1.1 skrll * notice, this list of conditions and the following disclaimer. 14 1.1 skrll * 2. Redistributions in binary form must reproduce the above copyright 15 1.1 skrll * notice, this list of conditions and the following disclaimer in the 16 1.1 skrll * documentation and/or other materials provided with the distribution. 17 1.1 skrll * 18 1.1 skrll * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.1 skrll * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.1 skrll * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.1 skrll * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 1.1 skrll * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 1.1 skrll * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 1.1 skrll * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.1 skrll * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 1.1 skrll * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 1.1 skrll * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 1.1 skrll * THE POSSIBILITY OF SUCH DAMAGE. 29 1.1 skrll */ 30 1.1 skrll 31 1.1 skrll #include <sys/cdefs.h> 32 1.18 riastrad __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.18 2025/04/06 03:31:52 riastradh Exp $"); 33 1.1 skrll 34 1.1 skrll /* #include "cardbus.h" */ 35 1.1 skrll 36 1.1 skrll #include <sys/param.h> 37 1.1 skrll #include <sys/systm.h> 38 1.1 skrll #include <sys/device.h> 39 1.1 skrll #include <sys/reboot.h> 40 1.1 skrll #include <sys/extent.h> 41 1.1 skrll 42 1.1 skrll #include <machine/iomod.h> 43 1.1 skrll #include <machine/autoconf.h> 44 1.1 skrll #include <machine/intr.h> 45 1.1 skrll 46 1.1 skrll #include <hppa/include/vmparam.h> 47 1.1 skrll #include <hppa/dev/cpudevs.h> 48 1.1 skrll 49 1.1 skrll #if NCARDBUS > 0 50 1.1 skrll #include <dev/cardbus/rbus.h> 51 1.1 skrll #endif 52 1.1 skrll 53 1.1 skrll #include <dev/pci/pcireg.h> 54 1.1 skrll #include <dev/pci/pcivar.h> 55 1.1 skrll #include <dev/pci/pcidevs.h> 56 1.1 skrll 57 1.1 skrll #define DINO_MEM_CHUNK 0x800000 58 1.1 skrll 59 1.1 skrll /* from machdep.c */ 60 1.1 skrll extern struct extent *hppa_io_extent; 61 1.1 skrll 62 1.1 skrll struct dino_regs { 63 1.1 skrll /* HPA Supervisory Register Set */ 64 1.1 skrll uint32_t pad0; /* 0x000 */ 65 1.1 skrll uint32_t iar0; /* 0x004 rw intr addr reg 0 */ 66 1.1 skrll uint32_t iodc; /* 0x008 rw iodc data/addr */ 67 1.1 skrll uint32_t irr0; /* 0x00c r intr req reg 0 */ 68 1.1 skrll uint32_t iar1; /* 0x010 rw intr addr reg 1 */ 69 1.1 skrll uint32_t irr1; /* 0x014 r intr req reg 1 */ 70 1.1 skrll uint32_t imr; /* 0x018 rw intr mask reg */ 71 1.1 skrll uint32_t ipr; /* 0x01c rw intr pending reg */ 72 1.1 skrll uint32_t toc_addr; /* 0x020 rw TOC addr reg */ 73 1.1 skrll uint32_t icr; /* 0x024 rw intr control reg */ 74 1.1 skrll uint32_t ilr; /* 0x028 r intr level reg */ 75 1.1 skrll uint32_t pad1; /* 0x02c */ 76 1.1 skrll uint32_t io_command; /* 0x030 w command register */ 77 1.1 skrll uint32_t io_status; /* 0x034 r status register */ 78 1.1 skrll uint32_t io_control; /* 0x038 rw control register */ 79 1.1 skrll uint32_t pad2; /* 0x03c AUX registers follow */ 80 1.1 skrll 81 1.1 skrll /* HPA Auxiliary Register Set */ 82 1.1 skrll uint32_t io_gsc_err_addr;/* 0x040 GSC error address */ 83 1.1 skrll uint32_t io_err_info; /* 0x044 error info register */ 84 1.1 skrll uint32_t io_pci_err_addr;/* 0x048 PCI error address */ 85 1.1 skrll uint32_t pad3[4]; /* 0x04c */ 86 1.1 skrll uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 87 1.1 skrll uint32_t io_addr_en; /* 0x060 address enable reg */ 88 1.1 skrll uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 89 1.1 skrll uint32_t pci_conf_data; /* 0x068 PCI conf data reg */ 90 1.1 skrll uint32_t pci_io_data; /* 0x06c PCI io data reg */ 91 1.1 skrll uint32_t pci_mem_data; /* 0x070 PCI memory data reg */ 92 1.1 skrll uint32_t pad4[0x740/4]; /* 0x074 */ 93 1.1 skrll 94 1.1 skrll /* HPA Bus (GSC) Specific-Dependent Register Set */ 95 1.1 skrll uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 96 1.1 skrll uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 97 1.1 skrll 98 1.1 skrll /* HPA HVERSION (Dino)-Dependent Register Set */ 99 1.1 skrll uint32_t gmask; /* 0x800 GSC arbitration mask */ 100 1.1 skrll uint32_t pamr; /* 0x804 PCI arbitration mask */ 101 1.1 skrll uint32_t papr; /* 0x808 PCI arbitration priority */ 102 1.1 skrll uint32_t damode; /* 0x80c PCI arbitration mode */ 103 1.1 skrll uint32_t pcicmd; /* 0x810 PCI command register */ 104 1.1 skrll uint32_t pcists; /* 0x814 PCI status register */ 105 1.1 skrll uint32_t pad6; /* 0x818 */ 106 1.1 skrll uint32_t mltim; /* 0x81c PCI master latency timer */ 107 1.1 skrll uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 108 1.1 skrll uint32_t pciror; /* 0x824 PCI read optimization reg */ 109 1.1 skrll uint32_t pciwor; /* 0x828 PCI write optimization reg */ 110 1.1 skrll uint32_t pad7; /* 0x82c */ 111 1.1 skrll uint32_t tltim; /* 0x830 PCI target latency reg */ 112 1.1 skrll }; 113 1.1 skrll 114 1.1 skrll struct dino_softc { 115 1.1 skrll device_t sc_dv; 116 1.1 skrll 117 1.1 skrll int sc_ver; 118 1.1 skrll void *sc_ih; 119 1.1 skrll struct hppa_interrupt_register sc_ir; 120 1.1 skrll bus_space_tag_t sc_bt; 121 1.1 skrll bus_space_handle_t sc_bh; 122 1.1 skrll bus_dma_tag_t sc_dmat; 123 1.4 skrll 124 1.4 skrll struct hppa_bus_dma_tag sc_dmatag; 125 1.4 skrll struct hppa_bus_space_tag sc_memt; 126 1.4 skrll 127 1.1 skrll volatile struct dino_regs *sc_regs; 128 1.1 skrll 129 1.1 skrll struct hppa_pci_chipset_tag sc_pc; 130 1.1 skrll struct hppa_bus_space_tag sc_iot; 131 1.4 skrll 132 1.1 skrll struct extent *sc_ioex; 133 1.1 skrll int sc_memrefcount[30]; 134 1.4 skrll 135 1.4 skrll char sc_ioexname[20]; 136 1.1 skrll }; 137 1.1 skrll 138 1.1 skrll int dinomatch(device_t, struct cfdata *, void *); 139 1.1 skrll void dinoattach(device_t, device_t, void *); 140 1.1 skrll static device_t dino_callback(device_t, struct confargs *); 141 1.1 skrll 142 1.1 skrll CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, 143 1.1 skrll NULL); 144 1.1 skrll 145 1.1 skrll void dino_attach_hook(device_t, device_t, 146 1.1 skrll struct pcibus_attach_args *); 147 1.1 skrll void dino_enable_bus(struct dino_softc *, int); 148 1.1 skrll int dino_maxdevs(void *, int); 149 1.1 skrll pcitag_t dino_make_tag(void *, int, int, int); 150 1.1 skrll void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 151 1.1 skrll pcireg_t dino_conf_read(void *, pcitag_t, int); 152 1.1 skrll void dino_conf_write(void *, pcitag_t, int, pcireg_t); 153 1.1 skrll 154 1.1 skrll int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 155 1.2 christos const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t); 156 1.1 skrll void *dino_intr_establish(void *, pci_intr_handle_t, int, 157 1.1 skrll int (*)(void *), void *); 158 1.1 skrll void dino_intr_disestablish(void *, void *); 159 1.1 skrll 160 1.1 skrll void *dino_alloc_parent(device_t, struct pci_attach_args *, int); 161 1.1 skrll 162 1.1 skrll int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 163 1.1 skrll int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 164 1.1 skrll int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 165 1.1 skrll bus_space_handle_t *); 166 1.1 skrll int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 167 1.1 skrll bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 168 1.1 skrll int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 169 1.1 skrll bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 170 1.1 skrll void dino_unmap(void *, bus_space_handle_t, bus_size_t); 171 1.1 skrll void dino_free(void *, bus_space_handle_t, bus_size_t); 172 1.1 skrll void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 173 1.1 skrll void *dino_vaddr(void *, bus_space_handle_t); 174 1.1 skrll paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int); 175 1.1 skrll 176 1.1 skrll uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 177 1.1 skrll uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 178 1.1 skrll uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 179 1.1 skrll uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 180 1.17 macallan uint16_t dino_rs2(void *, bus_space_handle_t, bus_size_t); 181 1.17 macallan uint32_t dino_rs4(void *, bus_space_handle_t, bus_size_t); 182 1.17 macallan uint64_t dino_rs8(void *, bus_space_handle_t, bus_size_t); 183 1.1 skrll void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t); 184 1.1 skrll void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 185 1.1 skrll void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 186 1.1 skrll void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t); 187 1.17 macallan void dino_ws2(void *, bus_space_handle_t, bus_size_t, uint16_t); 188 1.17 macallan void dino_ws4(void *, bus_space_handle_t, bus_size_t, uint32_t); 189 1.17 macallan void dino_ws8(void *, bus_space_handle_t, bus_size_t, uint64_t); 190 1.1 skrll void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 191 1.1 skrll void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 192 1.1 skrll void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 193 1.1 skrll void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 194 1.1 skrll void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 195 1.1 skrll bus_size_t); 196 1.1 skrll void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 197 1.1 skrll bus_size_t); 198 1.1 skrll void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 199 1.1 skrll bus_size_t); 200 1.1 skrll void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 201 1.1 skrll bus_size_t); 202 1.1 skrll void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 203 1.1 skrll void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 204 1.1 skrll void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 205 1.1 skrll void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 206 1.1 skrll void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 207 1.1 skrll bus_size_t); 208 1.1 skrll void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 209 1.1 skrll bus_size_t); 210 1.1 skrll void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 211 1.1 skrll bus_size_t); 212 1.1 skrll void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 213 1.1 skrll bus_size_t); 214 1.1 skrll void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 215 1.1 skrll bus_size_t); 216 1.1 skrll void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 217 1.1 skrll bus_size_t); 218 1.1 skrll void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 219 1.1 skrll void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 220 1.1 skrll void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 221 1.1 skrll void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 222 1.1 skrll void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 223 1.1 skrll bus_size_t); 224 1.1 skrll void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 225 1.1 skrll bus_size_t); 226 1.1 skrll void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 227 1.1 skrll bus_size_t); 228 1.1 skrll void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 229 1.1 skrll bus_size_t); 230 1.1 skrll void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 231 1.1 skrll bus_size_t); 232 1.1 skrll void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 233 1.1 skrll bus_size_t); 234 1.1 skrll void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 235 1.1 skrll bus_size_t); 236 1.1 skrll void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 237 1.1 skrll bus_size_t); 238 1.1 skrll void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 239 1.1 skrll bus_size_t); 240 1.1 skrll void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 241 1.1 skrll bus_size_t); 242 1.1 skrll void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 243 1.1 skrll void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 244 1.1 skrll void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 245 1.1 skrll void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 246 1.1 skrll void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 247 1.1 skrll bus_size_t, bus_size_t); 248 1.1 skrll void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 249 1.1 skrll bus_size_t, bus_size_t); 250 1.1 skrll void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 251 1.1 skrll bus_size_t, bus_size_t); 252 1.1 skrll void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 253 1.1 skrll bus_size_t, bus_size_t); 254 1.1 skrll int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 255 1.1 skrll bus_dmamap_t *); 256 1.1 skrll void dino_dmamap_destroy(void *, bus_dmamap_t); 257 1.1 skrll int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, 258 1.1 skrll int); 259 1.1 skrll int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 260 1.1 skrll int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 261 1.1 skrll int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 262 1.1 skrll bus_size_t, int); 263 1.1 skrll void dino_dmamap_unload(void *, bus_dmamap_t); 264 1.1 skrll void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 265 1.1 skrll int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 266 1.1 skrll bus_dma_segment_t *, int, int *, int); 267 1.1 skrll void dino_dmamem_free(void *, bus_dma_segment_t *, int); 268 1.1 skrll int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int); 269 1.1 skrll void dino_dmamem_unmap(void *, void *, size_t); 270 1.1 skrll paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 271 1.1 skrll 272 1.1 skrll 273 1.1 skrll void 274 1.1 skrll dino_attach_hook(device_t parent, device_t self, 275 1.1 skrll struct pcibus_attach_args *pba) 276 1.1 skrll { 277 1.1 skrll struct dino_softc *sc = pba->pba_pc->_cookie; 278 1.1 skrll 279 1.1 skrll /* 280 1.1 skrll * The firmware enables only devices that are needed for booting. 281 1.1 skrll * So other devices will fail to map PCI MEM / IO when they attach. 282 1.1 skrll * Therefore we recursively walk all buses to simply enable everything. 283 1.1 skrll */ 284 1.1 skrll dino_enable_bus(sc, 0); 285 1.1 skrll } 286 1.1 skrll 287 1.1 skrll void 288 1.1 skrll dino_enable_bus(struct dino_softc *sc, int bus) 289 1.1 skrll { 290 1.1 skrll int func; 291 1.1 skrll int dev; 292 1.1 skrll pcitag_t tag; 293 1.1 skrll pcireg_t data; 294 1.1 skrll pcireg_t class; 295 1.1 skrll 296 1.1 skrll for (dev = 0; dev < 32; dev++) { 297 1.1 skrll tag = dino_make_tag(sc, bus, dev, 0); 298 1.1 skrll if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) { 299 1.1 skrll for (func = 0; func < 8; func++) { 300 1.1 skrll tag = dino_make_tag(sc, bus, dev, func); 301 1.1 skrll if (dino_conf_read(sc, tag, 0) != 0xffffffff) { 302 1.1 skrll data = dino_conf_read(sc, tag, 303 1.1 skrll PCI_COMMAND_STATUS_REG); 304 1.1 skrll dino_conf_write(sc, tag, 305 1.1 skrll PCI_COMMAND_STATUS_REG, 306 1.1 skrll PCI_COMMAND_IO_ENABLE | 307 1.1 skrll PCI_COMMAND_MEM_ENABLE | 308 1.1 skrll PCI_COMMAND_MASTER_ENABLE | data); 309 1.1 skrll } 310 1.1 skrll } 311 1.1 skrll class = dino_conf_read(sc, tag, PCI_CLASS_REG); 312 1.1 skrll if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 313 1.1 skrll PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI) 314 1.1 skrll dino_enable_bus(sc, bus + 1); 315 1.1 skrll } 316 1.1 skrll } 317 1.1 skrll } 318 1.1 skrll 319 1.1 skrll int 320 1.1 skrll dino_maxdevs(void *v, int bus) 321 1.1 skrll { 322 1.1 skrll return 32; 323 1.1 skrll } 324 1.1 skrll 325 1.1 skrll pcitag_t 326 1.1 skrll dino_make_tag(void *v, int bus, int dev, int func) 327 1.1 skrll { 328 1.1 skrll if (bus > 255 || dev > 31 || func > 7) 329 1.1 skrll panic("dino_make_tag: bad request"); 330 1.1 skrll 331 1.1 skrll return (bus << 16) | (dev << 11) | (func << 8); 332 1.1 skrll } 333 1.1 skrll 334 1.1 skrll void 335 1.1 skrll dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 336 1.1 skrll { 337 1.1 skrll *bus = (tag >> 16) & 0xff; 338 1.1 skrll *dev = (tag >> 11) & 0x1f; 339 1.1 skrll *func= (tag >> 8) & 0x07; 340 1.1 skrll } 341 1.1 skrll 342 1.1 skrll pcireg_t 343 1.1 skrll dino_conf_read(void *v, pcitag_t tag, int reg) 344 1.1 skrll { 345 1.1 skrll struct dino_softc *sc = v; 346 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 347 1.1 skrll pcireg_t data; 348 1.1 skrll uint32_t pamr; 349 1.1 skrll 350 1.3 msaitoh if ((unsigned int)reg >= PCI_CONF_SIZE) 351 1.3 msaitoh return (pcireg_t) -1; 352 1.3 msaitoh 353 1.7 macallan /* 354 1.7 macallan * XXX 355 1.13 macallan * thus sayeth the Dino manual: 356 1.13 macallan * 7.7.1 Generating PCI Special Cycles thru PA I/O Space 357 1.13 macallan * When the PCI_CONFIG_ADDR registers BUS_NUM is the equal to the 358 1.13 macallan * DINOs bus number, 8h00, DEV_NUM and Function fields are all ones, 359 1.13 macallan * and the REG_NUM field is all zeros the next write to PCI_CONFIG_DATA 360 1.13 macallan * register will generate a special cycle on DINOs PCI bus. If the 361 1.13 macallan * BUS_NUM field does not equal DINO bus number then a type 1 362 1.13 macallan * transaction will be forwarded to PCI as described above. 363 1.13 macallan * Note: Dino is using a legal PCI configuration address to generate a 364 1.13 macallan * PCI special cycle. System firmware and software should not attempt 365 1.13 macallan * to read or write to this configuration address when walking the 366 1.13 macallan * PCI bus through configuration address space. 367 1.7 macallan */ 368 1.8 skrll if ((tag & 0xff00) == 0xff00) 369 1.8 skrll return -1; 370 1.7 macallan 371 1.1 skrll /* fix arbitration errata by disabling all pci devs on config read */ 372 1.1 skrll pamr = r->pamr; 373 1.1 skrll r->pamr = 0; 374 1.9 skrll 375 1.1 skrll r->pci_addr = tag | reg; 376 1.1 skrll data = r->pci_conf_data; 377 1.1 skrll 378 1.1 skrll /* restore arbitration */ 379 1.1 skrll r->pamr = pamr; 380 1.1 skrll 381 1.1 skrll return le32toh(data); 382 1.1 skrll } 383 1.1 skrll 384 1.1 skrll void 385 1.1 skrll dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 386 1.1 skrll { 387 1.1 skrll struct dino_softc *sc = v; 388 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 389 1.1 skrll uint32_t pamr; 390 1.1 skrll 391 1.3 msaitoh if ((unsigned int)reg >= PCI_CONF_SIZE) 392 1.3 msaitoh return; 393 1.3 msaitoh 394 1.7 macallan /* 395 1.13 macallan * don't try to access dev 1f / func 7, see comment in dino_conf_read() 396 1.7 macallan */ 397 1.7 macallan if ((tag & 0xff00) == 0xff00) return; 398 1.7 macallan 399 1.1 skrll /* fix arbitration errata by disabling all pci devs on config read */ 400 1.1 skrll pamr = r->pamr; 401 1.1 skrll r->pamr = 0; 402 1.1 skrll 403 1.1 skrll r->pci_addr = tag | reg; 404 1.1 skrll r->pci_conf_data = htole32(data); 405 1.1 skrll 406 1.1 skrll /* fix coalescing config and io writes by interleaving w/ a read */ 407 1.1 skrll r->pci_addr = tag | PCI_ID_REG; 408 1.1 skrll (void)r->pci_conf_data; 409 1.1 skrll 410 1.1 skrll /* restore arbitration */ 411 1.1 skrll r->pamr = pamr; 412 1.1 skrll } 413 1.1 skrll 414 1.1 skrll int 415 1.1 skrll dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 416 1.1 skrll { 417 1.1 skrll int line = pa->pa_intrline; 418 1.1 skrll 419 1.1 skrll if (line == 0xff) 420 1.1 skrll return 1; 421 1.1 skrll 422 1.17 macallan *ihp = line ; 423 1.1 skrll 424 1.1 skrll return 0; 425 1.1 skrll } 426 1.1 skrll 427 1.1 skrll const char * 428 1.2 christos dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 429 1.1 skrll { 430 1.2 christos snprintf(buf, len, "irq %ld", ih); 431 1.1 skrll return buf; 432 1.1 skrll } 433 1.1 skrll 434 1.1 skrll extern int cold; 435 1.1 skrll 436 1.1 skrll 437 1.1 skrll void * 438 1.1 skrll dino_intr_establish(void *v, pci_intr_handle_t ih, 439 1.1 skrll int pri, int (*handler)(void *), void *arg) 440 1.1 skrll { 441 1.1 skrll struct dino_softc *sc = v; 442 1.1 skrll 443 1.1 skrll return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih); 444 1.1 skrll } 445 1.1 skrll 446 1.1 skrll void 447 1.1 skrll dino_intr_disestablish(void *v, void *cookie) 448 1.1 skrll { 449 1.1 skrll /* XXX Implement me */ 450 1.1 skrll } 451 1.1 skrll 452 1.1 skrll 453 1.1 skrll #if NCARDBUS > 0 454 1.1 skrll void * 455 1.1 skrll dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io) 456 1.1 skrll { 457 1.1 skrll struct dino_softc *sc = pa->pa_pc->_cookie; 458 1.1 skrll struct extent *ex; 459 1.1 skrll bus_space_tag_t tag; 460 1.1 skrll bus_addr_t start; 461 1.1 skrll bus_size_t size; 462 1.1 skrll 463 1.1 skrll if (io) { 464 1.1 skrll ex = sc->sc_ioex; 465 1.1 skrll tag = pa->pa_iot; 466 1.1 skrll start = 0xa000; 467 1.1 skrll size = 0x1000; 468 1.1 skrll } else { 469 1.1 skrll ex = hppa_io_extent; 470 1.1 skrll tag = pa->pa_memt; 471 1.1 skrll start = ex->ex_start; /* XXX or 0xf0800000? */ 472 1.1 skrll size = DINO_MEM_CHUNK; 473 1.1 skrll } 474 1.1 skrll 475 1.1 skrll if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 476 1.1 skrll EX_NOBOUNDARY, EX_NOWAIT, &start)) 477 1.1 skrll return NULL; 478 1.1 skrll extent_free(ex, start, size, EX_NOWAIT); 479 1.1 skrll return rbus_new_root_share(tag, ex, start, size, start); 480 1.1 skrll } 481 1.1 skrll #endif 482 1.1 skrll 483 1.1 skrll int 484 1.1 skrll dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 485 1.1 skrll int flags, bus_space_handle_t *bshp) 486 1.1 skrll { 487 1.1 skrll struct dino_softc *sc = v; 488 1.1 skrll int error; 489 1.1 skrll 490 1.1 skrll if (!(flags & BUS_SPACE_MAP_NOEXTENT) && 491 1.1 skrll (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 492 1.1 skrll return error; 493 1.1 skrll 494 1.1 skrll if (bshp) 495 1.1 skrll *bshp = bpa; 496 1.1 skrll 497 1.1 skrll return 0; 498 1.1 skrll } 499 1.1 skrll 500 1.1 skrll int 501 1.1 skrll dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 502 1.1 skrll int flags, bus_space_handle_t *bshp) 503 1.1 skrll { 504 1.1 skrll struct dino_softc *sc = v; 505 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 506 1.1 skrll uint32_t reg; 507 1.1 skrll int error; 508 1.1 skrll 509 1.1 skrll reg = r->io_addr_en; 510 1.1 skrll reg |= 1 << ((bpa >> 23) & 0x1f); 511 1.1 skrll #ifdef DEBUG 512 1.1 skrll if (reg & 0x80000001) 513 1.1 skrll panic("mapping outside the mem extent range"); 514 1.1 skrll #endif 515 1.1 skrll if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) 516 1.1 skrll return error; 517 1.1 skrll ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; 518 1.1 skrll /* map into the upper bus space, if not yet mapped this 8M */ 519 1.1 skrll if (reg != r->io_addr_en) 520 1.1 skrll r->io_addr_en = reg; 521 1.1 skrll return 0; 522 1.1 skrll } 523 1.1 skrll 524 1.1 skrll int 525 1.1 skrll dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 526 1.1 skrll bus_size_t size, bus_space_handle_t *nbshp) 527 1.1 skrll { 528 1.1 skrll *nbshp = bsh + offset; 529 1.1 skrll return 0; 530 1.1 skrll } 531 1.1 skrll 532 1.1 skrll int 533 1.1 skrll dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 534 1.1 skrll bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 535 1.1 skrll bus_space_handle_t *bshp) 536 1.1 skrll { 537 1.1 skrll struct dino_softc *sc = v; 538 1.1 skrll struct extent *ex = sc->sc_ioex; 539 1.1 skrll bus_addr_t bpa; 540 1.1 skrll int error; 541 1.1 skrll 542 1.1 skrll if (rstart < ex->ex_start || rend > ex->ex_end) 543 1.1 skrll panic("dino_ioalloc: bad region start/end"); 544 1.1 skrll 545 1.1 skrll if ((error = extent_alloc_subregion(ex, rstart, rend, size, 546 1.1 skrll align, boundary, EX_NOWAIT, &bpa))) 547 1.1 skrll return error; 548 1.1 skrll 549 1.1 skrll if (addrp) 550 1.1 skrll *addrp = bpa; 551 1.1 skrll if (bshp) 552 1.1 skrll *bshp = bpa; 553 1.1 skrll 554 1.1 skrll return 0; 555 1.1 skrll } 556 1.1 skrll 557 1.1 skrll int 558 1.1 skrll dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 559 1.1 skrll bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 560 1.1 skrll bus_space_handle_t *bshp) 561 1.1 skrll { 562 1.1 skrll struct dino_softc *sc = v; 563 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 564 1.1 skrll uint32_t reg; 565 1.1 skrll int i, error; 566 1.1 skrll 567 1.1 skrll /* 568 1.1 skrll * Allow allocation only when PCI MEM is already mapped. 569 1.1 skrll * Needed to avoid allocation of I/O space used by devices that 570 1.1 skrll * have no driver in the current kernel. 571 1.1 skrll * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. 572 1.1 skrll */ 573 1.1 skrll reg = r->io_addr_en; 574 1.1 skrll if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) 575 1.1 skrll return -1; 576 1.1 skrll /* Find used PCI MEM and narrow allocateble region down to it. */ 577 1.1 skrll for (i = 1; i < 31; i++) 578 1.1 skrll if ((reg & 1 << i) != 0) { 579 1.1 skrll rstart = HPPA_IOSPACE | i << 23; 580 1.1 skrll rend = (HPPA_IOSPACE | (i + 1) << 23) - 1; 581 1.1 skrll break; 582 1.1 skrll } 583 1.1 skrll if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, 584 1.1 skrll boundary, flags, addrp, bshp))) 585 1.1 skrll return error; 586 1.1 skrll ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; 587 1.1 skrll return 0; 588 1.1 skrll } 589 1.1 skrll 590 1.1 skrll void 591 1.1 skrll dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 592 1.1 skrll { 593 1.1 skrll struct dino_softc *sc = v; 594 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 595 1.1 skrll 596 1.1 skrll if (bsh & HPPA_IOSPACE) { 597 1.1 skrll bus_space_unmap(sc->sc_bt, bsh, size); 598 1.1 skrll if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) 599 1.1 skrll /* Unmap the upper PCI MEM space. */ 600 1.1 skrll r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); 601 1.1 skrll } else { 602 1.1 skrll /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ 603 1.1 skrll if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) 604 1.1 skrll printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 605 1.1 skrll "dino_unmap: can't free region\n", bsh, size); 606 1.1 skrll } 607 1.1 skrll } 608 1.1 skrll 609 1.1 skrll void 610 1.1 skrll dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 611 1.1 skrll { 612 1.1 skrll /* should be enough */ 613 1.1 skrll dino_unmap(v, bh, size); 614 1.1 skrll } 615 1.1 skrll 616 1.1 skrll void 617 1.1 skrll dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 618 1.1 skrll { 619 1.1 skrll sync_caches(); 620 1.1 skrll } 621 1.1 skrll 622 1.1 skrll void* 623 1.1 skrll dino_vaddr(void *v, bus_space_handle_t h) 624 1.1 skrll { 625 1.1 skrll struct dino_softc *sc = v; 626 1.1 skrll 627 1.1 skrll return bus_space_vaddr(sc->sc_bt, h); 628 1.1 skrll } 629 1.1 skrll 630 1.1 skrll paddr_t 631 1.1 skrll dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 632 1.1 skrll { 633 1.10 macallan return btop(addr + off); 634 1.1 skrll } 635 1.1 skrll 636 1.1 skrll uint8_t 637 1.1 skrll dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 638 1.1 skrll { 639 1.1 skrll h += o; 640 1.1 skrll if (h & HPPA_IOSPACE) 641 1.1 skrll return *(volatile uint8_t *)h; 642 1.1 skrll else { 643 1.1 skrll struct dino_softc *sc = v; 644 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 645 1.1 skrll 646 1.1 skrll r->pci_addr = h; 647 1.1 skrll return *((volatile uint8_t *)&r->pci_io_data + (h & 3)); 648 1.1 skrll } 649 1.1 skrll } 650 1.1 skrll 651 1.1 skrll uint16_t 652 1.1 skrll dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 653 1.1 skrll { 654 1.1 skrll volatile uint16_t *p; 655 1.1 skrll 656 1.1 skrll h += o; 657 1.1 skrll if (h & HPPA_IOSPACE) 658 1.1 skrll p = (volatile uint16_t *)h; 659 1.1 skrll else { 660 1.1 skrll struct dino_softc *sc = v; 661 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 662 1.1 skrll 663 1.1 skrll r->pci_addr = h; 664 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 665 1.1 skrll if (h & 2) 666 1.1 skrll p++; 667 1.1 skrll } 668 1.1 skrll return le16toh(*p); 669 1.1 skrll } 670 1.1 skrll 671 1.1 skrll uint32_t 672 1.1 skrll dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 673 1.1 skrll { 674 1.1 skrll uint32_t data; 675 1.1 skrll 676 1.1 skrll h += o; 677 1.1 skrll if (h & HPPA_IOSPACE) 678 1.1 skrll data = *(volatile uint32_t *)h; 679 1.1 skrll else { 680 1.1 skrll struct dino_softc *sc = v; 681 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 682 1.1 skrll 683 1.1 skrll r->pci_addr = h; 684 1.1 skrll data = r->pci_io_data; 685 1.1 skrll } 686 1.1 skrll 687 1.1 skrll return le32toh(data); 688 1.1 skrll } 689 1.1 skrll 690 1.1 skrll uint64_t 691 1.1 skrll dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 692 1.1 skrll { 693 1.1 skrll uint64_t data; 694 1.1 skrll 695 1.1 skrll h += o; 696 1.1 skrll if (h & HPPA_IOSPACE) 697 1.1 skrll data = *(volatile uint64_t *)h; 698 1.1 skrll else 699 1.1 skrll panic("dino_r8: not implemented"); 700 1.1 skrll 701 1.1 skrll return le64toh(data); 702 1.1 skrll } 703 1.1 skrll 704 1.17 macallan uint16_t 705 1.17 macallan dino_rs2(void *v, bus_space_handle_t h, bus_size_t o) 706 1.17 macallan { 707 1.17 macallan volatile uint16_t *p; 708 1.17 macallan 709 1.17 macallan h += o; 710 1.17 macallan if (h & HPPA_IOSPACE) 711 1.17 macallan p = (volatile uint16_t *)h; 712 1.17 macallan else { 713 1.17 macallan struct dino_softc *sc = v; 714 1.17 macallan volatile struct dino_regs *r = sc->sc_regs; 715 1.17 macallan 716 1.17 macallan r->pci_addr = h; 717 1.17 macallan p = (volatile uint16_t *)&r->pci_io_data; 718 1.17 macallan if (h & 2) 719 1.17 macallan p++; 720 1.17 macallan } 721 1.17 macallan return *p; 722 1.17 macallan } 723 1.17 macallan 724 1.17 macallan uint32_t 725 1.17 macallan dino_rs4(void *v, bus_space_handle_t h, bus_size_t o) 726 1.17 macallan { 727 1.17 macallan uint32_t data; 728 1.17 macallan 729 1.17 macallan h += o; 730 1.17 macallan if (h & HPPA_IOSPACE) 731 1.17 macallan data = *(volatile uint32_t *)h; 732 1.17 macallan else { 733 1.17 macallan struct dino_softc *sc = v; 734 1.17 macallan volatile struct dino_regs *r = sc->sc_regs; 735 1.17 macallan 736 1.17 macallan r->pci_addr = h; 737 1.17 macallan data = r->pci_io_data; 738 1.17 macallan } 739 1.17 macallan 740 1.17 macallan return data; 741 1.17 macallan } 742 1.17 macallan 743 1.17 macallan uint64_t 744 1.17 macallan dino_rs8(void *v, bus_space_handle_t h, bus_size_t o) 745 1.17 macallan { 746 1.17 macallan uint64_t data; 747 1.17 macallan 748 1.17 macallan h += o; 749 1.17 macallan if (h & HPPA_IOSPACE) 750 1.17 macallan data = *(volatile uint64_t *)h; 751 1.17 macallan else 752 1.17 macallan panic("dino_r8: not implemented"); 753 1.17 macallan 754 1.17 macallan return data; 755 1.17 macallan } 756 1.17 macallan 757 1.1 skrll void 758 1.1 skrll dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv) 759 1.1 skrll { 760 1.1 skrll h += o; 761 1.1 skrll if (h & HPPA_IOSPACE) 762 1.1 skrll *(volatile uint8_t *)h = vv; 763 1.1 skrll else { 764 1.1 skrll struct dino_softc *sc = v; 765 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 766 1.1 skrll 767 1.1 skrll r->pci_addr = h; 768 1.1 skrll *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv; 769 1.1 skrll } 770 1.1 skrll } 771 1.1 skrll 772 1.1 skrll void 773 1.1 skrll dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 774 1.1 skrll { 775 1.1 skrll volatile uint16_t *p; 776 1.1 skrll 777 1.1 skrll h += o; 778 1.1 skrll if (h & HPPA_IOSPACE) 779 1.1 skrll p = (volatile uint16_t *)h; 780 1.1 skrll else { 781 1.1 skrll struct dino_softc *sc = v; 782 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 783 1.1 skrll 784 1.1 skrll r->pci_addr = h; 785 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 786 1.1 skrll if (h & 2) 787 1.1 skrll p++; 788 1.1 skrll } 789 1.1 skrll 790 1.1 skrll *p = htole16(vv); 791 1.1 skrll } 792 1.1 skrll 793 1.1 skrll void 794 1.1 skrll dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 795 1.1 skrll { 796 1.1 skrll h += o; 797 1.1 skrll vv = htole32(vv); 798 1.1 skrll if (h & HPPA_IOSPACE) 799 1.1 skrll *(volatile uint32_t *)h = vv; 800 1.1 skrll else { 801 1.1 skrll struct dino_softc *sc = v; 802 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 803 1.1 skrll 804 1.1 skrll r->pci_addr = h; 805 1.1 skrll r->pci_io_data = vv; 806 1.1 skrll } 807 1.1 skrll } 808 1.1 skrll 809 1.1 skrll void 810 1.1 skrll dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 811 1.1 skrll { 812 1.1 skrll h += o; 813 1.1 skrll if (h & HPPA_IOSPACE) 814 1.1 skrll *(volatile uint64_t *)h = htole64(vv); 815 1.1 skrll else 816 1.1 skrll panic("dino_w8: not implemented"); 817 1.1 skrll } 818 1.1 skrll 819 1.17 macallan void 820 1.17 macallan dino_ws2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 821 1.17 macallan { 822 1.17 macallan volatile uint16_t *p; 823 1.17 macallan 824 1.17 macallan h += o; 825 1.17 macallan if (h & HPPA_IOSPACE) 826 1.17 macallan p = (volatile uint16_t *)h; 827 1.17 macallan else { 828 1.17 macallan struct dino_softc *sc = v; 829 1.17 macallan volatile struct dino_regs *r = sc->sc_regs; 830 1.17 macallan 831 1.17 macallan r->pci_addr = h; 832 1.17 macallan p = (volatile uint16_t *)&r->pci_io_data; 833 1.17 macallan if (h & 2) 834 1.17 macallan p++; 835 1.17 macallan } 836 1.17 macallan 837 1.17 macallan *p = vv; 838 1.17 macallan } 839 1.17 macallan 840 1.17 macallan void 841 1.17 macallan dino_ws4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 842 1.17 macallan { 843 1.17 macallan h += o; 844 1.17 macallan if (h & HPPA_IOSPACE) 845 1.17 macallan *(volatile uint32_t *)h = vv; 846 1.17 macallan else { 847 1.17 macallan struct dino_softc *sc = v; 848 1.17 macallan volatile struct dino_regs *r = sc->sc_regs; 849 1.17 macallan 850 1.17 macallan r->pci_addr = h; 851 1.17 macallan r->pci_io_data = vv; 852 1.17 macallan } 853 1.17 macallan } 854 1.17 macallan 855 1.17 macallan void 856 1.17 macallan dino_ws8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 857 1.17 macallan { 858 1.17 macallan h += o; 859 1.17 macallan if (h & HPPA_IOSPACE) 860 1.17 macallan *(volatile uint64_t *)h = vv; 861 1.17 macallan else 862 1.17 macallan panic("dino_w8: not implemented"); 863 1.17 macallan } 864 1.1 skrll 865 1.1 skrll void 866 1.1 skrll dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 867 1.1 skrll { 868 1.1 skrll volatile uint8_t *p; 869 1.1 skrll 870 1.1 skrll h += o; 871 1.1 skrll if (h & HPPA_IOSPACE) 872 1.1 skrll p = (volatile uint8_t *)h; 873 1.1 skrll else { 874 1.1 skrll struct dino_softc *sc = v; 875 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 876 1.1 skrll 877 1.1 skrll r->pci_addr = h; 878 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 879 1.1 skrll } 880 1.1 skrll 881 1.1 skrll while (c--) 882 1.1 skrll *a++ = *p; 883 1.1 skrll } 884 1.1 skrll 885 1.1 skrll void 886 1.1 skrll dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 887 1.1 skrll { 888 1.1 skrll volatile uint16_t *p; 889 1.1 skrll 890 1.1 skrll h += o; 891 1.1 skrll if (h & HPPA_IOSPACE) 892 1.1 skrll p = (volatile uint16_t *)h; 893 1.1 skrll else { 894 1.1 skrll struct dino_softc *sc = v; 895 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 896 1.1 skrll 897 1.1 skrll r->pci_addr = h; 898 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 899 1.1 skrll if (h & 2) 900 1.1 skrll p++; 901 1.1 skrll } 902 1.1 skrll 903 1.1 skrll while (c--) 904 1.1 skrll *a++ = le16toh(*p); 905 1.1 skrll } 906 1.1 skrll 907 1.1 skrll void 908 1.1 skrll dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 909 1.1 skrll { 910 1.1 skrll volatile uint32_t *p; 911 1.1 skrll 912 1.1 skrll h += o; 913 1.1 skrll if (h & HPPA_IOSPACE) 914 1.1 skrll p = (volatile uint32_t *)h; 915 1.1 skrll else { 916 1.1 skrll struct dino_softc *sc = v; 917 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 918 1.1 skrll 919 1.1 skrll r->pci_addr = h; 920 1.1 skrll p = (volatile uint32_t *)&r->pci_io_data; 921 1.1 skrll } 922 1.1 skrll 923 1.1 skrll while (c--) 924 1.1 skrll *a++ = le32toh(*p); 925 1.1 skrll } 926 1.1 skrll 927 1.1 skrll void 928 1.1 skrll dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 929 1.1 skrll { 930 1.1 skrll panic("dino_rm_8: not implemented"); 931 1.1 skrll } 932 1.1 skrll 933 1.1 skrll void 934 1.1 skrll dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 935 1.1 skrll { 936 1.1 skrll volatile uint8_t *p; 937 1.1 skrll 938 1.1 skrll h += o; 939 1.1 skrll if (h & HPPA_IOSPACE) 940 1.1 skrll p = (volatile uint8_t *)h; 941 1.1 skrll else { 942 1.1 skrll struct dino_softc *sc = v; 943 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 944 1.1 skrll 945 1.1 skrll r->pci_addr = h; 946 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 947 1.1 skrll } 948 1.1 skrll 949 1.1 skrll while (c--) 950 1.1 skrll *p = *a++; 951 1.1 skrll } 952 1.1 skrll 953 1.1 skrll void 954 1.1 skrll dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 955 1.1 skrll { 956 1.1 skrll volatile uint16_t *p; 957 1.1 skrll 958 1.1 skrll h += o; 959 1.1 skrll if (h & HPPA_IOSPACE) 960 1.1 skrll p = (volatile uint16_t *)h; 961 1.1 skrll else { 962 1.1 skrll struct dino_softc *sc = v; 963 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 964 1.1 skrll 965 1.1 skrll r->pci_addr = h; 966 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 967 1.1 skrll if (h & 2) 968 1.1 skrll p++; 969 1.1 skrll } 970 1.1 skrll 971 1.1 skrll while (c--) 972 1.1 skrll *p = htole16(*a++); 973 1.1 skrll } 974 1.1 skrll 975 1.1 skrll void 976 1.1 skrll dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 977 1.1 skrll { 978 1.1 skrll volatile uint32_t *p; 979 1.1 skrll 980 1.1 skrll h += o; 981 1.1 skrll if (h & HPPA_IOSPACE) 982 1.1 skrll p = (volatile uint32_t *)h; 983 1.1 skrll else { 984 1.1 skrll struct dino_softc *sc = v; 985 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 986 1.1 skrll 987 1.1 skrll r->pci_addr = h; 988 1.1 skrll p = (volatile uint32_t *)&r->pci_io_data; 989 1.1 skrll } 990 1.1 skrll 991 1.1 skrll while (c--) 992 1.1 skrll *p = htole32(*a++); 993 1.1 skrll } 994 1.1 skrll 995 1.1 skrll void 996 1.1 skrll dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 997 1.1 skrll { 998 1.1 skrll panic("dino_wm_8: not implemented"); 999 1.1 skrll } 1000 1.1 skrll 1001 1.1 skrll void 1002 1.1 skrll dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1003 1.1 skrll { 1004 1.1 skrll volatile uint8_t *p; 1005 1.1 skrll 1006 1.1 skrll h += o; 1007 1.1 skrll if (h & HPPA_IOSPACE) 1008 1.1 skrll p = (volatile uint8_t *)h; 1009 1.1 skrll else { 1010 1.1 skrll struct dino_softc *sc = v; 1011 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1012 1.1 skrll 1013 1.1 skrll r->pci_addr = h; 1014 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1015 1.1 skrll } 1016 1.1 skrll 1017 1.1 skrll while (c--) 1018 1.1 skrll *p = vv; 1019 1.1 skrll } 1020 1.1 skrll 1021 1.1 skrll void 1022 1.1 skrll dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1023 1.1 skrll { 1024 1.1 skrll volatile uint16_t *p; 1025 1.1 skrll 1026 1.1 skrll h += o; 1027 1.1 skrll if (h & HPPA_IOSPACE) 1028 1.1 skrll p = (volatile uint16_t *)h; 1029 1.1 skrll else { 1030 1.1 skrll struct dino_softc *sc = v; 1031 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1032 1.1 skrll 1033 1.1 skrll r->pci_addr = h; 1034 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1035 1.1 skrll if (h & 2) 1036 1.1 skrll p++; 1037 1.1 skrll } 1038 1.1 skrll 1039 1.1 skrll while (c--) 1040 1.1 skrll *p = htole16(vv); 1041 1.1 skrll } 1042 1.1 skrll 1043 1.1 skrll void 1044 1.1 skrll dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1045 1.1 skrll { 1046 1.1 skrll volatile uint32_t *p; 1047 1.1 skrll 1048 1.1 skrll h += o; 1049 1.1 skrll if (h & HPPA_IOSPACE) 1050 1.1 skrll p = (volatile uint32_t *)h; 1051 1.1 skrll else { 1052 1.1 skrll struct dino_softc *sc = v; 1053 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1054 1.1 skrll 1055 1.1 skrll r->pci_addr = h; 1056 1.1 skrll p = (volatile uint32_t *)&r->pci_io_data; 1057 1.1 skrll } 1058 1.1 skrll 1059 1.1 skrll while (c--) 1060 1.1 skrll *p = htole32(vv); 1061 1.1 skrll } 1062 1.1 skrll 1063 1.1 skrll void 1064 1.1 skrll dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1065 1.1 skrll { 1066 1.1 skrll panic("dino_sm_8: not implemented"); 1067 1.1 skrll } 1068 1.1 skrll 1069 1.1 skrll void 1070 1.1 skrll dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 1071 1.1 skrll uint16_t *a, bus_size_t c) 1072 1.1 skrll { 1073 1.1 skrll volatile uint16_t *p; 1074 1.1 skrll 1075 1.1 skrll h += o; 1076 1.1 skrll if (h & HPPA_IOSPACE) 1077 1.1 skrll p = (volatile uint16_t *)h; 1078 1.1 skrll else { 1079 1.1 skrll struct dino_softc *sc = v; 1080 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1081 1.1 skrll 1082 1.1 skrll r->pci_addr = h; 1083 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1084 1.1 skrll if (h & 2) 1085 1.1 skrll p++; 1086 1.1 skrll } 1087 1.1 skrll 1088 1.1 skrll while (c--) 1089 1.1 skrll *a++ = *p; 1090 1.1 skrll } 1091 1.1 skrll 1092 1.1 skrll void 1093 1.1 skrll dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1094 1.1 skrll uint32_t *a, bus_size_t c) 1095 1.1 skrll { 1096 1.1 skrll volatile uint32_t *p; 1097 1.1 skrll 1098 1.1 skrll h += o; 1099 1.1 skrll if (h & HPPA_IOSPACE) 1100 1.1 skrll p = (volatile uint32_t *)h; 1101 1.1 skrll else { 1102 1.1 skrll struct dino_softc *sc = v; 1103 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1104 1.1 skrll 1105 1.1 skrll r->pci_addr = h; 1106 1.1 skrll p = (volatile uint32_t *)&r->pci_io_data; 1107 1.1 skrll } 1108 1.1 skrll 1109 1.1 skrll while (c--) 1110 1.1 skrll *a++ = *p; 1111 1.1 skrll } 1112 1.1 skrll 1113 1.1 skrll void 1114 1.1 skrll dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1115 1.1 skrll uint64_t *a, bus_size_t c) 1116 1.1 skrll { 1117 1.1 skrll panic("dino_rrm_8: not implemented"); 1118 1.1 skrll } 1119 1.1 skrll 1120 1.1 skrll void 1121 1.1 skrll dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 1122 1.1 skrll const uint16_t *a, bus_size_t c) 1123 1.1 skrll { 1124 1.1 skrll volatile uint16_t *p; 1125 1.1 skrll 1126 1.1 skrll h += o; 1127 1.1 skrll if (h & HPPA_IOSPACE) 1128 1.1 skrll p = (volatile uint16_t *)h; 1129 1.1 skrll else { 1130 1.1 skrll struct dino_softc *sc = v; 1131 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1132 1.1 skrll 1133 1.1 skrll r->pci_addr = h; 1134 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1135 1.1 skrll if (h & 2) 1136 1.1 skrll p++; 1137 1.1 skrll } 1138 1.1 skrll 1139 1.1 skrll while (c--) 1140 1.1 skrll *p = *a++; 1141 1.1 skrll } 1142 1.1 skrll 1143 1.1 skrll void 1144 1.1 skrll dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1145 1.1 skrll const uint32_t *a, bus_size_t c) 1146 1.1 skrll { 1147 1.1 skrll volatile uint32_t *p; 1148 1.1 skrll 1149 1.1 skrll h += o; 1150 1.1 skrll if (h & HPPA_IOSPACE) 1151 1.1 skrll p = (volatile uint32_t *)h; 1152 1.1 skrll else { 1153 1.1 skrll struct dino_softc *sc = v; 1154 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1155 1.1 skrll 1156 1.1 skrll r->pci_addr = h; 1157 1.1 skrll p = (volatile uint32_t *)&r->pci_io_data; 1158 1.1 skrll } 1159 1.1 skrll 1160 1.1 skrll while (c--) 1161 1.1 skrll *p = *a++; 1162 1.1 skrll } 1163 1.1 skrll 1164 1.1 skrll void 1165 1.1 skrll dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1166 1.1 skrll const uint64_t *a, bus_size_t c) 1167 1.1 skrll { 1168 1.1 skrll panic("dino_wrm_8: not implemented"); 1169 1.1 skrll } 1170 1.1 skrll 1171 1.1 skrll void 1172 1.1 skrll dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 1173 1.1 skrll { 1174 1.1 skrll volatile uint8_t *p; 1175 1.1 skrll 1176 1.1 skrll h += o; 1177 1.1 skrll if (h & HPPA_IOSPACE) { 1178 1.1 skrll p = (volatile uint8_t *)h; 1179 1.1 skrll while (c--) 1180 1.1 skrll *a++ = *p++; 1181 1.1 skrll } else { 1182 1.1 skrll struct dino_softc *sc = v; 1183 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1184 1.1 skrll 1185 1.1 skrll for (; c--; h++) { 1186 1.1 skrll r->pci_addr = h; 1187 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1188 1.1 skrll *a++ = *p; 1189 1.1 skrll } 1190 1.1 skrll } 1191 1.1 skrll } 1192 1.1 skrll 1193 1.1 skrll void 1194 1.1 skrll dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 1195 1.1 skrll { 1196 1.1 skrll volatile uint16_t *p, data; 1197 1.1 skrll 1198 1.1 skrll h += o; 1199 1.1 skrll if (h & HPPA_IOSPACE) { 1200 1.1 skrll p = (volatile uint16_t *)h; 1201 1.1 skrll while (c--) { 1202 1.1 skrll data = *p++; 1203 1.1 skrll *a++ = le16toh(data); 1204 1.1 skrll } 1205 1.1 skrll } else { 1206 1.1 skrll struct dino_softc *sc = v; 1207 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1208 1.1 skrll 1209 1.1 skrll for (; c--; h += 2) { 1210 1.1 skrll r->pci_addr = h; 1211 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1212 1.1 skrll if (h & 2) 1213 1.1 skrll p++; 1214 1.1 skrll data = *p; 1215 1.1 skrll *a++ = le16toh(data); 1216 1.1 skrll } 1217 1.1 skrll } 1218 1.1 skrll } 1219 1.1 skrll 1220 1.1 skrll void 1221 1.1 skrll dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 1222 1.1 skrll { 1223 1.1 skrll volatile uint32_t *p, data; 1224 1.1 skrll 1225 1.1 skrll h += o; 1226 1.1 skrll if (h & HPPA_IOSPACE) { 1227 1.1 skrll p = (volatile uint32_t *)h; 1228 1.1 skrll while (c--) { 1229 1.1 skrll data = *p++; 1230 1.1 skrll *a++ = le32toh(data); 1231 1.1 skrll } 1232 1.1 skrll } else { 1233 1.1 skrll struct dino_softc *sc = v; 1234 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1235 1.1 skrll 1236 1.1 skrll for (; c--; h += 4) { 1237 1.1 skrll r->pci_addr = h; 1238 1.1 skrll data = r->pci_io_data; 1239 1.1 skrll *a++ = le32toh(data); 1240 1.1 skrll } 1241 1.1 skrll } 1242 1.1 skrll } 1243 1.1 skrll 1244 1.1 skrll void 1245 1.1 skrll dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 1246 1.1 skrll { 1247 1.1 skrll panic("dino_rr_8: not implemented"); 1248 1.1 skrll } 1249 1.1 skrll 1250 1.1 skrll void 1251 1.1 skrll dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 1252 1.1 skrll { 1253 1.1 skrll volatile uint8_t *p; 1254 1.1 skrll 1255 1.1 skrll h += o; 1256 1.1 skrll if (h & HPPA_IOSPACE) { 1257 1.1 skrll p = (volatile uint8_t *)h; 1258 1.1 skrll while (c--) 1259 1.1 skrll *p++ = *a++; 1260 1.1 skrll } else { 1261 1.1 skrll struct dino_softc *sc = v; 1262 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1263 1.1 skrll 1264 1.1 skrll for (; c--; h++) { 1265 1.1 skrll r->pci_addr = h; 1266 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1267 1.1 skrll *p = *a++; 1268 1.1 skrll } 1269 1.1 skrll } 1270 1.1 skrll } 1271 1.1 skrll 1272 1.1 skrll void 1273 1.1 skrll dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 1274 1.1 skrll { 1275 1.1 skrll volatile uint16_t *p, data; 1276 1.1 skrll 1277 1.1 skrll h += o; 1278 1.1 skrll if (h & HPPA_IOSPACE) { 1279 1.1 skrll p = (volatile uint16_t *)h; 1280 1.1 skrll while (c--) { 1281 1.1 skrll data = *a++; 1282 1.1 skrll *p++ = htole16(data); 1283 1.1 skrll } 1284 1.1 skrll } else { 1285 1.1 skrll struct dino_softc *sc = v; 1286 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1287 1.1 skrll 1288 1.1 skrll for (; c--; h += 2) { 1289 1.1 skrll r->pci_addr = h; 1290 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1291 1.1 skrll if (h & 2) 1292 1.1 skrll p++; 1293 1.1 skrll data = *a++; 1294 1.1 skrll *p = htole16(data); 1295 1.1 skrll } 1296 1.1 skrll } 1297 1.1 skrll } 1298 1.1 skrll 1299 1.1 skrll void 1300 1.1 skrll dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 1301 1.1 skrll { 1302 1.1 skrll volatile uint32_t *p, data; 1303 1.1 skrll 1304 1.1 skrll h += o; 1305 1.1 skrll if (h & HPPA_IOSPACE) { 1306 1.1 skrll p = (volatile uint32_t *)h; 1307 1.1 skrll while (c--) { 1308 1.1 skrll data = *a++; 1309 1.1 skrll *p++ = htole32(data); 1310 1.1 skrll } 1311 1.1 skrll } else { 1312 1.1 skrll struct dino_softc *sc = v; 1313 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1314 1.1 skrll 1315 1.1 skrll for (; c--; h += 4) { 1316 1.1 skrll r->pci_addr = h; 1317 1.1 skrll data = *a++; 1318 1.1 skrll r->pci_io_data = htole32(data); 1319 1.1 skrll } 1320 1.1 skrll } 1321 1.1 skrll } 1322 1.1 skrll 1323 1.1 skrll void 1324 1.1 skrll dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 1325 1.1 skrll { 1326 1.1 skrll panic("dino_wr_8: not implemented"); 1327 1.1 skrll } 1328 1.1 skrll 1329 1.1 skrll void 1330 1.1 skrll dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1331 1.1 skrll uint16_t *a, bus_size_t c) 1332 1.1 skrll { 1333 1.1 skrll volatile uint16_t *p; 1334 1.1 skrll 1335 1.1 skrll h += o; 1336 1.1 skrll if (h & HPPA_IOSPACE) { 1337 1.1 skrll p = (volatile uint16_t *)h; 1338 1.1 skrll while (c--) 1339 1.1 skrll *a++ = *p++; 1340 1.1 skrll } else { 1341 1.1 skrll struct dino_softc *sc = v; 1342 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1343 1.1 skrll 1344 1.1 skrll for (; c--; h += 2) { 1345 1.1 skrll r->pci_addr = h; 1346 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1347 1.1 skrll if (h & 2) 1348 1.1 skrll p++; 1349 1.1 skrll *a++ = *p; 1350 1.1 skrll } 1351 1.1 skrll } 1352 1.1 skrll } 1353 1.1 skrll 1354 1.1 skrll void 1355 1.1 skrll dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1356 1.1 skrll uint32_t *a, bus_size_t c) 1357 1.1 skrll { 1358 1.1 skrll volatile uint32_t *p; 1359 1.1 skrll 1360 1.1 skrll h += o; 1361 1.1 skrll if (h & HPPA_IOSPACE) { 1362 1.1 skrll p = (volatile uint32_t *)h; 1363 1.1 skrll while (c--) 1364 1.1 skrll *a++ = *p++; 1365 1.1 skrll } else { 1366 1.1 skrll struct dino_softc *sc = v; 1367 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1368 1.1 skrll 1369 1.1 skrll for (; c--; h += 4) { 1370 1.1 skrll r->pci_addr = h; 1371 1.1 skrll *a++ = r->pci_io_data; 1372 1.1 skrll } 1373 1.1 skrll } 1374 1.1 skrll } 1375 1.1 skrll 1376 1.1 skrll void 1377 1.1 skrll dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1378 1.1 skrll uint64_t *a, bus_size_t c) 1379 1.1 skrll { 1380 1.1 skrll panic("dino_rrr_8: not implemented"); 1381 1.1 skrll } 1382 1.1 skrll 1383 1.1 skrll void 1384 1.1 skrll dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1385 1.1 skrll const uint16_t *a, bus_size_t c) 1386 1.1 skrll { 1387 1.1 skrll volatile uint16_t *p; 1388 1.1 skrll 1389 1.1 skrll h += o; 1390 1.1 skrll if (h & HPPA_IOSPACE) { 1391 1.1 skrll p = (volatile uint16_t *)h; 1392 1.1 skrll while (c--) 1393 1.1 skrll *p++ = *a++; 1394 1.1 skrll } else { 1395 1.1 skrll struct dino_softc *sc = v; 1396 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1397 1.1 skrll 1398 1.1 skrll for (; c--; h += 2) { 1399 1.1 skrll r->pci_addr = h; 1400 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1401 1.1 skrll if (h & 2) 1402 1.1 skrll p++; 1403 1.1 skrll *p = *a++; 1404 1.1 skrll } 1405 1.1 skrll } 1406 1.1 skrll } 1407 1.1 skrll 1408 1.1 skrll void 1409 1.1 skrll dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1410 1.1 skrll const uint32_t *a, bus_size_t c) 1411 1.1 skrll { 1412 1.1 skrll volatile uint32_t *p; 1413 1.1 skrll 1414 1.1 skrll c /= 4; 1415 1.1 skrll h += o; 1416 1.1 skrll if (h & HPPA_IOSPACE) { 1417 1.1 skrll p = (volatile uint32_t *)h; 1418 1.1 skrll while (c--) 1419 1.1 skrll *p++ = *a++; 1420 1.1 skrll } else { 1421 1.1 skrll struct dino_softc *sc = v; 1422 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1423 1.1 skrll 1424 1.1 skrll for (; c--; h += 4) { 1425 1.1 skrll r->pci_addr = h; 1426 1.1 skrll r->pci_io_data = *a++; 1427 1.1 skrll } 1428 1.1 skrll } 1429 1.1 skrll } 1430 1.1 skrll 1431 1.1 skrll void 1432 1.1 skrll dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1433 1.1 skrll const uint64_t *a, bus_size_t c) 1434 1.1 skrll { 1435 1.1 skrll panic("dino_wrr_8: not implemented"); 1436 1.1 skrll } 1437 1.1 skrll 1438 1.1 skrll void 1439 1.1 skrll dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1440 1.1 skrll { 1441 1.1 skrll volatile uint8_t *p; 1442 1.1 skrll 1443 1.1 skrll h += o; 1444 1.1 skrll if (h & HPPA_IOSPACE) { 1445 1.1 skrll p = (volatile uint8_t *)h; 1446 1.1 skrll while (c--) 1447 1.1 skrll *p++ = vv; 1448 1.1 skrll } else { 1449 1.1 skrll struct dino_softc *sc = v; 1450 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1451 1.1 skrll 1452 1.1 skrll for (; c--; h++) { 1453 1.1 skrll r->pci_addr = h; 1454 1.1 skrll p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1455 1.1 skrll *p = vv; 1456 1.1 skrll } 1457 1.1 skrll } 1458 1.1 skrll } 1459 1.1 skrll 1460 1.1 skrll void 1461 1.1 skrll dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1462 1.1 skrll { 1463 1.1 skrll volatile uint16_t *p; 1464 1.1 skrll 1465 1.1 skrll h += o; 1466 1.1 skrll vv = htole16(vv); 1467 1.1 skrll if (h & HPPA_IOSPACE) { 1468 1.1 skrll p = (volatile uint16_t *)h; 1469 1.1 skrll while (c--) 1470 1.1 skrll *p++ = vv; 1471 1.1 skrll } else { 1472 1.1 skrll struct dino_softc *sc = v; 1473 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1474 1.1 skrll 1475 1.1 skrll for (; c--; h += 2) { 1476 1.1 skrll r->pci_addr = h; 1477 1.1 skrll p = (volatile uint16_t *)&r->pci_io_data; 1478 1.1 skrll if (h & 2) 1479 1.1 skrll p++; 1480 1.1 skrll *p = vv; 1481 1.1 skrll } 1482 1.1 skrll } 1483 1.1 skrll } 1484 1.1 skrll 1485 1.1 skrll void 1486 1.1 skrll dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1487 1.1 skrll { 1488 1.1 skrll volatile uint32_t *p; 1489 1.1 skrll 1490 1.1 skrll h += o; 1491 1.1 skrll vv = htole32(vv); 1492 1.1 skrll if (h & HPPA_IOSPACE) { 1493 1.1 skrll p = (volatile uint32_t *)h; 1494 1.1 skrll while (c--) 1495 1.1 skrll *p++ = vv; 1496 1.1 skrll } else { 1497 1.1 skrll struct dino_softc *sc = v; 1498 1.1 skrll volatile struct dino_regs *r = sc->sc_regs; 1499 1.1 skrll 1500 1.1 skrll for (; c--; h += 4) { 1501 1.1 skrll r->pci_addr = h; 1502 1.1 skrll r->pci_io_data = vv; 1503 1.1 skrll } 1504 1.1 skrll } 1505 1.1 skrll } 1506 1.1 skrll 1507 1.1 skrll void 1508 1.1 skrll dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1509 1.1 skrll { 1510 1.1 skrll panic("dino_sr_8: not implemented"); 1511 1.1 skrll } 1512 1.1 skrll 1513 1.1 skrll void 1514 1.1 skrll dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1515 1.1 skrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1516 1.1 skrll { 1517 1.1 skrll while (c--) 1518 1.1 skrll dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1519 1.1 skrll } 1520 1.1 skrll 1521 1.1 skrll void 1522 1.1 skrll dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1523 1.1 skrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1524 1.1 skrll { 1525 1.1 skrll while (c--) { 1526 1.1 skrll dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1527 1.1 skrll o1 += 2; 1528 1.1 skrll o2 += 2; 1529 1.1 skrll } 1530 1.1 skrll } 1531 1.1 skrll 1532 1.1 skrll void 1533 1.1 skrll dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1534 1.1 skrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1535 1.1 skrll { 1536 1.1 skrll while (c--) { 1537 1.1 skrll dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1538 1.1 skrll o1 += 4; 1539 1.1 skrll o2 += 4; 1540 1.1 skrll } 1541 1.1 skrll } 1542 1.1 skrll 1543 1.1 skrll void 1544 1.1 skrll dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1545 1.1 skrll bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1546 1.1 skrll { 1547 1.1 skrll while (c--) { 1548 1.1 skrll dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1549 1.1 skrll o1 += 8; 1550 1.1 skrll o2 += 8; 1551 1.1 skrll } 1552 1.1 skrll } 1553 1.1 skrll 1554 1.1 skrll 1555 1.1 skrll const struct hppa_bus_space_tag dino_iomemt = { 1556 1.1 skrll NULL, 1557 1.1 skrll 1558 1.1 skrll NULL, dino_unmap, dino_subregion, NULL, dino_free, 1559 1.1 skrll dino_barrier, dino_vaddr, dino_mmap, 1560 1.1 skrll dino_r1, dino_r2, dino_r4, dino_r8, 1561 1.17 macallan dino_rs2, dino_rs4, dino_rs8, 1562 1.1 skrll dino_w1, dino_w2, dino_w4, dino_w8, 1563 1.17 macallan dino_ws2, dino_ws4, dino_ws8, 1564 1.1 skrll dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1565 1.1 skrll dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1566 1.1 skrll dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1567 1.1 skrll dino_rrm_2, dino_rrm_4, dino_rrm_8, 1568 1.1 skrll dino_wrm_2, dino_wrm_4, dino_wrm_8, 1569 1.1 skrll dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1570 1.1 skrll dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1571 1.1 skrll dino_rrr_2, dino_rrr_4, dino_rrr_8, 1572 1.1 skrll dino_wrr_2, dino_wrr_4, dino_wrr_8, 1573 1.1 skrll dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1574 1.1 skrll dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1575 1.1 skrll }; 1576 1.1 skrll 1577 1.1 skrll int 1578 1.1 skrll dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1579 1.1 skrll bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1580 1.1 skrll { 1581 1.1 skrll struct dino_softc *sc = v; 1582 1.1 skrll 1583 1.1 skrll /* TODO check the addresses, boundary, enable dma */ 1584 1.1 skrll 1585 1.1 skrll return bus_dmamap_create(sc->sc_dmat, size, nsegments, 1586 1.1 skrll maxsegsz, boundary, flags, dmamp); 1587 1.1 skrll } 1588 1.1 skrll 1589 1.1 skrll void 1590 1.1 skrll dino_dmamap_destroy(void *v, bus_dmamap_t map) 1591 1.1 skrll { 1592 1.1 skrll struct dino_softc *sc = v; 1593 1.1 skrll 1594 1.1 skrll bus_dmamap_destroy(sc->sc_dmat, map); 1595 1.1 skrll } 1596 1.1 skrll 1597 1.1 skrll int 1598 1.1 skrll dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1599 1.1 skrll struct proc *p, int flags) 1600 1.1 skrll { 1601 1.1 skrll struct dino_softc *sc = v; 1602 1.1 skrll 1603 1.1 skrll return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); 1604 1.1 skrll } 1605 1.1 skrll 1606 1.1 skrll int 1607 1.1 skrll dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1608 1.1 skrll { 1609 1.1 skrll struct dino_softc *sc = v; 1610 1.1 skrll 1611 1.1 skrll return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); 1612 1.1 skrll } 1613 1.1 skrll 1614 1.1 skrll int 1615 1.1 skrll dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1616 1.1 skrll { 1617 1.1 skrll struct dino_softc *sc = v; 1618 1.1 skrll 1619 1.1 skrll return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); 1620 1.1 skrll } 1621 1.1 skrll 1622 1.1 skrll int 1623 1.1 skrll dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1624 1.1 skrll int nsegs, bus_size_t size, int flags) 1625 1.1 skrll { 1626 1.1 skrll struct dino_softc *sc = v; 1627 1.1 skrll 1628 1.1 skrll return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); 1629 1.1 skrll } 1630 1.1 skrll 1631 1.1 skrll void 1632 1.1 skrll dino_dmamap_unload(void *v, bus_dmamap_t map) 1633 1.1 skrll { 1634 1.1 skrll struct dino_softc *sc = v; 1635 1.1 skrll 1636 1.1 skrll bus_dmamap_unload(sc->sc_dmat, map); 1637 1.1 skrll } 1638 1.1 skrll 1639 1.1 skrll void 1640 1.1 skrll dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1641 1.1 skrll bus_size_t len, int ops) 1642 1.1 skrll { 1643 1.1 skrll struct dino_softc *sc = v; 1644 1.1 skrll 1645 1.1 skrll return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); 1646 1.1 skrll } 1647 1.1 skrll 1648 1.1 skrll int 1649 1.1 skrll dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1650 1.1 skrll bus_size_t boundary, bus_dma_segment_t *segs, 1651 1.1 skrll int nsegs, int *rsegs, int flags) 1652 1.1 skrll { 1653 1.1 skrll struct dino_softc *sc = v; 1654 1.1 skrll 1655 1.1 skrll return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1656 1.1 skrll segs, nsegs, rsegs, flags); 1657 1.1 skrll } 1658 1.1 skrll 1659 1.1 skrll void 1660 1.1 skrll dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1661 1.1 skrll { 1662 1.1 skrll struct dino_softc *sc = v; 1663 1.1 skrll 1664 1.1 skrll bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1665 1.1 skrll } 1666 1.1 skrll 1667 1.1 skrll int 1668 1.1 skrll dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1669 1.1 skrll void **kvap, int flags) 1670 1.1 skrll { 1671 1.1 skrll struct dino_softc *sc = v; 1672 1.1 skrll 1673 1.1 skrll return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); 1674 1.1 skrll } 1675 1.1 skrll 1676 1.1 skrll void 1677 1.1 skrll dino_dmamem_unmap(void *v, void *kva, size_t size) 1678 1.1 skrll { 1679 1.1 skrll struct dino_softc *sc = v; 1680 1.1 skrll 1681 1.1 skrll bus_dmamem_unmap(sc->sc_dmat, kva, size); 1682 1.1 skrll } 1683 1.1 skrll 1684 1.1 skrll paddr_t 1685 1.1 skrll dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1686 1.1 skrll int prot, int flags) 1687 1.1 skrll { 1688 1.1 skrll struct dino_softc *sc = v; 1689 1.1 skrll 1690 1.1 skrll return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); 1691 1.1 skrll } 1692 1.1 skrll 1693 1.1 skrll const struct hppa_bus_dma_tag dino_dmat = { 1694 1.1 skrll NULL, 1695 1.1 skrll dino_dmamap_create, dino_dmamap_destroy, 1696 1.1 skrll dino_dmamap_load, dino_dmamap_load_mbuf, 1697 1.1 skrll dino_dmamap_load_uio, dino_dmamap_load_raw, 1698 1.1 skrll dino_dmamap_unload, dino_dmamap_sync, 1699 1.1 skrll 1700 1.1 skrll dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1701 1.1 skrll dino_dmamem_unmap, dino_dmamem_mmap 1702 1.1 skrll }; 1703 1.1 skrll 1704 1.1 skrll const struct hppa_pci_chipset_tag dino_pc = { 1705 1.15 skrll .pc_attach_hook = dino_attach_hook, 1706 1.15 skrll .pc_bus_maxdevs = dino_maxdevs, 1707 1.15 skrll .pc_make_tag = dino_make_tag, 1708 1.15 skrll .pc_decompose_tag = dino_decompose_tag, 1709 1.15 skrll .pc_conf_read = dino_conf_read, 1710 1.15 skrll .pc_conf_write = dino_conf_write, 1711 1.15 skrll .pc_intr_map = dino_intr_map, 1712 1.15 skrll .pc_intr_string = dino_intr_string, 1713 1.15 skrll .pc_intr_establish = dino_intr_establish, 1714 1.15 skrll .pc_intr_disestablish = dino_intr_disestablish, 1715 1.1 skrll #if NCARDBUS > 0 1716 1.15 skrll .pc_alloc_parent = dino_alloc_parent, 1717 1.1 skrll #endif 1718 1.1 skrll }; 1719 1.1 skrll 1720 1.1 skrll int 1721 1.1 skrll dinomatch(device_t parent, cfdata_t cfdata, void *aux) 1722 1.1 skrll { 1723 1.1 skrll struct confargs *ca = aux; 1724 1.1 skrll 1725 1.1 skrll /* there will be only one */ 1726 1.1 skrll if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 1727 1.1 skrll ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 1728 1.1 skrll return 0; 1729 1.1 skrll 1730 1.1 skrll /* do not match on the elroy family */ 1731 1.1 skrll if (ca->ca_type.iodc_model == 0x78) 1732 1.1 skrll return 0; 1733 1.1 skrll 1734 1.1 skrll return 1; 1735 1.1 skrll } 1736 1.1 skrll 1737 1.1 skrll void 1738 1.1 skrll dinoattach(device_t parent, device_t self, void *aux) 1739 1.1 skrll { 1740 1.1 skrll struct dino_softc *sc = device_private(self); 1741 1.1 skrll struct confargs *ca = (struct confargs *)aux, nca; 1742 1.1 skrll struct pcibus_attach_args pba; 1743 1.1 skrll volatile struct dino_regs *r; 1744 1.1 skrll struct cpu_info *ci = &cpus[0]; 1745 1.1 skrll const char *p = NULL; 1746 1.1 skrll int s, ver; 1747 1.1 skrll 1748 1.1 skrll sc->sc_dv = self; 1749 1.1 skrll sc->sc_bt = ca->ca_iot; 1750 1.1 skrll sc->sc_dmat = ca->ca_dmatag; 1751 1.1 skrll 1752 1.1 skrll ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 1753 1.1 skrll if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 1754 1.1 skrll aprint_error_dev(self, ": can't allocate interrupt"); 1755 1.1 skrll return; 1756 1.1 skrll } 1757 1.1 skrll 1758 1.1 skrll if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1759 1.1 skrll aprint_error(": can't map space\n"); 1760 1.1 skrll return; 1761 1.1 skrll } 1762 1.1 skrll 1763 1.18 riastrad sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1764 1.17 macallan 1765 1.1 skrll #ifdef trust_the_firmware_to_proper_initialize_everything 1766 1.1 skrll r->io_addr_en = 0; 1767 1.1 skrll r->io_control = 0x80; 1768 1.1 skrll r->pamr = 0; 1769 1.1 skrll r->papr = 0; 1770 1.1 skrll r->io_fbb_en |= 1; 1771 1.1 skrll r->damode = 0; 1772 1.13 macallan r->gmask &= ~1; /* allow GSC bus req */ 1773 1.1 skrll r->pciror = 0; 1774 1.1 skrll r->pciwor = 0; 1775 1.1 skrll r->brdg_feat = 0xc0000000; 1776 1.1 skrll #endif 1777 1.1 skrll 1778 1.1 skrll snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1779 1.1 skrll "%s_io", device_xname(self)); 1780 1.6 chs sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1781 1.6 chs NULL, 0, EX_WAITOK | EX_MALLOCOK); 1782 1.1 skrll 1783 1.1 skrll /* interrupts guts */ 1784 1.1 skrll s = splhigh(); 1785 1.1 skrll r->icr = 0; 1786 1.5 skrll r->imr = 0; 1787 1.1 skrll (void)r->irr0; 1788 1.1 skrll r->iar0 = ci->ci_hpa | (31 - ca->ca_irq); 1789 1.1 skrll splx(s); 1790 1.1 skrll /* Establish the interrupt register. */ 1791 1.1 skrll hppa_interrupt_register_establish(ci, &sc->sc_ir); 1792 1.1 skrll sc->sc_ir.ir_name = device_xname(self); 1793 1.1 skrll sc->sc_ir.ir_mask = &r->imr; 1794 1.1 skrll sc->sc_ir.ir_req = &r->irr0; 1795 1.1 skrll sc->sc_ir.ir_level = &r->ilr; 1796 1.1 skrll /* Add the I/O interrupt register. */ 1797 1.1 skrll 1798 1.1 skrll sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir, 1799 1.1 skrll &ci->ci_ir, ca->ca_irq); 1800 1.1 skrll 1801 1.1 skrll /* TODO establish the bus error interrupt */ 1802 1.1 skrll 1803 1.1 skrll ver = ca->ca_type.iodc_revision; 1804 1.1 skrll switch ((ca->ca_type.iodc_model << 4) | 1805 1.1 skrll (ca->ca_type.iodc_revision >> 4)) { 1806 1.1 skrll case 0x05d: 1807 1.1 skrll p = "Dino (card)"; /* j2240 */ 1808 1.1 skrll /* FALLTHROUGH */ 1809 1.1 skrll case 0x680: 1810 1.1 skrll if (!p) 1811 1.1 skrll p = "Dino"; 1812 1.1 skrll switch (ver & 0xf) { 1813 1.1 skrll case 0: ver = 0x20; break; 1814 1.1 skrll case 1: ver = 0x21; break; 1815 1.1 skrll case 2: ver = 0x30; break; 1816 1.1 skrll case 3: ver = 0x31; break; 1817 1.1 skrll } 1818 1.1 skrll break; 1819 1.1 skrll 1820 1.1 skrll case 0x682: 1821 1.1 skrll p = "Cujo"; 1822 1.1 skrll switch (ver & 0xf) { 1823 1.1 skrll case 0: ver = 0x10; break; 1824 1.1 skrll case 1: ver = 0x20; break; 1825 1.1 skrll } 1826 1.1 skrll break; 1827 1.1 skrll 1828 1.1 skrll default: 1829 1.1 skrll p = "Mojo"; 1830 1.1 skrll break; 1831 1.1 skrll } 1832 1.1 skrll 1833 1.1 skrll sc->sc_ver = ver; 1834 1.1 skrll aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); 1835 1.1 skrll 1836 1.1 skrll sc->sc_iot = dino_iomemt; 1837 1.1 skrll sc->sc_iot.hbt_cookie = sc; 1838 1.1 skrll sc->sc_iot.hbt_map = dino_iomap; 1839 1.1 skrll sc->sc_iot.hbt_alloc = dino_ioalloc; 1840 1.1 skrll sc->sc_memt = dino_iomemt; 1841 1.1 skrll sc->sc_memt.hbt_cookie = sc; 1842 1.1 skrll sc->sc_memt.hbt_map = dino_memmap; 1843 1.1 skrll sc->sc_memt.hbt_alloc = dino_memalloc; 1844 1.1 skrll sc->sc_pc = dino_pc; 1845 1.1 skrll sc->sc_pc._cookie = sc; 1846 1.1 skrll sc->sc_dmatag = dino_dmat; 1847 1.1 skrll sc->sc_dmatag._cookie = sc; 1848 1.1 skrll 1849 1.1 skrll /* scan for ps2 kbd/ms, serial, and flying toasters */ 1850 1.1 skrll nca = *ca; 1851 1.1 skrll 1852 1.1 skrll nca.ca_hpabase = 0; 1853 1.1 skrll nca.ca_nmodules = MAXMODBUS; 1854 1.1 skrll pdc_scanbus(self, &nca, dino_callback); 1855 1.1 skrll 1856 1.1 skrll memset(&pba, 0, sizeof(pba)); 1857 1.1 skrll pba.pba_iot = &sc->sc_iot; 1858 1.1 skrll pba.pba_memt = &sc->sc_memt; 1859 1.1 skrll pba.pba_dmat = &sc->sc_dmatag; 1860 1.1 skrll pba.pba_pc = &sc->sc_pc; 1861 1.1 skrll pba.pba_bus = 0; 1862 1.1 skrll pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 1863 1.11 thorpej config_found(self, &pba, pcibusprint, 1864 1.12 thorpej CFARGS(.iattr = "pcibus")); 1865 1.1 skrll } 1866 1.1 skrll 1867 1.1 skrll static device_t 1868 1.1 skrll dino_callback(device_t self, struct confargs *ca) 1869 1.1 skrll { 1870 1.11 thorpej return config_found(self, ca, mbprint, 1871 1.12 thorpej CFARGS(.submatch = mbsubmatch, 1872 1.12 thorpej .iattr = "gedoens")); 1873 1.1 skrll } 1874