dino.c revision 1.2.10.3
1 1.2.10.2 tls /* $NetBSD: dino.c,v 1.2.10.3 2017/12/03 11:36:16 jdolecek Exp $ */ 2 1.2.10.2 tls 3 1.2.10.2 tls /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ 4 1.2.10.2 tls 5 1.2.10.2 tls /* 6 1.2.10.2 tls * Copyright (c) 2003 Michael Shalayeff 7 1.2.10.2 tls * All rights reserved. 8 1.2.10.2 tls * 9 1.2.10.2 tls * Redistribution and use in source and binary forms, with or without 10 1.2.10.2 tls * modification, are permitted provided that the following conditions 11 1.2.10.2 tls * are met: 12 1.2.10.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.2.10.2 tls * notice, this list of conditions and the following disclaimer. 14 1.2.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.10.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.2.10.2 tls * documentation and/or other materials provided with the distribution. 17 1.2.10.2 tls * 18 1.2.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.2.10.2 tls * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.2.10.2 tls * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.2.10.2 tls * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 1.2.10.2 tls * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 1.2.10.2 tls * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 1.2.10.2 tls * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.2.10.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 1.2.10.2 tls * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 1.2.10.2 tls * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 1.2.10.2 tls * THE POSSIBILITY OF SUCH DAMAGE. 29 1.2.10.2 tls */ 30 1.2.10.2 tls 31 1.2.10.2 tls #include <sys/cdefs.h> 32 1.2.10.2 tls __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.2.10.3 2017/12/03 11:36:16 jdolecek Exp $"); 33 1.2.10.2 tls 34 1.2.10.2 tls /* #include "cardbus.h" */ 35 1.2.10.2 tls 36 1.2.10.2 tls #include <sys/param.h> 37 1.2.10.2 tls #include <sys/systm.h> 38 1.2.10.2 tls #include <sys/device.h> 39 1.2.10.2 tls #include <sys/reboot.h> 40 1.2.10.2 tls #include <sys/malloc.h> 41 1.2.10.2 tls #include <sys/extent.h> 42 1.2.10.2 tls 43 1.2.10.2 tls #include <machine/iomod.h> 44 1.2.10.2 tls #include <machine/autoconf.h> 45 1.2.10.2 tls #include <machine/intr.h> 46 1.2.10.2 tls 47 1.2.10.2 tls #include <hppa/include/vmparam.h> 48 1.2.10.2 tls #include <hppa/dev/cpudevs.h> 49 1.2.10.2 tls 50 1.2.10.2 tls #if NCARDBUS > 0 51 1.2.10.2 tls #include <dev/cardbus/rbus.h> 52 1.2.10.2 tls #endif 53 1.2.10.2 tls 54 1.2.10.2 tls #include <dev/pci/pcireg.h> 55 1.2.10.2 tls #include <dev/pci/pcivar.h> 56 1.2.10.2 tls #include <dev/pci/pcidevs.h> 57 1.2.10.2 tls 58 1.2.10.2 tls #define DINO_MEM_CHUNK 0x800000 59 1.2.10.2 tls 60 1.2.10.2 tls /* from machdep.c */ 61 1.2.10.2 tls extern struct extent *hppa_io_extent; 62 1.2.10.2 tls 63 1.2.10.2 tls struct dino_regs { 64 1.2.10.2 tls /* HPA Supervisory Register Set */ 65 1.2.10.2 tls uint32_t pad0; /* 0x000 */ 66 1.2.10.2 tls uint32_t iar0; /* 0x004 rw intr addr reg 0 */ 67 1.2.10.2 tls uint32_t iodc; /* 0x008 rw iodc data/addr */ 68 1.2.10.2 tls uint32_t irr0; /* 0x00c r intr req reg 0 */ 69 1.2.10.2 tls uint32_t iar1; /* 0x010 rw intr addr reg 1 */ 70 1.2.10.2 tls uint32_t irr1; /* 0x014 r intr req reg 1 */ 71 1.2.10.2 tls uint32_t imr; /* 0x018 rw intr mask reg */ 72 1.2.10.2 tls uint32_t ipr; /* 0x01c rw intr pending reg */ 73 1.2.10.2 tls uint32_t toc_addr; /* 0x020 rw TOC addr reg */ 74 1.2.10.2 tls uint32_t icr; /* 0x024 rw intr control reg */ 75 1.2.10.2 tls uint32_t ilr; /* 0x028 r intr level reg */ 76 1.2.10.2 tls uint32_t pad1; /* 0x02c */ 77 1.2.10.2 tls uint32_t io_command; /* 0x030 w command register */ 78 1.2.10.2 tls uint32_t io_status; /* 0x034 r status register */ 79 1.2.10.2 tls uint32_t io_control; /* 0x038 rw control register */ 80 1.2.10.2 tls uint32_t pad2; /* 0x03c AUX registers follow */ 81 1.2.10.2 tls 82 1.2.10.2 tls /* HPA Auxiliary Register Set */ 83 1.2.10.2 tls uint32_t io_gsc_err_addr;/* 0x040 GSC error address */ 84 1.2.10.2 tls uint32_t io_err_info; /* 0x044 error info register */ 85 1.2.10.2 tls uint32_t io_pci_err_addr;/* 0x048 PCI error address */ 86 1.2.10.2 tls uint32_t pad3[4]; /* 0x04c */ 87 1.2.10.2 tls uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 88 1.2.10.2 tls uint32_t io_addr_en; /* 0x060 address enable reg */ 89 1.2.10.2 tls uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 90 1.2.10.2 tls uint32_t pci_conf_data; /* 0x068 PCI conf data reg */ 91 1.2.10.2 tls uint32_t pci_io_data; /* 0x06c PCI io data reg */ 92 1.2.10.2 tls uint32_t pci_mem_data; /* 0x070 PCI memory data reg */ 93 1.2.10.2 tls uint32_t pad4[0x740/4]; /* 0x074 */ 94 1.2.10.2 tls 95 1.2.10.2 tls /* HPA Bus (GSC) Specific-Dependent Register Set */ 96 1.2.10.2 tls uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 97 1.2.10.2 tls uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 98 1.2.10.2 tls 99 1.2.10.2 tls /* HPA HVERSION (Dino)-Dependent Register Set */ 100 1.2.10.2 tls uint32_t gmask; /* 0x800 GSC arbitration mask */ 101 1.2.10.2 tls uint32_t pamr; /* 0x804 PCI arbitration mask */ 102 1.2.10.2 tls uint32_t papr; /* 0x808 PCI arbitration priority */ 103 1.2.10.2 tls uint32_t damode; /* 0x80c PCI arbitration mode */ 104 1.2.10.2 tls uint32_t pcicmd; /* 0x810 PCI command register */ 105 1.2.10.2 tls uint32_t pcists; /* 0x814 PCI status register */ 106 1.2.10.2 tls uint32_t pad6; /* 0x818 */ 107 1.2.10.2 tls uint32_t mltim; /* 0x81c PCI master latency timer */ 108 1.2.10.2 tls uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 109 1.2.10.2 tls uint32_t pciror; /* 0x824 PCI read optimization reg */ 110 1.2.10.2 tls uint32_t pciwor; /* 0x828 PCI write optimization reg */ 111 1.2.10.2 tls uint32_t pad7; /* 0x82c */ 112 1.2.10.2 tls uint32_t tltim; /* 0x830 PCI target latency reg */ 113 1.2.10.2 tls }; 114 1.2.10.2 tls 115 1.2.10.2 tls struct dino_softc { 116 1.2.10.2 tls device_t sc_dv; 117 1.2.10.2 tls 118 1.2.10.2 tls int sc_ver; 119 1.2.10.2 tls void *sc_ih; 120 1.2.10.2 tls struct hppa_interrupt_register sc_ir; 121 1.2.10.2 tls bus_space_tag_t sc_bt; 122 1.2.10.2 tls bus_space_handle_t sc_bh; 123 1.2.10.2 tls bus_dma_tag_t sc_dmat; 124 1.2.10.2 tls volatile struct dino_regs *sc_regs; 125 1.2.10.2 tls 126 1.2.10.2 tls struct hppa_pci_chipset_tag sc_pc; 127 1.2.10.2 tls struct hppa_bus_space_tag sc_iot; 128 1.2.10.2 tls char sc_ioexname[20]; 129 1.2.10.2 tls struct extent *sc_ioex; 130 1.2.10.2 tls struct hppa_bus_space_tag sc_memt; 131 1.2.10.2 tls int sc_memrefcount[30]; 132 1.2.10.2 tls struct hppa_bus_dma_tag sc_dmatag; 133 1.2.10.2 tls }; 134 1.2.10.2 tls 135 1.2.10.2 tls int dinomatch(device_t, struct cfdata *, void *); 136 1.2.10.2 tls void dinoattach(device_t, device_t, void *); 137 1.2.10.2 tls static device_t dino_callback(device_t, struct confargs *); 138 1.2.10.2 tls 139 1.2.10.2 tls CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, 140 1.2.10.2 tls NULL); 141 1.2.10.2 tls 142 1.2.10.2 tls void dino_attach_hook(device_t, device_t, 143 1.2.10.2 tls struct pcibus_attach_args *); 144 1.2.10.2 tls void dino_enable_bus(struct dino_softc *, int); 145 1.2.10.2 tls int dino_maxdevs(void *, int); 146 1.2.10.2 tls pcitag_t dino_make_tag(void *, int, int, int); 147 1.2.10.2 tls void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 148 1.2.10.2 tls pcireg_t dino_conf_read(void *, pcitag_t, int); 149 1.2.10.2 tls void dino_conf_write(void *, pcitag_t, int, pcireg_t); 150 1.2.10.2 tls 151 1.2.10.2 tls int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 152 1.2.10.2 tls const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t); 153 1.2.10.2 tls void *dino_intr_establish(void *, pci_intr_handle_t, int, 154 1.2.10.2 tls int (*)(void *), void *); 155 1.2.10.2 tls void dino_intr_disestablish(void *, void *); 156 1.2.10.2 tls 157 1.2.10.2 tls void *dino_alloc_parent(device_t, struct pci_attach_args *, int); 158 1.2.10.2 tls 159 1.2.10.2 tls int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 160 1.2.10.2 tls int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 161 1.2.10.2 tls int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 162 1.2.10.2 tls bus_space_handle_t *); 163 1.2.10.2 tls int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 164 1.2.10.2 tls bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 165 1.2.10.2 tls int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 166 1.2.10.2 tls bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 167 1.2.10.2 tls void dino_unmap(void *, bus_space_handle_t, bus_size_t); 168 1.2.10.2 tls void dino_free(void *, bus_space_handle_t, bus_size_t); 169 1.2.10.2 tls void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 170 1.2.10.2 tls void *dino_vaddr(void *, bus_space_handle_t); 171 1.2.10.2 tls paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int); 172 1.2.10.2 tls 173 1.2.10.2 tls uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 174 1.2.10.2 tls uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 175 1.2.10.2 tls uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 176 1.2.10.2 tls uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 177 1.2.10.2 tls void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t); 178 1.2.10.2 tls void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 179 1.2.10.2 tls void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 180 1.2.10.2 tls void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t); 181 1.2.10.2 tls void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 182 1.2.10.2 tls void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 183 1.2.10.2 tls void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 184 1.2.10.2 tls void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 185 1.2.10.2 tls void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 186 1.2.10.2 tls bus_size_t); 187 1.2.10.2 tls void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 188 1.2.10.2 tls bus_size_t); 189 1.2.10.2 tls void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 190 1.2.10.2 tls bus_size_t); 191 1.2.10.2 tls void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 192 1.2.10.2 tls bus_size_t); 193 1.2.10.2 tls void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 194 1.2.10.2 tls void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 195 1.2.10.2 tls void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 196 1.2.10.2 tls void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 197 1.2.10.2 tls void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 198 1.2.10.2 tls bus_size_t); 199 1.2.10.2 tls void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 200 1.2.10.2 tls bus_size_t); 201 1.2.10.2 tls void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 202 1.2.10.2 tls bus_size_t); 203 1.2.10.2 tls void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 204 1.2.10.2 tls bus_size_t); 205 1.2.10.2 tls void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 206 1.2.10.2 tls bus_size_t); 207 1.2.10.2 tls void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 208 1.2.10.2 tls bus_size_t); 209 1.2.10.2 tls void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 210 1.2.10.2 tls void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 211 1.2.10.2 tls void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 212 1.2.10.2 tls void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 213 1.2.10.2 tls void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 214 1.2.10.2 tls bus_size_t); 215 1.2.10.2 tls void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 216 1.2.10.2 tls bus_size_t); 217 1.2.10.2 tls void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 218 1.2.10.2 tls bus_size_t); 219 1.2.10.2 tls void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 220 1.2.10.2 tls bus_size_t); 221 1.2.10.2 tls void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 222 1.2.10.2 tls bus_size_t); 223 1.2.10.2 tls void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 224 1.2.10.2 tls bus_size_t); 225 1.2.10.2 tls void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 226 1.2.10.2 tls bus_size_t); 227 1.2.10.2 tls void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 228 1.2.10.2 tls bus_size_t); 229 1.2.10.2 tls void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 230 1.2.10.2 tls bus_size_t); 231 1.2.10.2 tls void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 232 1.2.10.2 tls bus_size_t); 233 1.2.10.2 tls void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 234 1.2.10.2 tls void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 235 1.2.10.2 tls void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 236 1.2.10.2 tls void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 237 1.2.10.2 tls void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 238 1.2.10.2 tls bus_size_t, bus_size_t); 239 1.2.10.2 tls void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 240 1.2.10.2 tls bus_size_t, bus_size_t); 241 1.2.10.2 tls void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 242 1.2.10.2 tls bus_size_t, bus_size_t); 243 1.2.10.2 tls void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 244 1.2.10.2 tls bus_size_t, bus_size_t); 245 1.2.10.2 tls int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 246 1.2.10.2 tls bus_dmamap_t *); 247 1.2.10.2 tls void dino_dmamap_destroy(void *, bus_dmamap_t); 248 1.2.10.2 tls int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, 249 1.2.10.2 tls int); 250 1.2.10.2 tls int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 251 1.2.10.2 tls int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 252 1.2.10.2 tls int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 253 1.2.10.2 tls bus_size_t, int); 254 1.2.10.2 tls void dino_dmamap_unload(void *, bus_dmamap_t); 255 1.2.10.2 tls void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 256 1.2.10.2 tls int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 257 1.2.10.2 tls bus_dma_segment_t *, int, int *, int); 258 1.2.10.2 tls void dino_dmamem_free(void *, bus_dma_segment_t *, int); 259 1.2.10.2 tls int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int); 260 1.2.10.2 tls void dino_dmamem_unmap(void *, void *, size_t); 261 1.2.10.2 tls paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 262 1.2.10.2 tls 263 1.2.10.2 tls 264 1.2.10.2 tls void 265 1.2.10.2 tls dino_attach_hook(device_t parent, device_t self, 266 1.2.10.2 tls struct pcibus_attach_args *pba) 267 1.2.10.2 tls { 268 1.2.10.2 tls struct dino_softc *sc = pba->pba_pc->_cookie; 269 1.2.10.2 tls 270 1.2.10.2 tls /* 271 1.2.10.2 tls * The firmware enables only devices that are needed for booting. 272 1.2.10.2 tls * So other devices will fail to map PCI MEM / IO when they attach. 273 1.2.10.2 tls * Therefore we recursively walk all buses to simply enable everything. 274 1.2.10.2 tls */ 275 1.2.10.2 tls dino_enable_bus(sc, 0); 276 1.2.10.2 tls } 277 1.2.10.2 tls 278 1.2.10.2 tls void 279 1.2.10.2 tls dino_enable_bus(struct dino_softc *sc, int bus) 280 1.2.10.2 tls { 281 1.2.10.2 tls int func; 282 1.2.10.2 tls int dev; 283 1.2.10.2 tls pcitag_t tag; 284 1.2.10.2 tls pcireg_t data; 285 1.2.10.2 tls pcireg_t class; 286 1.2.10.2 tls 287 1.2.10.2 tls for (dev = 0; dev < 32; dev++) { 288 1.2.10.2 tls tag = dino_make_tag(sc, bus, dev, 0); 289 1.2.10.2 tls if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) { 290 1.2.10.2 tls for (func = 0; func < 8; func++) { 291 1.2.10.2 tls tag = dino_make_tag(sc, bus, dev, func); 292 1.2.10.2 tls if (dino_conf_read(sc, tag, 0) != 0xffffffff) { 293 1.2.10.2 tls data = dino_conf_read(sc, tag, 294 1.2.10.2 tls PCI_COMMAND_STATUS_REG); 295 1.2.10.2 tls dino_conf_write(sc, tag, 296 1.2.10.2 tls PCI_COMMAND_STATUS_REG, 297 1.2.10.2 tls PCI_COMMAND_IO_ENABLE | 298 1.2.10.2 tls PCI_COMMAND_MEM_ENABLE | 299 1.2.10.2 tls PCI_COMMAND_MASTER_ENABLE | data); 300 1.2.10.2 tls } 301 1.2.10.2 tls } 302 1.2.10.2 tls class = dino_conf_read(sc, tag, PCI_CLASS_REG); 303 1.2.10.2 tls if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 304 1.2.10.2 tls PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI) 305 1.2.10.2 tls dino_enable_bus(sc, bus + 1); 306 1.2.10.2 tls } 307 1.2.10.2 tls } 308 1.2.10.2 tls } 309 1.2.10.2 tls 310 1.2.10.2 tls int 311 1.2.10.2 tls dino_maxdevs(void *v, int bus) 312 1.2.10.2 tls { 313 1.2.10.2 tls return 32; 314 1.2.10.2 tls } 315 1.2.10.2 tls 316 1.2.10.2 tls pcitag_t 317 1.2.10.2 tls dino_make_tag(void *v, int bus, int dev, int func) 318 1.2.10.2 tls { 319 1.2.10.2 tls if (bus > 255 || dev > 31 || func > 7) 320 1.2.10.2 tls panic("dino_make_tag: bad request"); 321 1.2.10.2 tls 322 1.2.10.2 tls return (bus << 16) | (dev << 11) | (func << 8); 323 1.2.10.2 tls } 324 1.2.10.2 tls 325 1.2.10.2 tls void 326 1.2.10.2 tls dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 327 1.2.10.2 tls { 328 1.2.10.2 tls *bus = (tag >> 16) & 0xff; 329 1.2.10.2 tls *dev = (tag >> 11) & 0x1f; 330 1.2.10.2 tls *func= (tag >> 8) & 0x07; 331 1.2.10.2 tls } 332 1.2.10.2 tls 333 1.2.10.2 tls pcireg_t 334 1.2.10.2 tls dino_conf_read(void *v, pcitag_t tag, int reg) 335 1.2.10.2 tls { 336 1.2.10.2 tls struct dino_softc *sc = v; 337 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 338 1.2.10.2 tls pcireg_t data; 339 1.2.10.2 tls uint32_t pamr; 340 1.2.10.2 tls 341 1.2.10.3 jdolecek if ((unsigned int)reg >= PCI_CONF_SIZE) 342 1.2.10.3 jdolecek return (pcireg_t) -1; 343 1.2.10.3 jdolecek 344 1.2.10.2 tls /* fix arbitration errata by disabling all pci devs on config read */ 345 1.2.10.2 tls pamr = r->pamr; 346 1.2.10.2 tls r->pamr = 0; 347 1.2.10.2 tls 348 1.2.10.2 tls r->pci_addr = tag | reg; 349 1.2.10.2 tls data = r->pci_conf_data; 350 1.2.10.2 tls 351 1.2.10.2 tls /* restore arbitration */ 352 1.2.10.2 tls r->pamr = pamr; 353 1.2.10.2 tls 354 1.2.10.2 tls return le32toh(data); 355 1.2.10.2 tls } 356 1.2.10.2 tls 357 1.2.10.2 tls void 358 1.2.10.2 tls dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 359 1.2.10.2 tls { 360 1.2.10.2 tls struct dino_softc *sc = v; 361 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 362 1.2.10.2 tls uint32_t pamr; 363 1.2.10.2 tls 364 1.2.10.3 jdolecek if ((unsigned int)reg >= PCI_CONF_SIZE) 365 1.2.10.3 jdolecek return; 366 1.2.10.3 jdolecek 367 1.2.10.2 tls /* fix arbitration errata by disabling all pci devs on config read */ 368 1.2.10.2 tls pamr = r->pamr; 369 1.2.10.2 tls r->pamr = 0; 370 1.2.10.2 tls 371 1.2.10.2 tls r->pci_addr = tag | reg; 372 1.2.10.2 tls r->pci_conf_data = htole32(data); 373 1.2.10.2 tls 374 1.2.10.2 tls /* fix coalescing config and io writes by interleaving w/ a read */ 375 1.2.10.2 tls r->pci_addr = tag | PCI_ID_REG; 376 1.2.10.2 tls (void)r->pci_conf_data; 377 1.2.10.2 tls 378 1.2.10.2 tls /* restore arbitration */ 379 1.2.10.2 tls r->pamr = pamr; 380 1.2.10.2 tls } 381 1.2.10.2 tls 382 1.2.10.2 tls int 383 1.2.10.2 tls dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 384 1.2.10.2 tls { 385 1.2.10.2 tls int line = pa->pa_intrline; 386 1.2.10.2 tls 387 1.2.10.2 tls if (line == 0xff) 388 1.2.10.2 tls return 1; 389 1.2.10.2 tls 390 1.2.10.2 tls *ihp = line; 391 1.2.10.2 tls 392 1.2.10.2 tls return 0; 393 1.2.10.2 tls } 394 1.2.10.2 tls 395 1.2.10.2 tls const char * 396 1.2.10.2 tls dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 397 1.2.10.2 tls { 398 1.2.10.2 tls snprintf(buf, len, "irq %ld", ih); 399 1.2.10.2 tls return buf; 400 1.2.10.2 tls } 401 1.2.10.2 tls 402 1.2.10.2 tls extern int cold; 403 1.2.10.2 tls 404 1.2.10.2 tls 405 1.2.10.2 tls void * 406 1.2.10.2 tls dino_intr_establish(void *v, pci_intr_handle_t ih, 407 1.2.10.2 tls int pri, int (*handler)(void *), void *arg) 408 1.2.10.2 tls { 409 1.2.10.2 tls struct dino_softc *sc = v; 410 1.2.10.2 tls 411 1.2.10.2 tls return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih); 412 1.2.10.2 tls } 413 1.2.10.2 tls 414 1.2.10.2 tls void 415 1.2.10.2 tls dino_intr_disestablish(void *v, void *cookie) 416 1.2.10.2 tls { 417 1.2.10.2 tls /* XXX Implement me */ 418 1.2.10.2 tls } 419 1.2.10.2 tls 420 1.2.10.2 tls 421 1.2.10.2 tls #if NCARDBUS > 0 422 1.2.10.2 tls void * 423 1.2.10.2 tls dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io) 424 1.2.10.2 tls { 425 1.2.10.2 tls struct dino_softc *sc = pa->pa_pc->_cookie; 426 1.2.10.2 tls struct extent *ex; 427 1.2.10.2 tls bus_space_tag_t tag; 428 1.2.10.2 tls bus_addr_t start; 429 1.2.10.2 tls bus_size_t size; 430 1.2.10.2 tls 431 1.2.10.2 tls if (io) { 432 1.2.10.2 tls ex = sc->sc_ioex; 433 1.2.10.2 tls tag = pa->pa_iot; 434 1.2.10.2 tls start = 0xa000; 435 1.2.10.2 tls size = 0x1000; 436 1.2.10.2 tls } else { 437 1.2.10.2 tls ex = hppa_io_extent; 438 1.2.10.2 tls tag = pa->pa_memt; 439 1.2.10.2 tls start = ex->ex_start; /* XXX or 0xf0800000? */ 440 1.2.10.2 tls size = DINO_MEM_CHUNK; 441 1.2.10.2 tls } 442 1.2.10.2 tls 443 1.2.10.2 tls if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 444 1.2.10.2 tls EX_NOBOUNDARY, EX_NOWAIT, &start)) 445 1.2.10.2 tls return NULL; 446 1.2.10.2 tls extent_free(ex, start, size, EX_NOWAIT); 447 1.2.10.2 tls return rbus_new_root_share(tag, ex, start, size, start); 448 1.2.10.2 tls } 449 1.2.10.2 tls #endif 450 1.2.10.2 tls 451 1.2.10.2 tls int 452 1.2.10.2 tls dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 453 1.2.10.2 tls int flags, bus_space_handle_t *bshp) 454 1.2.10.2 tls { 455 1.2.10.2 tls struct dino_softc *sc = v; 456 1.2.10.2 tls int error; 457 1.2.10.2 tls 458 1.2.10.2 tls if (!(flags & BUS_SPACE_MAP_NOEXTENT) && 459 1.2.10.2 tls (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 460 1.2.10.2 tls return error; 461 1.2.10.2 tls 462 1.2.10.2 tls if (bshp) 463 1.2.10.2 tls *bshp = bpa; 464 1.2.10.2 tls 465 1.2.10.2 tls return 0; 466 1.2.10.2 tls } 467 1.2.10.2 tls 468 1.2.10.2 tls int 469 1.2.10.2 tls dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 470 1.2.10.2 tls int flags, bus_space_handle_t *bshp) 471 1.2.10.2 tls { 472 1.2.10.2 tls struct dino_softc *sc = v; 473 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 474 1.2.10.2 tls uint32_t reg; 475 1.2.10.2 tls int error; 476 1.2.10.2 tls 477 1.2.10.2 tls reg = r->io_addr_en; 478 1.2.10.2 tls reg |= 1 << ((bpa >> 23) & 0x1f); 479 1.2.10.2 tls #ifdef DEBUG 480 1.2.10.2 tls if (reg & 0x80000001) 481 1.2.10.2 tls panic("mapping outside the mem extent range"); 482 1.2.10.2 tls #endif 483 1.2.10.2 tls if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) 484 1.2.10.2 tls return error; 485 1.2.10.2 tls ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; 486 1.2.10.2 tls /* map into the upper bus space, if not yet mapped this 8M */ 487 1.2.10.2 tls if (reg != r->io_addr_en) 488 1.2.10.2 tls r->io_addr_en = reg; 489 1.2.10.2 tls return 0; 490 1.2.10.2 tls } 491 1.2.10.2 tls 492 1.2.10.2 tls int 493 1.2.10.2 tls dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 494 1.2.10.2 tls bus_size_t size, bus_space_handle_t *nbshp) 495 1.2.10.2 tls { 496 1.2.10.2 tls *nbshp = bsh + offset; 497 1.2.10.2 tls return 0; 498 1.2.10.2 tls } 499 1.2.10.2 tls 500 1.2.10.2 tls int 501 1.2.10.2 tls dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 502 1.2.10.2 tls bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 503 1.2.10.2 tls bus_space_handle_t *bshp) 504 1.2.10.2 tls { 505 1.2.10.2 tls struct dino_softc *sc = v; 506 1.2.10.2 tls struct extent *ex = sc->sc_ioex; 507 1.2.10.2 tls bus_addr_t bpa; 508 1.2.10.2 tls int error; 509 1.2.10.2 tls 510 1.2.10.2 tls if (rstart < ex->ex_start || rend > ex->ex_end) 511 1.2.10.2 tls panic("dino_ioalloc: bad region start/end"); 512 1.2.10.2 tls 513 1.2.10.2 tls if ((error = extent_alloc_subregion(ex, rstart, rend, size, 514 1.2.10.2 tls align, boundary, EX_NOWAIT, &bpa))) 515 1.2.10.2 tls return error; 516 1.2.10.2 tls 517 1.2.10.2 tls if (addrp) 518 1.2.10.2 tls *addrp = bpa; 519 1.2.10.2 tls if (bshp) 520 1.2.10.2 tls *bshp = bpa; 521 1.2.10.2 tls 522 1.2.10.2 tls return 0; 523 1.2.10.2 tls } 524 1.2.10.2 tls 525 1.2.10.2 tls int 526 1.2.10.2 tls dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 527 1.2.10.2 tls bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 528 1.2.10.2 tls bus_space_handle_t *bshp) 529 1.2.10.2 tls { 530 1.2.10.2 tls struct dino_softc *sc = v; 531 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 532 1.2.10.2 tls uint32_t reg; 533 1.2.10.2 tls int i, error; 534 1.2.10.2 tls 535 1.2.10.2 tls /* 536 1.2.10.2 tls * Allow allocation only when PCI MEM is already mapped. 537 1.2.10.2 tls * Needed to avoid allocation of I/O space used by devices that 538 1.2.10.2 tls * have no driver in the current kernel. 539 1.2.10.2 tls * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. 540 1.2.10.2 tls */ 541 1.2.10.2 tls reg = r->io_addr_en; 542 1.2.10.2 tls if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) 543 1.2.10.2 tls return -1; 544 1.2.10.2 tls /* Find used PCI MEM and narrow allocateble region down to it. */ 545 1.2.10.2 tls for (i = 1; i < 31; i++) 546 1.2.10.2 tls if ((reg & 1 << i) != 0) { 547 1.2.10.2 tls rstart = HPPA_IOSPACE | i << 23; 548 1.2.10.2 tls rend = (HPPA_IOSPACE | (i + 1) << 23) - 1; 549 1.2.10.2 tls break; 550 1.2.10.2 tls } 551 1.2.10.2 tls if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, 552 1.2.10.2 tls boundary, flags, addrp, bshp))) 553 1.2.10.2 tls return error; 554 1.2.10.2 tls ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; 555 1.2.10.2 tls return 0; 556 1.2.10.2 tls } 557 1.2.10.2 tls 558 1.2.10.2 tls void 559 1.2.10.2 tls dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 560 1.2.10.2 tls { 561 1.2.10.2 tls struct dino_softc *sc = v; 562 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 563 1.2.10.2 tls 564 1.2.10.2 tls if (bsh & HPPA_IOSPACE) { 565 1.2.10.2 tls bus_space_unmap(sc->sc_bt, bsh, size); 566 1.2.10.2 tls if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) 567 1.2.10.2 tls /* Unmap the upper PCI MEM space. */ 568 1.2.10.2 tls r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); 569 1.2.10.2 tls } else { 570 1.2.10.2 tls /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ 571 1.2.10.2 tls if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) 572 1.2.10.2 tls printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 573 1.2.10.2 tls "dino_unmap: can't free region\n", bsh, size); 574 1.2.10.2 tls } 575 1.2.10.2 tls } 576 1.2.10.2 tls 577 1.2.10.2 tls void 578 1.2.10.2 tls dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 579 1.2.10.2 tls { 580 1.2.10.2 tls /* should be enough */ 581 1.2.10.2 tls dino_unmap(v, bh, size); 582 1.2.10.2 tls } 583 1.2.10.2 tls 584 1.2.10.2 tls void 585 1.2.10.2 tls dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 586 1.2.10.2 tls { 587 1.2.10.2 tls sync_caches(); 588 1.2.10.2 tls } 589 1.2.10.2 tls 590 1.2.10.2 tls void* 591 1.2.10.2 tls dino_vaddr(void *v, bus_space_handle_t h) 592 1.2.10.2 tls { 593 1.2.10.2 tls struct dino_softc *sc = v; 594 1.2.10.2 tls 595 1.2.10.2 tls return bus_space_vaddr(sc->sc_bt, h); 596 1.2.10.2 tls } 597 1.2.10.2 tls 598 1.2.10.2 tls paddr_t 599 1.2.10.2 tls dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 600 1.2.10.2 tls { 601 1.2.10.2 tls return -1; 602 1.2.10.2 tls } 603 1.2.10.2 tls 604 1.2.10.2 tls uint8_t 605 1.2.10.2 tls dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 606 1.2.10.2 tls { 607 1.2.10.2 tls h += o; 608 1.2.10.2 tls if (h & HPPA_IOSPACE) 609 1.2.10.2 tls return *(volatile uint8_t *)h; 610 1.2.10.2 tls else { 611 1.2.10.2 tls struct dino_softc *sc = v; 612 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 613 1.2.10.2 tls 614 1.2.10.2 tls r->pci_addr = h; 615 1.2.10.2 tls return *((volatile uint8_t *)&r->pci_io_data + (h & 3)); 616 1.2.10.2 tls } 617 1.2.10.2 tls } 618 1.2.10.2 tls 619 1.2.10.2 tls uint16_t 620 1.2.10.2 tls dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 621 1.2.10.2 tls { 622 1.2.10.2 tls volatile uint16_t *p; 623 1.2.10.2 tls 624 1.2.10.2 tls h += o; 625 1.2.10.2 tls if (h & HPPA_IOSPACE) 626 1.2.10.2 tls p = (volatile uint16_t *)h; 627 1.2.10.2 tls else { 628 1.2.10.2 tls struct dino_softc *sc = v; 629 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 630 1.2.10.2 tls 631 1.2.10.2 tls r->pci_addr = h; 632 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 633 1.2.10.2 tls if (h & 2) 634 1.2.10.2 tls p++; 635 1.2.10.2 tls } 636 1.2.10.2 tls return le16toh(*p); 637 1.2.10.2 tls } 638 1.2.10.2 tls 639 1.2.10.2 tls uint32_t 640 1.2.10.2 tls dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 641 1.2.10.2 tls { 642 1.2.10.2 tls uint32_t data; 643 1.2.10.2 tls 644 1.2.10.2 tls h += o; 645 1.2.10.2 tls if (h & HPPA_IOSPACE) 646 1.2.10.2 tls data = *(volatile uint32_t *)h; 647 1.2.10.2 tls else { 648 1.2.10.2 tls struct dino_softc *sc = v; 649 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 650 1.2.10.2 tls 651 1.2.10.2 tls r->pci_addr = h; 652 1.2.10.2 tls data = r->pci_io_data; 653 1.2.10.2 tls } 654 1.2.10.2 tls 655 1.2.10.2 tls return le32toh(data); 656 1.2.10.2 tls } 657 1.2.10.2 tls 658 1.2.10.2 tls uint64_t 659 1.2.10.2 tls dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 660 1.2.10.2 tls { 661 1.2.10.2 tls uint64_t data; 662 1.2.10.2 tls 663 1.2.10.2 tls h += o; 664 1.2.10.2 tls if (h & HPPA_IOSPACE) 665 1.2.10.2 tls data = *(volatile uint64_t *)h; 666 1.2.10.2 tls else 667 1.2.10.2 tls panic("dino_r8: not implemented"); 668 1.2.10.2 tls 669 1.2.10.2 tls return le64toh(data); 670 1.2.10.2 tls } 671 1.2.10.2 tls 672 1.2.10.2 tls void 673 1.2.10.2 tls dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv) 674 1.2.10.2 tls { 675 1.2.10.2 tls h += o; 676 1.2.10.2 tls if (h & HPPA_IOSPACE) 677 1.2.10.2 tls *(volatile uint8_t *)h = vv; 678 1.2.10.2 tls else { 679 1.2.10.2 tls struct dino_softc *sc = v; 680 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 681 1.2.10.2 tls 682 1.2.10.2 tls r->pci_addr = h; 683 1.2.10.2 tls *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv; 684 1.2.10.2 tls } 685 1.2.10.2 tls } 686 1.2.10.2 tls 687 1.2.10.2 tls void 688 1.2.10.2 tls dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 689 1.2.10.2 tls { 690 1.2.10.2 tls volatile uint16_t *p; 691 1.2.10.2 tls 692 1.2.10.2 tls h += o; 693 1.2.10.2 tls if (h & HPPA_IOSPACE) 694 1.2.10.2 tls p = (volatile uint16_t *)h; 695 1.2.10.2 tls else { 696 1.2.10.2 tls struct dino_softc *sc = v; 697 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 698 1.2.10.2 tls 699 1.2.10.2 tls r->pci_addr = h; 700 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 701 1.2.10.2 tls if (h & 2) 702 1.2.10.2 tls p++; 703 1.2.10.2 tls } 704 1.2.10.2 tls 705 1.2.10.2 tls *p = htole16(vv); 706 1.2.10.2 tls } 707 1.2.10.2 tls 708 1.2.10.2 tls void 709 1.2.10.2 tls dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 710 1.2.10.2 tls { 711 1.2.10.2 tls h += o; 712 1.2.10.2 tls vv = htole32(vv); 713 1.2.10.2 tls if (h & HPPA_IOSPACE) 714 1.2.10.2 tls *(volatile uint32_t *)h = vv; 715 1.2.10.2 tls else { 716 1.2.10.2 tls struct dino_softc *sc = v; 717 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 718 1.2.10.2 tls 719 1.2.10.2 tls r->pci_addr = h; 720 1.2.10.2 tls r->pci_io_data = vv; 721 1.2.10.2 tls } 722 1.2.10.2 tls } 723 1.2.10.2 tls 724 1.2.10.2 tls void 725 1.2.10.2 tls dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 726 1.2.10.2 tls { 727 1.2.10.2 tls h += o; 728 1.2.10.2 tls if (h & HPPA_IOSPACE) 729 1.2.10.2 tls *(volatile uint64_t *)h = htole64(vv); 730 1.2.10.2 tls else 731 1.2.10.2 tls panic("dino_w8: not implemented"); 732 1.2.10.2 tls } 733 1.2.10.2 tls 734 1.2.10.2 tls 735 1.2.10.2 tls void 736 1.2.10.2 tls dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 737 1.2.10.2 tls { 738 1.2.10.2 tls volatile uint8_t *p; 739 1.2.10.2 tls 740 1.2.10.2 tls h += o; 741 1.2.10.2 tls if (h & HPPA_IOSPACE) 742 1.2.10.2 tls p = (volatile uint8_t *)h; 743 1.2.10.2 tls else { 744 1.2.10.2 tls struct dino_softc *sc = v; 745 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 746 1.2.10.2 tls 747 1.2.10.2 tls r->pci_addr = h; 748 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 749 1.2.10.2 tls } 750 1.2.10.2 tls 751 1.2.10.2 tls while (c--) 752 1.2.10.2 tls *a++ = *p; 753 1.2.10.2 tls } 754 1.2.10.2 tls 755 1.2.10.2 tls void 756 1.2.10.2 tls dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 757 1.2.10.2 tls { 758 1.2.10.2 tls volatile uint16_t *p; 759 1.2.10.2 tls 760 1.2.10.2 tls h += o; 761 1.2.10.2 tls if (h & HPPA_IOSPACE) 762 1.2.10.2 tls p = (volatile uint16_t *)h; 763 1.2.10.2 tls else { 764 1.2.10.2 tls struct dino_softc *sc = v; 765 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 766 1.2.10.2 tls 767 1.2.10.2 tls r->pci_addr = h; 768 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 769 1.2.10.2 tls if (h & 2) 770 1.2.10.2 tls p++; 771 1.2.10.2 tls } 772 1.2.10.2 tls 773 1.2.10.2 tls while (c--) 774 1.2.10.2 tls *a++ = le16toh(*p); 775 1.2.10.2 tls } 776 1.2.10.2 tls 777 1.2.10.2 tls void 778 1.2.10.2 tls dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 779 1.2.10.2 tls { 780 1.2.10.2 tls volatile uint32_t *p; 781 1.2.10.2 tls 782 1.2.10.2 tls h += o; 783 1.2.10.2 tls if (h & HPPA_IOSPACE) 784 1.2.10.2 tls p = (volatile uint32_t *)h; 785 1.2.10.2 tls else { 786 1.2.10.2 tls struct dino_softc *sc = v; 787 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 788 1.2.10.2 tls 789 1.2.10.2 tls r->pci_addr = h; 790 1.2.10.2 tls p = (volatile uint32_t *)&r->pci_io_data; 791 1.2.10.2 tls } 792 1.2.10.2 tls 793 1.2.10.2 tls while (c--) 794 1.2.10.2 tls *a++ = le32toh(*p); 795 1.2.10.2 tls } 796 1.2.10.2 tls 797 1.2.10.2 tls void 798 1.2.10.2 tls dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 799 1.2.10.2 tls { 800 1.2.10.2 tls panic("dino_rm_8: not implemented"); 801 1.2.10.2 tls } 802 1.2.10.2 tls 803 1.2.10.2 tls void 804 1.2.10.2 tls dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 805 1.2.10.2 tls { 806 1.2.10.2 tls volatile uint8_t *p; 807 1.2.10.2 tls 808 1.2.10.2 tls h += o; 809 1.2.10.2 tls if (h & HPPA_IOSPACE) 810 1.2.10.2 tls p = (volatile uint8_t *)h; 811 1.2.10.2 tls else { 812 1.2.10.2 tls struct dino_softc *sc = v; 813 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 814 1.2.10.2 tls 815 1.2.10.2 tls r->pci_addr = h; 816 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 817 1.2.10.2 tls } 818 1.2.10.2 tls 819 1.2.10.2 tls while (c--) 820 1.2.10.2 tls *p = *a++; 821 1.2.10.2 tls } 822 1.2.10.2 tls 823 1.2.10.2 tls void 824 1.2.10.2 tls dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 825 1.2.10.2 tls { 826 1.2.10.2 tls volatile uint16_t *p; 827 1.2.10.2 tls 828 1.2.10.2 tls h += o; 829 1.2.10.2 tls if (h & HPPA_IOSPACE) 830 1.2.10.2 tls p = (volatile uint16_t *)h; 831 1.2.10.2 tls else { 832 1.2.10.2 tls struct dino_softc *sc = v; 833 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 834 1.2.10.2 tls 835 1.2.10.2 tls r->pci_addr = h; 836 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 837 1.2.10.2 tls if (h & 2) 838 1.2.10.2 tls p++; 839 1.2.10.2 tls } 840 1.2.10.2 tls 841 1.2.10.2 tls while (c--) 842 1.2.10.2 tls *p = htole16(*a++); 843 1.2.10.2 tls } 844 1.2.10.2 tls 845 1.2.10.2 tls void 846 1.2.10.2 tls dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 847 1.2.10.2 tls { 848 1.2.10.2 tls volatile uint32_t *p; 849 1.2.10.2 tls 850 1.2.10.2 tls h += o; 851 1.2.10.2 tls if (h & HPPA_IOSPACE) 852 1.2.10.2 tls p = (volatile uint32_t *)h; 853 1.2.10.2 tls else { 854 1.2.10.2 tls struct dino_softc *sc = v; 855 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 856 1.2.10.2 tls 857 1.2.10.2 tls r->pci_addr = h; 858 1.2.10.2 tls p = (volatile uint32_t *)&r->pci_io_data; 859 1.2.10.2 tls } 860 1.2.10.2 tls 861 1.2.10.2 tls while (c--) 862 1.2.10.2 tls *p = htole32(*a++); 863 1.2.10.2 tls } 864 1.2.10.2 tls 865 1.2.10.2 tls void 866 1.2.10.2 tls dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 867 1.2.10.2 tls { 868 1.2.10.2 tls panic("dino_wm_8: not implemented"); 869 1.2.10.2 tls } 870 1.2.10.2 tls 871 1.2.10.2 tls void 872 1.2.10.2 tls dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 873 1.2.10.2 tls { 874 1.2.10.2 tls volatile uint8_t *p; 875 1.2.10.2 tls 876 1.2.10.2 tls h += o; 877 1.2.10.2 tls if (h & HPPA_IOSPACE) 878 1.2.10.2 tls p = (volatile uint8_t *)h; 879 1.2.10.2 tls else { 880 1.2.10.2 tls struct dino_softc *sc = v; 881 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 882 1.2.10.2 tls 883 1.2.10.2 tls r->pci_addr = h; 884 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 885 1.2.10.2 tls } 886 1.2.10.2 tls 887 1.2.10.2 tls while (c--) 888 1.2.10.2 tls *p = vv; 889 1.2.10.2 tls } 890 1.2.10.2 tls 891 1.2.10.2 tls void 892 1.2.10.2 tls dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 893 1.2.10.2 tls { 894 1.2.10.2 tls volatile uint16_t *p; 895 1.2.10.2 tls 896 1.2.10.2 tls h += o; 897 1.2.10.2 tls if (h & HPPA_IOSPACE) 898 1.2.10.2 tls p = (volatile uint16_t *)h; 899 1.2.10.2 tls else { 900 1.2.10.2 tls struct dino_softc *sc = v; 901 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 902 1.2.10.2 tls 903 1.2.10.2 tls r->pci_addr = h; 904 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 905 1.2.10.2 tls if (h & 2) 906 1.2.10.2 tls p++; 907 1.2.10.2 tls } 908 1.2.10.2 tls 909 1.2.10.2 tls while (c--) 910 1.2.10.2 tls *p = htole16(vv); 911 1.2.10.2 tls } 912 1.2.10.2 tls 913 1.2.10.2 tls void 914 1.2.10.2 tls dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 915 1.2.10.2 tls { 916 1.2.10.2 tls volatile uint32_t *p; 917 1.2.10.2 tls 918 1.2.10.2 tls h += o; 919 1.2.10.2 tls if (h & HPPA_IOSPACE) 920 1.2.10.2 tls p = (volatile uint32_t *)h; 921 1.2.10.2 tls else { 922 1.2.10.2 tls struct dino_softc *sc = v; 923 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 924 1.2.10.2 tls 925 1.2.10.2 tls r->pci_addr = h; 926 1.2.10.2 tls p = (volatile uint32_t *)&r->pci_io_data; 927 1.2.10.2 tls } 928 1.2.10.2 tls 929 1.2.10.2 tls while (c--) 930 1.2.10.2 tls *p = htole32(vv); 931 1.2.10.2 tls } 932 1.2.10.2 tls 933 1.2.10.2 tls void 934 1.2.10.2 tls dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 935 1.2.10.2 tls { 936 1.2.10.2 tls panic("dino_sm_8: not implemented"); 937 1.2.10.2 tls } 938 1.2.10.2 tls 939 1.2.10.2 tls void 940 1.2.10.2 tls dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 941 1.2.10.2 tls uint16_t *a, bus_size_t c) 942 1.2.10.2 tls { 943 1.2.10.2 tls volatile uint16_t *p; 944 1.2.10.2 tls 945 1.2.10.2 tls h += o; 946 1.2.10.2 tls if (h & HPPA_IOSPACE) 947 1.2.10.2 tls p = (volatile uint16_t *)h; 948 1.2.10.2 tls else { 949 1.2.10.2 tls struct dino_softc *sc = v; 950 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 951 1.2.10.2 tls 952 1.2.10.2 tls r->pci_addr = h; 953 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 954 1.2.10.2 tls if (h & 2) 955 1.2.10.2 tls p++; 956 1.2.10.2 tls } 957 1.2.10.2 tls 958 1.2.10.2 tls while (c--) 959 1.2.10.2 tls *a++ = *p; 960 1.2.10.2 tls } 961 1.2.10.2 tls 962 1.2.10.2 tls void 963 1.2.10.2 tls dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 964 1.2.10.2 tls uint32_t *a, bus_size_t c) 965 1.2.10.2 tls { 966 1.2.10.2 tls volatile uint32_t *p; 967 1.2.10.2 tls 968 1.2.10.2 tls h += o; 969 1.2.10.2 tls if (h & HPPA_IOSPACE) 970 1.2.10.2 tls p = (volatile uint32_t *)h; 971 1.2.10.2 tls else { 972 1.2.10.2 tls struct dino_softc *sc = v; 973 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 974 1.2.10.2 tls 975 1.2.10.2 tls r->pci_addr = h; 976 1.2.10.2 tls p = (volatile uint32_t *)&r->pci_io_data; 977 1.2.10.2 tls } 978 1.2.10.2 tls 979 1.2.10.2 tls while (c--) 980 1.2.10.2 tls *a++ = *p; 981 1.2.10.2 tls } 982 1.2.10.2 tls 983 1.2.10.2 tls void 984 1.2.10.2 tls dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 985 1.2.10.2 tls uint64_t *a, bus_size_t c) 986 1.2.10.2 tls { 987 1.2.10.2 tls panic("dino_rrm_8: not implemented"); 988 1.2.10.2 tls } 989 1.2.10.2 tls 990 1.2.10.2 tls void 991 1.2.10.2 tls dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 992 1.2.10.2 tls const uint16_t *a, bus_size_t c) 993 1.2.10.2 tls { 994 1.2.10.2 tls volatile uint16_t *p; 995 1.2.10.2 tls 996 1.2.10.2 tls h += o; 997 1.2.10.2 tls if (h & HPPA_IOSPACE) 998 1.2.10.2 tls p = (volatile uint16_t *)h; 999 1.2.10.2 tls else { 1000 1.2.10.2 tls struct dino_softc *sc = v; 1001 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1002 1.2.10.2 tls 1003 1.2.10.2 tls r->pci_addr = h; 1004 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1005 1.2.10.2 tls if (h & 2) 1006 1.2.10.2 tls p++; 1007 1.2.10.2 tls } 1008 1.2.10.2 tls 1009 1.2.10.2 tls while (c--) 1010 1.2.10.2 tls *p = *a++; 1011 1.2.10.2 tls } 1012 1.2.10.2 tls 1013 1.2.10.2 tls void 1014 1.2.10.2 tls dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1015 1.2.10.2 tls const uint32_t *a, bus_size_t c) 1016 1.2.10.2 tls { 1017 1.2.10.2 tls volatile uint32_t *p; 1018 1.2.10.2 tls 1019 1.2.10.2 tls h += o; 1020 1.2.10.2 tls if (h & HPPA_IOSPACE) 1021 1.2.10.2 tls p = (volatile uint32_t *)h; 1022 1.2.10.2 tls else { 1023 1.2.10.2 tls struct dino_softc *sc = v; 1024 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1025 1.2.10.2 tls 1026 1.2.10.2 tls r->pci_addr = h; 1027 1.2.10.2 tls p = (volatile uint32_t *)&r->pci_io_data; 1028 1.2.10.2 tls } 1029 1.2.10.2 tls 1030 1.2.10.2 tls while (c--) 1031 1.2.10.2 tls *p = *a++; 1032 1.2.10.2 tls } 1033 1.2.10.2 tls 1034 1.2.10.2 tls void 1035 1.2.10.2 tls dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1036 1.2.10.2 tls const uint64_t *a, bus_size_t c) 1037 1.2.10.2 tls { 1038 1.2.10.2 tls panic("dino_wrm_8: not implemented"); 1039 1.2.10.2 tls } 1040 1.2.10.2 tls 1041 1.2.10.2 tls void 1042 1.2.10.2 tls dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 1043 1.2.10.2 tls { 1044 1.2.10.2 tls volatile uint8_t *p; 1045 1.2.10.2 tls 1046 1.2.10.2 tls h += o; 1047 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1048 1.2.10.2 tls p = (volatile uint8_t *)h; 1049 1.2.10.2 tls while (c--) 1050 1.2.10.2 tls *a++ = *p++; 1051 1.2.10.2 tls } else { 1052 1.2.10.2 tls struct dino_softc *sc = v; 1053 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1054 1.2.10.2 tls 1055 1.2.10.2 tls for (; c--; h++) { 1056 1.2.10.2 tls r->pci_addr = h; 1057 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1058 1.2.10.2 tls *a++ = *p; 1059 1.2.10.2 tls } 1060 1.2.10.2 tls } 1061 1.2.10.2 tls } 1062 1.2.10.2 tls 1063 1.2.10.2 tls void 1064 1.2.10.2 tls dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 1065 1.2.10.2 tls { 1066 1.2.10.2 tls volatile uint16_t *p, data; 1067 1.2.10.2 tls 1068 1.2.10.2 tls h += o; 1069 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1070 1.2.10.2 tls p = (volatile uint16_t *)h; 1071 1.2.10.2 tls while (c--) { 1072 1.2.10.2 tls data = *p++; 1073 1.2.10.2 tls *a++ = le16toh(data); 1074 1.2.10.2 tls } 1075 1.2.10.2 tls } else { 1076 1.2.10.2 tls struct dino_softc *sc = v; 1077 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1078 1.2.10.2 tls 1079 1.2.10.2 tls for (; c--; h += 2) { 1080 1.2.10.2 tls r->pci_addr = h; 1081 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1082 1.2.10.2 tls if (h & 2) 1083 1.2.10.2 tls p++; 1084 1.2.10.2 tls data = *p; 1085 1.2.10.2 tls *a++ = le16toh(data); 1086 1.2.10.2 tls } 1087 1.2.10.2 tls } 1088 1.2.10.2 tls } 1089 1.2.10.2 tls 1090 1.2.10.2 tls void 1091 1.2.10.2 tls dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 1092 1.2.10.2 tls { 1093 1.2.10.2 tls volatile uint32_t *p, data; 1094 1.2.10.2 tls 1095 1.2.10.2 tls h += o; 1096 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1097 1.2.10.2 tls p = (volatile uint32_t *)h; 1098 1.2.10.2 tls while (c--) { 1099 1.2.10.2 tls data = *p++; 1100 1.2.10.2 tls *a++ = le32toh(data); 1101 1.2.10.2 tls } 1102 1.2.10.2 tls } else { 1103 1.2.10.2 tls struct dino_softc *sc = v; 1104 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1105 1.2.10.2 tls 1106 1.2.10.2 tls for (; c--; h += 4) { 1107 1.2.10.2 tls r->pci_addr = h; 1108 1.2.10.2 tls data = r->pci_io_data; 1109 1.2.10.2 tls *a++ = le32toh(data); 1110 1.2.10.2 tls } 1111 1.2.10.2 tls } 1112 1.2.10.2 tls } 1113 1.2.10.2 tls 1114 1.2.10.2 tls void 1115 1.2.10.2 tls dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 1116 1.2.10.2 tls { 1117 1.2.10.2 tls panic("dino_rr_8: not implemented"); 1118 1.2.10.2 tls } 1119 1.2.10.2 tls 1120 1.2.10.2 tls void 1121 1.2.10.2 tls dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 1122 1.2.10.2 tls { 1123 1.2.10.2 tls volatile uint8_t *p; 1124 1.2.10.2 tls 1125 1.2.10.2 tls h += o; 1126 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1127 1.2.10.2 tls p = (volatile uint8_t *)h; 1128 1.2.10.2 tls while (c--) 1129 1.2.10.2 tls *p++ = *a++; 1130 1.2.10.2 tls } else { 1131 1.2.10.2 tls struct dino_softc *sc = v; 1132 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1133 1.2.10.2 tls 1134 1.2.10.2 tls for (; c--; h++) { 1135 1.2.10.2 tls r->pci_addr = h; 1136 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1137 1.2.10.2 tls *p = *a++; 1138 1.2.10.2 tls } 1139 1.2.10.2 tls } 1140 1.2.10.2 tls } 1141 1.2.10.2 tls 1142 1.2.10.2 tls void 1143 1.2.10.2 tls dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 1144 1.2.10.2 tls { 1145 1.2.10.2 tls volatile uint16_t *p, data; 1146 1.2.10.2 tls 1147 1.2.10.2 tls h += o; 1148 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1149 1.2.10.2 tls p = (volatile uint16_t *)h; 1150 1.2.10.2 tls while (c--) { 1151 1.2.10.2 tls data = *a++; 1152 1.2.10.2 tls *p++ = htole16(data); 1153 1.2.10.2 tls } 1154 1.2.10.2 tls } else { 1155 1.2.10.2 tls struct dino_softc *sc = v; 1156 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1157 1.2.10.2 tls 1158 1.2.10.2 tls for (; c--; h += 2) { 1159 1.2.10.2 tls r->pci_addr = h; 1160 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1161 1.2.10.2 tls if (h & 2) 1162 1.2.10.2 tls p++; 1163 1.2.10.2 tls data = *a++; 1164 1.2.10.2 tls *p = htole16(data); 1165 1.2.10.2 tls } 1166 1.2.10.2 tls } 1167 1.2.10.2 tls } 1168 1.2.10.2 tls 1169 1.2.10.2 tls void 1170 1.2.10.2 tls dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 1171 1.2.10.2 tls { 1172 1.2.10.2 tls volatile uint32_t *p, data; 1173 1.2.10.2 tls 1174 1.2.10.2 tls h += o; 1175 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1176 1.2.10.2 tls p = (volatile uint32_t *)h; 1177 1.2.10.2 tls while (c--) { 1178 1.2.10.2 tls data = *a++; 1179 1.2.10.2 tls *p++ = htole32(data); 1180 1.2.10.2 tls } 1181 1.2.10.2 tls } else { 1182 1.2.10.2 tls struct dino_softc *sc = v; 1183 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1184 1.2.10.2 tls 1185 1.2.10.2 tls for (; c--; h += 4) { 1186 1.2.10.2 tls r->pci_addr = h; 1187 1.2.10.2 tls data = *a++; 1188 1.2.10.2 tls r->pci_io_data = htole32(data); 1189 1.2.10.2 tls } 1190 1.2.10.2 tls } 1191 1.2.10.2 tls } 1192 1.2.10.2 tls 1193 1.2.10.2 tls void 1194 1.2.10.2 tls dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 1195 1.2.10.2 tls { 1196 1.2.10.2 tls panic("dino_wr_8: not implemented"); 1197 1.2.10.2 tls } 1198 1.2.10.2 tls 1199 1.2.10.2 tls void 1200 1.2.10.2 tls dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1201 1.2.10.2 tls uint16_t *a, bus_size_t c) 1202 1.2.10.2 tls { 1203 1.2.10.2 tls volatile uint16_t *p; 1204 1.2.10.2 tls 1205 1.2.10.2 tls h += o; 1206 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1207 1.2.10.2 tls p = (volatile uint16_t *)h; 1208 1.2.10.2 tls while (c--) 1209 1.2.10.2 tls *a++ = *p++; 1210 1.2.10.2 tls } else { 1211 1.2.10.2 tls struct dino_softc *sc = v; 1212 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1213 1.2.10.2 tls 1214 1.2.10.2 tls for (; c--; h += 2) { 1215 1.2.10.2 tls r->pci_addr = h; 1216 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1217 1.2.10.2 tls if (h & 2) 1218 1.2.10.2 tls p++; 1219 1.2.10.2 tls *a++ = *p; 1220 1.2.10.2 tls } 1221 1.2.10.2 tls } 1222 1.2.10.2 tls } 1223 1.2.10.2 tls 1224 1.2.10.2 tls void 1225 1.2.10.2 tls dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1226 1.2.10.2 tls uint32_t *a, bus_size_t c) 1227 1.2.10.2 tls { 1228 1.2.10.2 tls volatile uint32_t *p; 1229 1.2.10.2 tls 1230 1.2.10.2 tls h += o; 1231 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1232 1.2.10.2 tls p = (volatile uint32_t *)h; 1233 1.2.10.2 tls while (c--) 1234 1.2.10.2 tls *a++ = *p++; 1235 1.2.10.2 tls } else { 1236 1.2.10.2 tls struct dino_softc *sc = v; 1237 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1238 1.2.10.2 tls 1239 1.2.10.2 tls for (; c--; h += 4) { 1240 1.2.10.2 tls r->pci_addr = h; 1241 1.2.10.2 tls *a++ = r->pci_io_data; 1242 1.2.10.2 tls } 1243 1.2.10.2 tls } 1244 1.2.10.2 tls } 1245 1.2.10.2 tls 1246 1.2.10.2 tls void 1247 1.2.10.2 tls dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1248 1.2.10.2 tls uint64_t *a, bus_size_t c) 1249 1.2.10.2 tls { 1250 1.2.10.2 tls panic("dino_rrr_8: not implemented"); 1251 1.2.10.2 tls } 1252 1.2.10.2 tls 1253 1.2.10.2 tls void 1254 1.2.10.2 tls dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1255 1.2.10.2 tls const uint16_t *a, bus_size_t c) 1256 1.2.10.2 tls { 1257 1.2.10.2 tls volatile uint16_t *p; 1258 1.2.10.2 tls 1259 1.2.10.2 tls h += o; 1260 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1261 1.2.10.2 tls p = (volatile uint16_t *)h; 1262 1.2.10.2 tls while (c--) 1263 1.2.10.2 tls *p++ = *a++; 1264 1.2.10.2 tls } else { 1265 1.2.10.2 tls struct dino_softc *sc = v; 1266 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1267 1.2.10.2 tls 1268 1.2.10.2 tls for (; c--; h += 2) { 1269 1.2.10.2 tls r->pci_addr = h; 1270 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1271 1.2.10.2 tls if (h & 2) 1272 1.2.10.2 tls p++; 1273 1.2.10.2 tls *p = *a++; 1274 1.2.10.2 tls } 1275 1.2.10.2 tls } 1276 1.2.10.2 tls } 1277 1.2.10.2 tls 1278 1.2.10.2 tls void 1279 1.2.10.2 tls dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1280 1.2.10.2 tls const uint32_t *a, bus_size_t c) 1281 1.2.10.2 tls { 1282 1.2.10.2 tls volatile uint32_t *p; 1283 1.2.10.2 tls 1284 1.2.10.2 tls c /= 4; 1285 1.2.10.2 tls h += o; 1286 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1287 1.2.10.2 tls p = (volatile uint32_t *)h; 1288 1.2.10.2 tls while (c--) 1289 1.2.10.2 tls *p++ = *a++; 1290 1.2.10.2 tls } else { 1291 1.2.10.2 tls struct dino_softc *sc = v; 1292 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1293 1.2.10.2 tls 1294 1.2.10.2 tls for (; c--; h += 4) { 1295 1.2.10.2 tls r->pci_addr = h; 1296 1.2.10.2 tls r->pci_io_data = *a++; 1297 1.2.10.2 tls } 1298 1.2.10.2 tls } 1299 1.2.10.2 tls } 1300 1.2.10.2 tls 1301 1.2.10.2 tls void 1302 1.2.10.2 tls dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1303 1.2.10.2 tls const uint64_t *a, bus_size_t c) 1304 1.2.10.2 tls { 1305 1.2.10.2 tls panic("dino_wrr_8: not implemented"); 1306 1.2.10.2 tls } 1307 1.2.10.2 tls 1308 1.2.10.2 tls void 1309 1.2.10.2 tls dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1310 1.2.10.2 tls { 1311 1.2.10.2 tls volatile uint8_t *p; 1312 1.2.10.2 tls 1313 1.2.10.2 tls h += o; 1314 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1315 1.2.10.2 tls p = (volatile uint8_t *)h; 1316 1.2.10.2 tls while (c--) 1317 1.2.10.2 tls *p++ = vv; 1318 1.2.10.2 tls } else { 1319 1.2.10.2 tls struct dino_softc *sc = v; 1320 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1321 1.2.10.2 tls 1322 1.2.10.2 tls for (; c--; h++) { 1323 1.2.10.2 tls r->pci_addr = h; 1324 1.2.10.2 tls p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1325 1.2.10.2 tls *p = vv; 1326 1.2.10.2 tls } 1327 1.2.10.2 tls } 1328 1.2.10.2 tls } 1329 1.2.10.2 tls 1330 1.2.10.2 tls void 1331 1.2.10.2 tls dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1332 1.2.10.2 tls { 1333 1.2.10.2 tls volatile uint16_t *p; 1334 1.2.10.2 tls 1335 1.2.10.2 tls h += o; 1336 1.2.10.2 tls vv = htole16(vv); 1337 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1338 1.2.10.2 tls p = (volatile uint16_t *)h; 1339 1.2.10.2 tls while (c--) 1340 1.2.10.2 tls *p++ = vv; 1341 1.2.10.2 tls } else { 1342 1.2.10.2 tls struct dino_softc *sc = v; 1343 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1344 1.2.10.2 tls 1345 1.2.10.2 tls for (; c--; h += 2) { 1346 1.2.10.2 tls r->pci_addr = h; 1347 1.2.10.2 tls p = (volatile uint16_t *)&r->pci_io_data; 1348 1.2.10.2 tls if (h & 2) 1349 1.2.10.2 tls p++; 1350 1.2.10.2 tls *p = vv; 1351 1.2.10.2 tls } 1352 1.2.10.2 tls } 1353 1.2.10.2 tls } 1354 1.2.10.2 tls 1355 1.2.10.2 tls void 1356 1.2.10.2 tls dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1357 1.2.10.2 tls { 1358 1.2.10.2 tls volatile uint32_t *p; 1359 1.2.10.2 tls 1360 1.2.10.2 tls h += o; 1361 1.2.10.2 tls vv = htole32(vv); 1362 1.2.10.2 tls if (h & HPPA_IOSPACE) { 1363 1.2.10.2 tls p = (volatile uint32_t *)h; 1364 1.2.10.2 tls while (c--) 1365 1.2.10.2 tls *p++ = vv; 1366 1.2.10.2 tls } else { 1367 1.2.10.2 tls struct dino_softc *sc = v; 1368 1.2.10.2 tls volatile struct dino_regs *r = sc->sc_regs; 1369 1.2.10.2 tls 1370 1.2.10.2 tls for (; c--; h += 4) { 1371 1.2.10.2 tls r->pci_addr = h; 1372 1.2.10.2 tls r->pci_io_data = vv; 1373 1.2.10.2 tls } 1374 1.2.10.2 tls } 1375 1.2.10.2 tls } 1376 1.2.10.2 tls 1377 1.2.10.2 tls void 1378 1.2.10.2 tls dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1379 1.2.10.2 tls { 1380 1.2.10.2 tls panic("dino_sr_8: not implemented"); 1381 1.2.10.2 tls } 1382 1.2.10.2 tls 1383 1.2.10.2 tls void 1384 1.2.10.2 tls dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1385 1.2.10.2 tls bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1386 1.2.10.2 tls { 1387 1.2.10.2 tls while (c--) 1388 1.2.10.2 tls dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1389 1.2.10.2 tls } 1390 1.2.10.2 tls 1391 1.2.10.2 tls void 1392 1.2.10.2 tls dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1393 1.2.10.2 tls bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1394 1.2.10.2 tls { 1395 1.2.10.2 tls while (c--) { 1396 1.2.10.2 tls dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1397 1.2.10.2 tls o1 += 2; 1398 1.2.10.2 tls o2 += 2; 1399 1.2.10.2 tls } 1400 1.2.10.2 tls } 1401 1.2.10.2 tls 1402 1.2.10.2 tls void 1403 1.2.10.2 tls dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1404 1.2.10.2 tls bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1405 1.2.10.2 tls { 1406 1.2.10.2 tls while (c--) { 1407 1.2.10.2 tls dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1408 1.2.10.2 tls o1 += 4; 1409 1.2.10.2 tls o2 += 4; 1410 1.2.10.2 tls } 1411 1.2.10.2 tls } 1412 1.2.10.2 tls 1413 1.2.10.2 tls void 1414 1.2.10.2 tls dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1415 1.2.10.2 tls bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1416 1.2.10.2 tls { 1417 1.2.10.2 tls while (c--) { 1418 1.2.10.2 tls dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1419 1.2.10.2 tls o1 += 8; 1420 1.2.10.2 tls o2 += 8; 1421 1.2.10.2 tls } 1422 1.2.10.2 tls } 1423 1.2.10.2 tls 1424 1.2.10.2 tls 1425 1.2.10.2 tls const struct hppa_bus_space_tag dino_iomemt = { 1426 1.2.10.2 tls NULL, 1427 1.2.10.2 tls 1428 1.2.10.2 tls NULL, dino_unmap, dino_subregion, NULL, dino_free, 1429 1.2.10.2 tls dino_barrier, dino_vaddr, dino_mmap, 1430 1.2.10.2 tls dino_r1, dino_r2, dino_r4, dino_r8, 1431 1.2.10.2 tls dino_w1, dino_w2, dino_w4, dino_w8, 1432 1.2.10.2 tls dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1433 1.2.10.2 tls dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1434 1.2.10.2 tls dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1435 1.2.10.2 tls dino_rrm_2, dino_rrm_4, dino_rrm_8, 1436 1.2.10.2 tls dino_wrm_2, dino_wrm_4, dino_wrm_8, 1437 1.2.10.2 tls dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1438 1.2.10.2 tls dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1439 1.2.10.2 tls dino_rrr_2, dino_rrr_4, dino_rrr_8, 1440 1.2.10.2 tls dino_wrr_2, dino_wrr_4, dino_wrr_8, 1441 1.2.10.2 tls dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1442 1.2.10.2 tls dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1443 1.2.10.2 tls }; 1444 1.2.10.2 tls 1445 1.2.10.2 tls int 1446 1.2.10.2 tls dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1447 1.2.10.2 tls bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1448 1.2.10.2 tls { 1449 1.2.10.2 tls struct dino_softc *sc = v; 1450 1.2.10.2 tls 1451 1.2.10.2 tls /* TODO check the addresses, boundary, enable dma */ 1452 1.2.10.2 tls 1453 1.2.10.2 tls return bus_dmamap_create(sc->sc_dmat, size, nsegments, 1454 1.2.10.2 tls maxsegsz, boundary, flags, dmamp); 1455 1.2.10.2 tls } 1456 1.2.10.2 tls 1457 1.2.10.2 tls void 1458 1.2.10.2 tls dino_dmamap_destroy(void *v, bus_dmamap_t map) 1459 1.2.10.2 tls { 1460 1.2.10.2 tls struct dino_softc *sc = v; 1461 1.2.10.2 tls 1462 1.2.10.2 tls bus_dmamap_destroy(sc->sc_dmat, map); 1463 1.2.10.2 tls } 1464 1.2.10.2 tls 1465 1.2.10.2 tls int 1466 1.2.10.2 tls dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1467 1.2.10.2 tls struct proc *p, int flags) 1468 1.2.10.2 tls { 1469 1.2.10.2 tls struct dino_softc *sc = v; 1470 1.2.10.2 tls 1471 1.2.10.2 tls return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); 1472 1.2.10.2 tls } 1473 1.2.10.2 tls 1474 1.2.10.2 tls int 1475 1.2.10.2 tls dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1476 1.2.10.2 tls { 1477 1.2.10.2 tls struct dino_softc *sc = v; 1478 1.2.10.2 tls 1479 1.2.10.2 tls return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); 1480 1.2.10.2 tls } 1481 1.2.10.2 tls 1482 1.2.10.2 tls int 1483 1.2.10.2 tls dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1484 1.2.10.2 tls { 1485 1.2.10.2 tls struct dino_softc *sc = v; 1486 1.2.10.2 tls 1487 1.2.10.2 tls return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); 1488 1.2.10.2 tls } 1489 1.2.10.2 tls 1490 1.2.10.2 tls int 1491 1.2.10.2 tls dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1492 1.2.10.2 tls int nsegs, bus_size_t size, int flags) 1493 1.2.10.2 tls { 1494 1.2.10.2 tls struct dino_softc *sc = v; 1495 1.2.10.2 tls 1496 1.2.10.2 tls return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); 1497 1.2.10.2 tls } 1498 1.2.10.2 tls 1499 1.2.10.2 tls void 1500 1.2.10.2 tls dino_dmamap_unload(void *v, bus_dmamap_t map) 1501 1.2.10.2 tls { 1502 1.2.10.2 tls struct dino_softc *sc = v; 1503 1.2.10.2 tls 1504 1.2.10.2 tls bus_dmamap_unload(sc->sc_dmat, map); 1505 1.2.10.2 tls } 1506 1.2.10.2 tls 1507 1.2.10.2 tls void 1508 1.2.10.2 tls dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1509 1.2.10.2 tls bus_size_t len, int ops) 1510 1.2.10.2 tls { 1511 1.2.10.2 tls struct dino_softc *sc = v; 1512 1.2.10.2 tls 1513 1.2.10.2 tls return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); 1514 1.2.10.2 tls } 1515 1.2.10.2 tls 1516 1.2.10.2 tls int 1517 1.2.10.2 tls dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1518 1.2.10.2 tls bus_size_t boundary, bus_dma_segment_t *segs, 1519 1.2.10.2 tls int nsegs, int *rsegs, int flags) 1520 1.2.10.2 tls { 1521 1.2.10.2 tls struct dino_softc *sc = v; 1522 1.2.10.2 tls 1523 1.2.10.2 tls return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1524 1.2.10.2 tls segs, nsegs, rsegs, flags); 1525 1.2.10.2 tls } 1526 1.2.10.2 tls 1527 1.2.10.2 tls void 1528 1.2.10.2 tls dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1529 1.2.10.2 tls { 1530 1.2.10.2 tls struct dino_softc *sc = v; 1531 1.2.10.2 tls 1532 1.2.10.2 tls bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1533 1.2.10.2 tls } 1534 1.2.10.2 tls 1535 1.2.10.2 tls int 1536 1.2.10.2 tls dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1537 1.2.10.2 tls void **kvap, int flags) 1538 1.2.10.2 tls { 1539 1.2.10.2 tls struct dino_softc *sc = v; 1540 1.2.10.2 tls 1541 1.2.10.2 tls return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); 1542 1.2.10.2 tls } 1543 1.2.10.2 tls 1544 1.2.10.2 tls void 1545 1.2.10.2 tls dino_dmamem_unmap(void *v, void *kva, size_t size) 1546 1.2.10.2 tls { 1547 1.2.10.2 tls struct dino_softc *sc = v; 1548 1.2.10.2 tls 1549 1.2.10.2 tls bus_dmamem_unmap(sc->sc_dmat, kva, size); 1550 1.2.10.2 tls } 1551 1.2.10.2 tls 1552 1.2.10.2 tls paddr_t 1553 1.2.10.2 tls dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1554 1.2.10.2 tls int prot, int flags) 1555 1.2.10.2 tls { 1556 1.2.10.2 tls struct dino_softc *sc = v; 1557 1.2.10.2 tls 1558 1.2.10.2 tls return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); 1559 1.2.10.2 tls } 1560 1.2.10.2 tls 1561 1.2.10.2 tls const struct hppa_bus_dma_tag dino_dmat = { 1562 1.2.10.2 tls NULL, 1563 1.2.10.2 tls dino_dmamap_create, dino_dmamap_destroy, 1564 1.2.10.2 tls dino_dmamap_load, dino_dmamap_load_mbuf, 1565 1.2.10.2 tls dino_dmamap_load_uio, dino_dmamap_load_raw, 1566 1.2.10.2 tls dino_dmamap_unload, dino_dmamap_sync, 1567 1.2.10.2 tls 1568 1.2.10.2 tls dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1569 1.2.10.2 tls dino_dmamem_unmap, dino_dmamem_mmap 1570 1.2.10.2 tls }; 1571 1.2.10.2 tls 1572 1.2.10.2 tls const struct hppa_pci_chipset_tag dino_pc = { 1573 1.2.10.2 tls NULL, 1574 1.2.10.2 tls dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, 1575 1.2.10.2 tls dino_conf_read, dino_conf_write, 1576 1.2.10.2 tls dino_intr_map, dino_intr_string, 1577 1.2.10.2 tls dino_intr_establish, dino_intr_disestablish, 1578 1.2.10.2 tls #if NCARDBUS > 0 1579 1.2.10.2 tls dino_alloc_parent 1580 1.2.10.2 tls #else 1581 1.2.10.2 tls NULL 1582 1.2.10.2 tls #endif 1583 1.2.10.2 tls }; 1584 1.2.10.2 tls 1585 1.2.10.2 tls int 1586 1.2.10.2 tls dinomatch(device_t parent, cfdata_t cfdata, void *aux) 1587 1.2.10.2 tls { 1588 1.2.10.2 tls struct confargs *ca = aux; 1589 1.2.10.2 tls 1590 1.2.10.2 tls /* there will be only one */ 1591 1.2.10.2 tls if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 1592 1.2.10.2 tls ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 1593 1.2.10.2 tls return 0; 1594 1.2.10.2 tls 1595 1.2.10.2 tls /* do not match on the elroy family */ 1596 1.2.10.2 tls if (ca->ca_type.iodc_model == 0x78) 1597 1.2.10.2 tls return 0; 1598 1.2.10.2 tls 1599 1.2.10.2 tls return 1; 1600 1.2.10.2 tls } 1601 1.2.10.2 tls 1602 1.2.10.2 tls void 1603 1.2.10.2 tls dinoattach(device_t parent, device_t self, void *aux) 1604 1.2.10.2 tls { 1605 1.2.10.2 tls struct dino_softc *sc = device_private(self); 1606 1.2.10.2 tls struct confargs *ca = (struct confargs *)aux, nca; 1607 1.2.10.2 tls struct pcibus_attach_args pba; 1608 1.2.10.2 tls volatile struct dino_regs *r; 1609 1.2.10.2 tls struct cpu_info *ci = &cpus[0]; 1610 1.2.10.2 tls const char *p = NULL; 1611 1.2.10.2 tls int s, ver; 1612 1.2.10.2 tls 1613 1.2.10.2 tls sc->sc_dv = self; 1614 1.2.10.2 tls sc->sc_bt = ca->ca_iot; 1615 1.2.10.2 tls sc->sc_dmat = ca->ca_dmatag; 1616 1.2.10.2 tls 1617 1.2.10.2 tls ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 1618 1.2.10.2 tls if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 1619 1.2.10.2 tls aprint_error_dev(self, ": can't allocate interrupt"); 1620 1.2.10.2 tls return; 1621 1.2.10.2 tls } 1622 1.2.10.2 tls 1623 1.2.10.2 tls if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1624 1.2.10.2 tls aprint_error(": can't map space\n"); 1625 1.2.10.2 tls return; 1626 1.2.10.2 tls } 1627 1.2.10.2 tls 1628 1.2.10.2 tls sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1629 1.2.10.2 tls #ifdef trust_the_firmware_to_proper_initialize_everything 1630 1.2.10.2 tls r->io_addr_en = 0; 1631 1.2.10.2 tls r->io_control = 0x80; 1632 1.2.10.2 tls r->pamr = 0; 1633 1.2.10.2 tls r->papr = 0; 1634 1.2.10.2 tls r->io_fbb_en |= 1; 1635 1.2.10.2 tls r->damode = 0; 1636 1.2.10.2 tls r->gmask &= ~1; /* allow GSC bus req */ 1637 1.2.10.2 tls r->pciror = 0; 1638 1.2.10.2 tls r->pciwor = 0; 1639 1.2.10.2 tls r->brdg_feat = 0xc0000000; 1640 1.2.10.2 tls #endif 1641 1.2.10.2 tls 1642 1.2.10.2 tls snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1643 1.2.10.2 tls "%s_io", device_xname(self)); 1644 1.2.10.2 tls if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1645 1.2.10.2 tls NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { 1646 1.2.10.2 tls aprint_error(": can't allocate I/O extent map\n"); 1647 1.2.10.2 tls bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE); 1648 1.2.10.2 tls return; 1649 1.2.10.2 tls } 1650 1.2.10.2 tls 1651 1.2.10.2 tls /* interrupts guts */ 1652 1.2.10.2 tls s = splhigh(); 1653 1.2.10.2 tls r->icr = 0; 1654 1.2.10.2 tls r->imr = ~0; 1655 1.2.10.2 tls (void)r->irr0; 1656 1.2.10.2 tls r->imr = 0; 1657 1.2.10.2 tls r->iar0 = ci->ci_hpa | (31 - ca->ca_irq); 1658 1.2.10.2 tls splx(s); 1659 1.2.10.2 tls /* Establish the interrupt register. */ 1660 1.2.10.2 tls hppa_interrupt_register_establish(ci, &sc->sc_ir); 1661 1.2.10.2 tls sc->sc_ir.ir_name = device_xname(self); 1662 1.2.10.2 tls sc->sc_ir.ir_mask = &r->imr; 1663 1.2.10.2 tls sc->sc_ir.ir_req = &r->irr0; 1664 1.2.10.2 tls sc->sc_ir.ir_level = &r->ilr; 1665 1.2.10.2 tls /* Add the I/O interrupt register. */ 1666 1.2.10.2 tls 1667 1.2.10.2 tls sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir, 1668 1.2.10.2 tls &ci->ci_ir, ca->ca_irq); 1669 1.2.10.2 tls 1670 1.2.10.2 tls /* TODO establish the bus error interrupt */ 1671 1.2.10.2 tls 1672 1.2.10.2 tls ver = ca->ca_type.iodc_revision; 1673 1.2.10.2 tls switch ((ca->ca_type.iodc_model << 4) | 1674 1.2.10.2 tls (ca->ca_type.iodc_revision >> 4)) { 1675 1.2.10.2 tls case 0x05d: 1676 1.2.10.2 tls p = "Dino (card)"; /* j2240 */ 1677 1.2.10.2 tls /* FALLTHROUGH */ 1678 1.2.10.2 tls case 0x680: 1679 1.2.10.2 tls if (!p) 1680 1.2.10.2 tls p = "Dino"; 1681 1.2.10.2 tls switch (ver & 0xf) { 1682 1.2.10.2 tls case 0: ver = 0x20; break; 1683 1.2.10.2 tls case 1: ver = 0x21; break; 1684 1.2.10.2 tls case 2: ver = 0x30; break; 1685 1.2.10.2 tls case 3: ver = 0x31; break; 1686 1.2.10.2 tls } 1687 1.2.10.2 tls break; 1688 1.2.10.2 tls 1689 1.2.10.2 tls case 0x682: 1690 1.2.10.2 tls p = "Cujo"; 1691 1.2.10.2 tls switch (ver & 0xf) { 1692 1.2.10.2 tls case 0: ver = 0x10; break; 1693 1.2.10.2 tls case 1: ver = 0x20; break; 1694 1.2.10.2 tls } 1695 1.2.10.2 tls break; 1696 1.2.10.2 tls 1697 1.2.10.2 tls default: 1698 1.2.10.2 tls p = "Mojo"; 1699 1.2.10.2 tls break; 1700 1.2.10.2 tls } 1701 1.2.10.2 tls 1702 1.2.10.2 tls sc->sc_ver = ver; 1703 1.2.10.2 tls aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); 1704 1.2.10.2 tls 1705 1.2.10.2 tls sc->sc_iot = dino_iomemt; 1706 1.2.10.2 tls sc->sc_iot.hbt_cookie = sc; 1707 1.2.10.2 tls sc->sc_iot.hbt_map = dino_iomap; 1708 1.2.10.2 tls sc->sc_iot.hbt_alloc = dino_ioalloc; 1709 1.2.10.2 tls sc->sc_memt = dino_iomemt; 1710 1.2.10.2 tls sc->sc_memt.hbt_cookie = sc; 1711 1.2.10.2 tls sc->sc_memt.hbt_map = dino_memmap; 1712 1.2.10.2 tls sc->sc_memt.hbt_alloc = dino_memalloc; 1713 1.2.10.2 tls sc->sc_pc = dino_pc; 1714 1.2.10.2 tls sc->sc_pc._cookie = sc; 1715 1.2.10.2 tls sc->sc_dmatag = dino_dmat; 1716 1.2.10.2 tls sc->sc_dmatag._cookie = sc; 1717 1.2.10.2 tls 1718 1.2.10.2 tls /* scan for ps2 kbd/ms, serial, and flying toasters */ 1719 1.2.10.2 tls nca = *ca; 1720 1.2.10.2 tls 1721 1.2.10.2 tls nca.ca_hpabase = 0; 1722 1.2.10.2 tls nca.ca_nmodules = MAXMODBUS; 1723 1.2.10.2 tls pdc_scanbus(self, &nca, dino_callback); 1724 1.2.10.2 tls 1725 1.2.10.2 tls memset(&pba, 0, sizeof(pba)); 1726 1.2.10.2 tls pba.pba_iot = &sc->sc_iot; 1727 1.2.10.2 tls pba.pba_memt = &sc->sc_memt; 1728 1.2.10.2 tls pba.pba_dmat = &sc->sc_dmatag; 1729 1.2.10.2 tls pba.pba_pc = &sc->sc_pc; 1730 1.2.10.2 tls pba.pba_bus = 0; 1731 1.2.10.2 tls pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 1732 1.2.10.2 tls config_found_ia(self, "pcibus", &pba, pcibusprint); 1733 1.2.10.2 tls } 1734 1.2.10.2 tls 1735 1.2.10.2 tls static device_t 1736 1.2.10.2 tls dino_callback(device_t self, struct confargs *ca) 1737 1.2.10.2 tls { 1738 1.2.10.2 tls 1739 1.2.10.2 tls return config_found_sm_loc(self, "dino", NULL, ca, mbprint, mbsubmatch); 1740 1.2.10.2 tls } 1741
Indexes created Thu Oct 02 07:10:07 GMT 2025