dino.c revision 1.2.4.2
1 1.2.4.2 rmind /* $NetBSD: dino.c,v 1.2.4.2 2014/05/18 17:45:10 rmind Exp $ */ 2 1.2.4.2 rmind 3 1.2.4.2 rmind /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ 4 1.2.4.2 rmind 5 1.2.4.2 rmind /* 6 1.2.4.2 rmind * Copyright (c) 2003 Michael Shalayeff 7 1.2.4.2 rmind * All rights reserved. 8 1.2.4.2 rmind * 9 1.2.4.2 rmind * Redistribution and use in source and binary forms, with or without 10 1.2.4.2 rmind * modification, are permitted provided that the following conditions 11 1.2.4.2 rmind * are met: 12 1.2.4.2 rmind * 1. Redistributions of source code must retain the above copyright 13 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer. 14 1.2.4.2 rmind * 2. Redistributions in binary form must reproduce the above copyright 15 1.2.4.2 rmind * notice, this list of conditions and the following disclaimer in the 16 1.2.4.2 rmind * documentation and/or other materials provided with the distribution. 17 1.2.4.2 rmind * 18 1.2.4.2 rmind * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.2.4.2 rmind * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.2.4.2 rmind * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.2.4.2 rmind * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 1.2.4.2 rmind * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 1.2.4.2 rmind * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 1.2.4.2 rmind * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.2.4.2 rmind * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 1.2.4.2 rmind * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 1.2.4.2 rmind * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 1.2.4.2 rmind * THE POSSIBILITY OF SUCH DAMAGE. 29 1.2.4.2 rmind */ 30 1.2.4.2 rmind 31 1.2.4.2 rmind #include <sys/cdefs.h> 32 1.2.4.2 rmind __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.2.4.2 2014/05/18 17:45:10 rmind Exp $"); 33 1.2.4.2 rmind 34 1.2.4.2 rmind /* #include "cardbus.h" */ 35 1.2.4.2 rmind 36 1.2.4.2 rmind #include <sys/param.h> 37 1.2.4.2 rmind #include <sys/systm.h> 38 1.2.4.2 rmind #include <sys/device.h> 39 1.2.4.2 rmind #include <sys/reboot.h> 40 1.2.4.2 rmind #include <sys/malloc.h> 41 1.2.4.2 rmind #include <sys/extent.h> 42 1.2.4.2 rmind 43 1.2.4.2 rmind #include <machine/iomod.h> 44 1.2.4.2 rmind #include <machine/autoconf.h> 45 1.2.4.2 rmind #include <machine/intr.h> 46 1.2.4.2 rmind 47 1.2.4.2 rmind #include <hppa/include/vmparam.h> 48 1.2.4.2 rmind #include <hppa/dev/cpudevs.h> 49 1.2.4.2 rmind 50 1.2.4.2 rmind #if NCARDBUS > 0 51 1.2.4.2 rmind #include <dev/cardbus/rbus.h> 52 1.2.4.2 rmind #endif 53 1.2.4.2 rmind 54 1.2.4.2 rmind #include <dev/pci/pcireg.h> 55 1.2.4.2 rmind #include <dev/pci/pcivar.h> 56 1.2.4.2 rmind #include <dev/pci/pcidevs.h> 57 1.2.4.2 rmind 58 1.2.4.2 rmind #define DINO_MEM_CHUNK 0x800000 59 1.2.4.2 rmind 60 1.2.4.2 rmind /* from machdep.c */ 61 1.2.4.2 rmind extern struct extent *hppa_io_extent; 62 1.2.4.2 rmind 63 1.2.4.2 rmind struct dino_regs { 64 1.2.4.2 rmind /* HPA Supervisory Register Set */ 65 1.2.4.2 rmind uint32_t pad0; /* 0x000 */ 66 1.2.4.2 rmind uint32_t iar0; /* 0x004 rw intr addr reg 0 */ 67 1.2.4.2 rmind uint32_t iodc; /* 0x008 rw iodc data/addr */ 68 1.2.4.2 rmind uint32_t irr0; /* 0x00c r intr req reg 0 */ 69 1.2.4.2 rmind uint32_t iar1; /* 0x010 rw intr addr reg 1 */ 70 1.2.4.2 rmind uint32_t irr1; /* 0x014 r intr req reg 1 */ 71 1.2.4.2 rmind uint32_t imr; /* 0x018 rw intr mask reg */ 72 1.2.4.2 rmind uint32_t ipr; /* 0x01c rw intr pending reg */ 73 1.2.4.2 rmind uint32_t toc_addr; /* 0x020 rw TOC addr reg */ 74 1.2.4.2 rmind uint32_t icr; /* 0x024 rw intr control reg */ 75 1.2.4.2 rmind uint32_t ilr; /* 0x028 r intr level reg */ 76 1.2.4.2 rmind uint32_t pad1; /* 0x02c */ 77 1.2.4.2 rmind uint32_t io_command; /* 0x030 w command register */ 78 1.2.4.2 rmind uint32_t io_status; /* 0x034 r status register */ 79 1.2.4.2 rmind uint32_t io_control; /* 0x038 rw control register */ 80 1.2.4.2 rmind uint32_t pad2; /* 0x03c AUX registers follow */ 81 1.2.4.2 rmind 82 1.2.4.2 rmind /* HPA Auxiliary Register Set */ 83 1.2.4.2 rmind uint32_t io_gsc_err_addr;/* 0x040 GSC error address */ 84 1.2.4.2 rmind uint32_t io_err_info; /* 0x044 error info register */ 85 1.2.4.2 rmind uint32_t io_pci_err_addr;/* 0x048 PCI error address */ 86 1.2.4.2 rmind uint32_t pad3[4]; /* 0x04c */ 87 1.2.4.2 rmind uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 88 1.2.4.2 rmind uint32_t io_addr_en; /* 0x060 address enable reg */ 89 1.2.4.2 rmind uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 90 1.2.4.2 rmind uint32_t pci_conf_data; /* 0x068 PCI conf data reg */ 91 1.2.4.2 rmind uint32_t pci_io_data; /* 0x06c PCI io data reg */ 92 1.2.4.2 rmind uint32_t pci_mem_data; /* 0x070 PCI memory data reg */ 93 1.2.4.2 rmind uint32_t pad4[0x740/4]; /* 0x074 */ 94 1.2.4.2 rmind 95 1.2.4.2 rmind /* HPA Bus (GSC) Specific-Dependent Register Set */ 96 1.2.4.2 rmind uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 97 1.2.4.2 rmind uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 98 1.2.4.2 rmind 99 1.2.4.2 rmind /* HPA HVERSION (Dino)-Dependent Register Set */ 100 1.2.4.2 rmind uint32_t gmask; /* 0x800 GSC arbitration mask */ 101 1.2.4.2 rmind uint32_t pamr; /* 0x804 PCI arbitration mask */ 102 1.2.4.2 rmind uint32_t papr; /* 0x808 PCI arbitration priority */ 103 1.2.4.2 rmind uint32_t damode; /* 0x80c PCI arbitration mode */ 104 1.2.4.2 rmind uint32_t pcicmd; /* 0x810 PCI command register */ 105 1.2.4.2 rmind uint32_t pcists; /* 0x814 PCI status register */ 106 1.2.4.2 rmind uint32_t pad6; /* 0x818 */ 107 1.2.4.2 rmind uint32_t mltim; /* 0x81c PCI master latency timer */ 108 1.2.4.2 rmind uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 109 1.2.4.2 rmind uint32_t pciror; /* 0x824 PCI read optimization reg */ 110 1.2.4.2 rmind uint32_t pciwor; /* 0x828 PCI write optimization reg */ 111 1.2.4.2 rmind uint32_t pad7; /* 0x82c */ 112 1.2.4.2 rmind uint32_t tltim; /* 0x830 PCI target latency reg */ 113 1.2.4.2 rmind }; 114 1.2.4.2 rmind 115 1.2.4.2 rmind struct dino_softc { 116 1.2.4.2 rmind device_t sc_dv; 117 1.2.4.2 rmind 118 1.2.4.2 rmind int sc_ver; 119 1.2.4.2 rmind void *sc_ih; 120 1.2.4.2 rmind struct hppa_interrupt_register sc_ir; 121 1.2.4.2 rmind bus_space_tag_t sc_bt; 122 1.2.4.2 rmind bus_space_handle_t sc_bh; 123 1.2.4.2 rmind bus_dma_tag_t sc_dmat; 124 1.2.4.2 rmind volatile struct dino_regs *sc_regs; 125 1.2.4.2 rmind 126 1.2.4.2 rmind struct hppa_pci_chipset_tag sc_pc; 127 1.2.4.2 rmind struct hppa_bus_space_tag sc_iot; 128 1.2.4.2 rmind char sc_ioexname[20]; 129 1.2.4.2 rmind struct extent *sc_ioex; 130 1.2.4.2 rmind struct hppa_bus_space_tag sc_memt; 131 1.2.4.2 rmind int sc_memrefcount[30]; 132 1.2.4.2 rmind struct hppa_bus_dma_tag sc_dmatag; 133 1.2.4.2 rmind }; 134 1.2.4.2 rmind 135 1.2.4.2 rmind int dinomatch(device_t, struct cfdata *, void *); 136 1.2.4.2 rmind void dinoattach(device_t, device_t, void *); 137 1.2.4.2 rmind static device_t dino_callback(device_t, struct confargs *); 138 1.2.4.2 rmind 139 1.2.4.2 rmind CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, 140 1.2.4.2 rmind NULL); 141 1.2.4.2 rmind 142 1.2.4.2 rmind void dino_attach_hook(device_t, device_t, 143 1.2.4.2 rmind struct pcibus_attach_args *); 144 1.2.4.2 rmind void dino_enable_bus(struct dino_softc *, int); 145 1.2.4.2 rmind int dino_maxdevs(void *, int); 146 1.2.4.2 rmind pcitag_t dino_make_tag(void *, int, int, int); 147 1.2.4.2 rmind void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 148 1.2.4.2 rmind pcireg_t dino_conf_read(void *, pcitag_t, int); 149 1.2.4.2 rmind void dino_conf_write(void *, pcitag_t, int, pcireg_t); 150 1.2.4.2 rmind 151 1.2.4.2 rmind int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 152 1.2.4.2 rmind const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t); 153 1.2.4.2 rmind void *dino_intr_establish(void *, pci_intr_handle_t, int, 154 1.2.4.2 rmind int (*)(void *), void *); 155 1.2.4.2 rmind void dino_intr_disestablish(void *, void *); 156 1.2.4.2 rmind 157 1.2.4.2 rmind void *dino_alloc_parent(device_t, struct pci_attach_args *, int); 158 1.2.4.2 rmind 159 1.2.4.2 rmind int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 160 1.2.4.2 rmind int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 161 1.2.4.2 rmind int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 162 1.2.4.2 rmind bus_space_handle_t *); 163 1.2.4.2 rmind int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 164 1.2.4.2 rmind bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 165 1.2.4.2 rmind int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 166 1.2.4.2 rmind bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 167 1.2.4.2 rmind void dino_unmap(void *, bus_space_handle_t, bus_size_t); 168 1.2.4.2 rmind void dino_free(void *, bus_space_handle_t, bus_size_t); 169 1.2.4.2 rmind void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 170 1.2.4.2 rmind void *dino_vaddr(void *, bus_space_handle_t); 171 1.2.4.2 rmind paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int); 172 1.2.4.2 rmind 173 1.2.4.2 rmind uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 174 1.2.4.2 rmind uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 175 1.2.4.2 rmind uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 176 1.2.4.2 rmind uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 177 1.2.4.2 rmind void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t); 178 1.2.4.2 rmind void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 179 1.2.4.2 rmind void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 180 1.2.4.2 rmind void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t); 181 1.2.4.2 rmind void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 182 1.2.4.2 rmind void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 183 1.2.4.2 rmind void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 184 1.2.4.2 rmind void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 185 1.2.4.2 rmind void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 186 1.2.4.2 rmind bus_size_t); 187 1.2.4.2 rmind void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 188 1.2.4.2 rmind bus_size_t); 189 1.2.4.2 rmind void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 190 1.2.4.2 rmind bus_size_t); 191 1.2.4.2 rmind void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 192 1.2.4.2 rmind bus_size_t); 193 1.2.4.2 rmind void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 194 1.2.4.2 rmind void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 195 1.2.4.2 rmind void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 196 1.2.4.2 rmind void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 197 1.2.4.2 rmind void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 198 1.2.4.2 rmind bus_size_t); 199 1.2.4.2 rmind void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 200 1.2.4.2 rmind bus_size_t); 201 1.2.4.2 rmind void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 202 1.2.4.2 rmind bus_size_t); 203 1.2.4.2 rmind void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 204 1.2.4.2 rmind bus_size_t); 205 1.2.4.2 rmind void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 206 1.2.4.2 rmind bus_size_t); 207 1.2.4.2 rmind void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 208 1.2.4.2 rmind bus_size_t); 209 1.2.4.2 rmind void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 210 1.2.4.2 rmind void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 211 1.2.4.2 rmind void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 212 1.2.4.2 rmind void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 213 1.2.4.2 rmind void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 214 1.2.4.2 rmind bus_size_t); 215 1.2.4.2 rmind void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 216 1.2.4.2 rmind bus_size_t); 217 1.2.4.2 rmind void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 218 1.2.4.2 rmind bus_size_t); 219 1.2.4.2 rmind void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 220 1.2.4.2 rmind bus_size_t); 221 1.2.4.2 rmind void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 222 1.2.4.2 rmind bus_size_t); 223 1.2.4.2 rmind void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 224 1.2.4.2 rmind bus_size_t); 225 1.2.4.2 rmind void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 226 1.2.4.2 rmind bus_size_t); 227 1.2.4.2 rmind void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 228 1.2.4.2 rmind bus_size_t); 229 1.2.4.2 rmind void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 230 1.2.4.2 rmind bus_size_t); 231 1.2.4.2 rmind void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 232 1.2.4.2 rmind bus_size_t); 233 1.2.4.2 rmind void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 234 1.2.4.2 rmind void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 235 1.2.4.2 rmind void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 236 1.2.4.2 rmind void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 237 1.2.4.2 rmind void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 238 1.2.4.2 rmind bus_size_t, bus_size_t); 239 1.2.4.2 rmind void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 240 1.2.4.2 rmind bus_size_t, bus_size_t); 241 1.2.4.2 rmind void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 242 1.2.4.2 rmind bus_size_t, bus_size_t); 243 1.2.4.2 rmind void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 244 1.2.4.2 rmind bus_size_t, bus_size_t); 245 1.2.4.2 rmind int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 246 1.2.4.2 rmind bus_dmamap_t *); 247 1.2.4.2 rmind void dino_dmamap_destroy(void *, bus_dmamap_t); 248 1.2.4.2 rmind int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, 249 1.2.4.2 rmind int); 250 1.2.4.2 rmind int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 251 1.2.4.2 rmind int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 252 1.2.4.2 rmind int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 253 1.2.4.2 rmind bus_size_t, int); 254 1.2.4.2 rmind void dino_dmamap_unload(void *, bus_dmamap_t); 255 1.2.4.2 rmind void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 256 1.2.4.2 rmind int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 257 1.2.4.2 rmind bus_dma_segment_t *, int, int *, int); 258 1.2.4.2 rmind void dino_dmamem_free(void *, bus_dma_segment_t *, int); 259 1.2.4.2 rmind int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int); 260 1.2.4.2 rmind void dino_dmamem_unmap(void *, void *, size_t); 261 1.2.4.2 rmind paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 262 1.2.4.2 rmind 263 1.2.4.2 rmind 264 1.2.4.2 rmind void 265 1.2.4.2 rmind dino_attach_hook(device_t parent, device_t self, 266 1.2.4.2 rmind struct pcibus_attach_args *pba) 267 1.2.4.2 rmind { 268 1.2.4.2 rmind struct dino_softc *sc = pba->pba_pc->_cookie; 269 1.2.4.2 rmind 270 1.2.4.2 rmind /* 271 1.2.4.2 rmind * The firmware enables only devices that are needed for booting. 272 1.2.4.2 rmind * So other devices will fail to map PCI MEM / IO when they attach. 273 1.2.4.2 rmind * Therefore we recursively walk all buses to simply enable everything. 274 1.2.4.2 rmind */ 275 1.2.4.2 rmind dino_enable_bus(sc, 0); 276 1.2.4.2 rmind } 277 1.2.4.2 rmind 278 1.2.4.2 rmind void 279 1.2.4.2 rmind dino_enable_bus(struct dino_softc *sc, int bus) 280 1.2.4.2 rmind { 281 1.2.4.2 rmind int func; 282 1.2.4.2 rmind int dev; 283 1.2.4.2 rmind pcitag_t tag; 284 1.2.4.2 rmind pcireg_t data; 285 1.2.4.2 rmind pcireg_t class; 286 1.2.4.2 rmind 287 1.2.4.2 rmind for (dev = 0; dev < 32; dev++) { 288 1.2.4.2 rmind tag = dino_make_tag(sc, bus, dev, 0); 289 1.2.4.2 rmind if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) { 290 1.2.4.2 rmind for (func = 0; func < 8; func++) { 291 1.2.4.2 rmind tag = dino_make_tag(sc, bus, dev, func); 292 1.2.4.2 rmind if (dino_conf_read(sc, tag, 0) != 0xffffffff) { 293 1.2.4.2 rmind data = dino_conf_read(sc, tag, 294 1.2.4.2 rmind PCI_COMMAND_STATUS_REG); 295 1.2.4.2 rmind dino_conf_write(sc, tag, 296 1.2.4.2 rmind PCI_COMMAND_STATUS_REG, 297 1.2.4.2 rmind PCI_COMMAND_IO_ENABLE | 298 1.2.4.2 rmind PCI_COMMAND_MEM_ENABLE | 299 1.2.4.2 rmind PCI_COMMAND_MASTER_ENABLE | data); 300 1.2.4.2 rmind } 301 1.2.4.2 rmind } 302 1.2.4.2 rmind class = dino_conf_read(sc, tag, PCI_CLASS_REG); 303 1.2.4.2 rmind if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 304 1.2.4.2 rmind PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI) 305 1.2.4.2 rmind dino_enable_bus(sc, bus + 1); 306 1.2.4.2 rmind } 307 1.2.4.2 rmind } 308 1.2.4.2 rmind } 309 1.2.4.2 rmind 310 1.2.4.2 rmind int 311 1.2.4.2 rmind dino_maxdevs(void *v, int bus) 312 1.2.4.2 rmind { 313 1.2.4.2 rmind return 32; 314 1.2.4.2 rmind } 315 1.2.4.2 rmind 316 1.2.4.2 rmind pcitag_t 317 1.2.4.2 rmind dino_make_tag(void *v, int bus, int dev, int func) 318 1.2.4.2 rmind { 319 1.2.4.2 rmind if (bus > 255 || dev > 31 || func > 7) 320 1.2.4.2 rmind panic("dino_make_tag: bad request"); 321 1.2.4.2 rmind 322 1.2.4.2 rmind return (bus << 16) | (dev << 11) | (func << 8); 323 1.2.4.2 rmind } 324 1.2.4.2 rmind 325 1.2.4.2 rmind void 326 1.2.4.2 rmind dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 327 1.2.4.2 rmind { 328 1.2.4.2 rmind *bus = (tag >> 16) & 0xff; 329 1.2.4.2 rmind *dev = (tag >> 11) & 0x1f; 330 1.2.4.2 rmind *func= (tag >> 8) & 0x07; 331 1.2.4.2 rmind } 332 1.2.4.2 rmind 333 1.2.4.2 rmind pcireg_t 334 1.2.4.2 rmind dino_conf_read(void *v, pcitag_t tag, int reg) 335 1.2.4.2 rmind { 336 1.2.4.2 rmind struct dino_softc *sc = v; 337 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 338 1.2.4.2 rmind pcireg_t data; 339 1.2.4.2 rmind uint32_t pamr; 340 1.2.4.2 rmind 341 1.2.4.2 rmind /* fix arbitration errata by disabling all pci devs on config read */ 342 1.2.4.2 rmind pamr = r->pamr; 343 1.2.4.2 rmind r->pamr = 0; 344 1.2.4.2 rmind 345 1.2.4.2 rmind r->pci_addr = tag | reg; 346 1.2.4.2 rmind data = r->pci_conf_data; 347 1.2.4.2 rmind 348 1.2.4.2 rmind /* restore arbitration */ 349 1.2.4.2 rmind r->pamr = pamr; 350 1.2.4.2 rmind 351 1.2.4.2 rmind return le32toh(data); 352 1.2.4.2 rmind } 353 1.2.4.2 rmind 354 1.2.4.2 rmind void 355 1.2.4.2 rmind dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 356 1.2.4.2 rmind { 357 1.2.4.2 rmind struct dino_softc *sc = v; 358 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 359 1.2.4.2 rmind uint32_t pamr; 360 1.2.4.2 rmind 361 1.2.4.2 rmind /* fix arbitration errata by disabling all pci devs on config read */ 362 1.2.4.2 rmind pamr = r->pamr; 363 1.2.4.2 rmind r->pamr = 0; 364 1.2.4.2 rmind 365 1.2.4.2 rmind r->pci_addr = tag | reg; 366 1.2.4.2 rmind r->pci_conf_data = htole32(data); 367 1.2.4.2 rmind 368 1.2.4.2 rmind /* fix coalescing config and io writes by interleaving w/ a read */ 369 1.2.4.2 rmind r->pci_addr = tag | PCI_ID_REG; 370 1.2.4.2 rmind (void)r->pci_conf_data; 371 1.2.4.2 rmind 372 1.2.4.2 rmind /* restore arbitration */ 373 1.2.4.2 rmind r->pamr = pamr; 374 1.2.4.2 rmind } 375 1.2.4.2 rmind 376 1.2.4.2 rmind int 377 1.2.4.2 rmind dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 378 1.2.4.2 rmind { 379 1.2.4.2 rmind int line = pa->pa_intrline; 380 1.2.4.2 rmind 381 1.2.4.2 rmind if (line == 0xff) 382 1.2.4.2 rmind return 1; 383 1.2.4.2 rmind 384 1.2.4.2 rmind *ihp = line; 385 1.2.4.2 rmind 386 1.2.4.2 rmind return 0; 387 1.2.4.2 rmind } 388 1.2.4.2 rmind 389 1.2.4.2 rmind const char * 390 1.2.4.2 rmind dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 391 1.2.4.2 rmind { 392 1.2.4.2 rmind snprintf(buf, len, "irq %ld", ih); 393 1.2.4.2 rmind return buf; 394 1.2.4.2 rmind } 395 1.2.4.2 rmind 396 1.2.4.2 rmind extern int cold; 397 1.2.4.2 rmind 398 1.2.4.2 rmind 399 1.2.4.2 rmind void * 400 1.2.4.2 rmind dino_intr_establish(void *v, pci_intr_handle_t ih, 401 1.2.4.2 rmind int pri, int (*handler)(void *), void *arg) 402 1.2.4.2 rmind { 403 1.2.4.2 rmind struct dino_softc *sc = v; 404 1.2.4.2 rmind 405 1.2.4.2 rmind return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih); 406 1.2.4.2 rmind } 407 1.2.4.2 rmind 408 1.2.4.2 rmind void 409 1.2.4.2 rmind dino_intr_disestablish(void *v, void *cookie) 410 1.2.4.2 rmind { 411 1.2.4.2 rmind /* XXX Implement me */ 412 1.2.4.2 rmind } 413 1.2.4.2 rmind 414 1.2.4.2 rmind 415 1.2.4.2 rmind #if NCARDBUS > 0 416 1.2.4.2 rmind void * 417 1.2.4.2 rmind dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io) 418 1.2.4.2 rmind { 419 1.2.4.2 rmind struct dino_softc *sc = pa->pa_pc->_cookie; 420 1.2.4.2 rmind struct extent *ex; 421 1.2.4.2 rmind bus_space_tag_t tag; 422 1.2.4.2 rmind bus_addr_t start; 423 1.2.4.2 rmind bus_size_t size; 424 1.2.4.2 rmind 425 1.2.4.2 rmind if (io) { 426 1.2.4.2 rmind ex = sc->sc_ioex; 427 1.2.4.2 rmind tag = pa->pa_iot; 428 1.2.4.2 rmind start = 0xa000; 429 1.2.4.2 rmind size = 0x1000; 430 1.2.4.2 rmind } else { 431 1.2.4.2 rmind ex = hppa_io_extent; 432 1.2.4.2 rmind tag = pa->pa_memt; 433 1.2.4.2 rmind start = ex->ex_start; /* XXX or 0xf0800000? */ 434 1.2.4.2 rmind size = DINO_MEM_CHUNK; 435 1.2.4.2 rmind } 436 1.2.4.2 rmind 437 1.2.4.2 rmind if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 438 1.2.4.2 rmind EX_NOBOUNDARY, EX_NOWAIT, &start)) 439 1.2.4.2 rmind return NULL; 440 1.2.4.2 rmind extent_free(ex, start, size, EX_NOWAIT); 441 1.2.4.2 rmind return rbus_new_root_share(tag, ex, start, size, start); 442 1.2.4.2 rmind } 443 1.2.4.2 rmind #endif 444 1.2.4.2 rmind 445 1.2.4.2 rmind int 446 1.2.4.2 rmind dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 447 1.2.4.2 rmind int flags, bus_space_handle_t *bshp) 448 1.2.4.2 rmind { 449 1.2.4.2 rmind struct dino_softc *sc = v; 450 1.2.4.2 rmind int error; 451 1.2.4.2 rmind 452 1.2.4.2 rmind if (!(flags & BUS_SPACE_MAP_NOEXTENT) && 453 1.2.4.2 rmind (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 454 1.2.4.2 rmind return error; 455 1.2.4.2 rmind 456 1.2.4.2 rmind if (bshp) 457 1.2.4.2 rmind *bshp = bpa; 458 1.2.4.2 rmind 459 1.2.4.2 rmind return 0; 460 1.2.4.2 rmind } 461 1.2.4.2 rmind 462 1.2.4.2 rmind int 463 1.2.4.2 rmind dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 464 1.2.4.2 rmind int flags, bus_space_handle_t *bshp) 465 1.2.4.2 rmind { 466 1.2.4.2 rmind struct dino_softc *sc = v; 467 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 468 1.2.4.2 rmind uint32_t reg; 469 1.2.4.2 rmind int error; 470 1.2.4.2 rmind 471 1.2.4.2 rmind reg = r->io_addr_en; 472 1.2.4.2 rmind reg |= 1 << ((bpa >> 23) & 0x1f); 473 1.2.4.2 rmind #ifdef DEBUG 474 1.2.4.2 rmind if (reg & 0x80000001) 475 1.2.4.2 rmind panic("mapping outside the mem extent range"); 476 1.2.4.2 rmind #endif 477 1.2.4.2 rmind if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) 478 1.2.4.2 rmind return error; 479 1.2.4.2 rmind ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; 480 1.2.4.2 rmind /* map into the upper bus space, if not yet mapped this 8M */ 481 1.2.4.2 rmind if (reg != r->io_addr_en) 482 1.2.4.2 rmind r->io_addr_en = reg; 483 1.2.4.2 rmind return 0; 484 1.2.4.2 rmind } 485 1.2.4.2 rmind 486 1.2.4.2 rmind int 487 1.2.4.2 rmind dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 488 1.2.4.2 rmind bus_size_t size, bus_space_handle_t *nbshp) 489 1.2.4.2 rmind { 490 1.2.4.2 rmind *nbshp = bsh + offset; 491 1.2.4.2 rmind return 0; 492 1.2.4.2 rmind } 493 1.2.4.2 rmind 494 1.2.4.2 rmind int 495 1.2.4.2 rmind dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 496 1.2.4.2 rmind bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 497 1.2.4.2 rmind bus_space_handle_t *bshp) 498 1.2.4.2 rmind { 499 1.2.4.2 rmind struct dino_softc *sc = v; 500 1.2.4.2 rmind struct extent *ex = sc->sc_ioex; 501 1.2.4.2 rmind bus_addr_t bpa; 502 1.2.4.2 rmind int error; 503 1.2.4.2 rmind 504 1.2.4.2 rmind if (rstart < ex->ex_start || rend > ex->ex_end) 505 1.2.4.2 rmind panic("dino_ioalloc: bad region start/end"); 506 1.2.4.2 rmind 507 1.2.4.2 rmind if ((error = extent_alloc_subregion(ex, rstart, rend, size, 508 1.2.4.2 rmind align, boundary, EX_NOWAIT, &bpa))) 509 1.2.4.2 rmind return error; 510 1.2.4.2 rmind 511 1.2.4.2 rmind if (addrp) 512 1.2.4.2 rmind *addrp = bpa; 513 1.2.4.2 rmind if (bshp) 514 1.2.4.2 rmind *bshp = bpa; 515 1.2.4.2 rmind 516 1.2.4.2 rmind return 0; 517 1.2.4.2 rmind } 518 1.2.4.2 rmind 519 1.2.4.2 rmind int 520 1.2.4.2 rmind dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 521 1.2.4.2 rmind bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 522 1.2.4.2 rmind bus_space_handle_t *bshp) 523 1.2.4.2 rmind { 524 1.2.4.2 rmind struct dino_softc *sc = v; 525 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 526 1.2.4.2 rmind uint32_t reg; 527 1.2.4.2 rmind int i, error; 528 1.2.4.2 rmind 529 1.2.4.2 rmind /* 530 1.2.4.2 rmind * Allow allocation only when PCI MEM is already mapped. 531 1.2.4.2 rmind * Needed to avoid allocation of I/O space used by devices that 532 1.2.4.2 rmind * have no driver in the current kernel. 533 1.2.4.2 rmind * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. 534 1.2.4.2 rmind */ 535 1.2.4.2 rmind reg = r->io_addr_en; 536 1.2.4.2 rmind if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) 537 1.2.4.2 rmind return -1; 538 1.2.4.2 rmind /* Find used PCI MEM and narrow allocateble region down to it. */ 539 1.2.4.2 rmind for (i = 1; i < 31; i++) 540 1.2.4.2 rmind if ((reg & 1 << i) != 0) { 541 1.2.4.2 rmind rstart = HPPA_IOSPACE | i << 23; 542 1.2.4.2 rmind rend = (HPPA_IOSPACE | (i + 1) << 23) - 1; 543 1.2.4.2 rmind break; 544 1.2.4.2 rmind } 545 1.2.4.2 rmind if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, 546 1.2.4.2 rmind boundary, flags, addrp, bshp))) 547 1.2.4.2 rmind return error; 548 1.2.4.2 rmind ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; 549 1.2.4.2 rmind return 0; 550 1.2.4.2 rmind } 551 1.2.4.2 rmind 552 1.2.4.2 rmind void 553 1.2.4.2 rmind dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 554 1.2.4.2 rmind { 555 1.2.4.2 rmind struct dino_softc *sc = v; 556 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 557 1.2.4.2 rmind 558 1.2.4.2 rmind if (bsh & HPPA_IOSPACE) { 559 1.2.4.2 rmind bus_space_unmap(sc->sc_bt, bsh, size); 560 1.2.4.2 rmind if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) 561 1.2.4.2 rmind /* Unmap the upper PCI MEM space. */ 562 1.2.4.2 rmind r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); 563 1.2.4.2 rmind } else { 564 1.2.4.2 rmind /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ 565 1.2.4.2 rmind if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) 566 1.2.4.2 rmind printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 567 1.2.4.2 rmind "dino_unmap: can't free region\n", bsh, size); 568 1.2.4.2 rmind } 569 1.2.4.2 rmind } 570 1.2.4.2 rmind 571 1.2.4.2 rmind void 572 1.2.4.2 rmind dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 573 1.2.4.2 rmind { 574 1.2.4.2 rmind /* should be enough */ 575 1.2.4.2 rmind dino_unmap(v, bh, size); 576 1.2.4.2 rmind } 577 1.2.4.2 rmind 578 1.2.4.2 rmind void 579 1.2.4.2 rmind dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 580 1.2.4.2 rmind { 581 1.2.4.2 rmind sync_caches(); 582 1.2.4.2 rmind } 583 1.2.4.2 rmind 584 1.2.4.2 rmind void* 585 1.2.4.2 rmind dino_vaddr(void *v, bus_space_handle_t h) 586 1.2.4.2 rmind { 587 1.2.4.2 rmind struct dino_softc *sc = v; 588 1.2.4.2 rmind 589 1.2.4.2 rmind return bus_space_vaddr(sc->sc_bt, h); 590 1.2.4.2 rmind } 591 1.2.4.2 rmind 592 1.2.4.2 rmind paddr_t 593 1.2.4.2 rmind dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 594 1.2.4.2 rmind { 595 1.2.4.2 rmind return -1; 596 1.2.4.2 rmind } 597 1.2.4.2 rmind 598 1.2.4.2 rmind uint8_t 599 1.2.4.2 rmind dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 600 1.2.4.2 rmind { 601 1.2.4.2 rmind h += o; 602 1.2.4.2 rmind if (h & HPPA_IOSPACE) 603 1.2.4.2 rmind return *(volatile uint8_t *)h; 604 1.2.4.2 rmind else { 605 1.2.4.2 rmind struct dino_softc *sc = v; 606 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 607 1.2.4.2 rmind 608 1.2.4.2 rmind r->pci_addr = h; 609 1.2.4.2 rmind return *((volatile uint8_t *)&r->pci_io_data + (h & 3)); 610 1.2.4.2 rmind } 611 1.2.4.2 rmind } 612 1.2.4.2 rmind 613 1.2.4.2 rmind uint16_t 614 1.2.4.2 rmind dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 615 1.2.4.2 rmind { 616 1.2.4.2 rmind volatile uint16_t *p; 617 1.2.4.2 rmind 618 1.2.4.2 rmind h += o; 619 1.2.4.2 rmind if (h & HPPA_IOSPACE) 620 1.2.4.2 rmind p = (volatile uint16_t *)h; 621 1.2.4.2 rmind else { 622 1.2.4.2 rmind struct dino_softc *sc = v; 623 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 624 1.2.4.2 rmind 625 1.2.4.2 rmind r->pci_addr = h; 626 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 627 1.2.4.2 rmind if (h & 2) 628 1.2.4.2 rmind p++; 629 1.2.4.2 rmind } 630 1.2.4.2 rmind return le16toh(*p); 631 1.2.4.2 rmind } 632 1.2.4.2 rmind 633 1.2.4.2 rmind uint32_t 634 1.2.4.2 rmind dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 635 1.2.4.2 rmind { 636 1.2.4.2 rmind uint32_t data; 637 1.2.4.2 rmind 638 1.2.4.2 rmind h += o; 639 1.2.4.2 rmind if (h & HPPA_IOSPACE) 640 1.2.4.2 rmind data = *(volatile uint32_t *)h; 641 1.2.4.2 rmind else { 642 1.2.4.2 rmind struct dino_softc *sc = v; 643 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 644 1.2.4.2 rmind 645 1.2.4.2 rmind r->pci_addr = h; 646 1.2.4.2 rmind data = r->pci_io_data; 647 1.2.4.2 rmind } 648 1.2.4.2 rmind 649 1.2.4.2 rmind return le32toh(data); 650 1.2.4.2 rmind } 651 1.2.4.2 rmind 652 1.2.4.2 rmind uint64_t 653 1.2.4.2 rmind dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 654 1.2.4.2 rmind { 655 1.2.4.2 rmind uint64_t data; 656 1.2.4.2 rmind 657 1.2.4.2 rmind h += o; 658 1.2.4.2 rmind if (h & HPPA_IOSPACE) 659 1.2.4.2 rmind data = *(volatile uint64_t *)h; 660 1.2.4.2 rmind else 661 1.2.4.2 rmind panic("dino_r8: not implemented"); 662 1.2.4.2 rmind 663 1.2.4.2 rmind return le64toh(data); 664 1.2.4.2 rmind } 665 1.2.4.2 rmind 666 1.2.4.2 rmind void 667 1.2.4.2 rmind dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv) 668 1.2.4.2 rmind { 669 1.2.4.2 rmind h += o; 670 1.2.4.2 rmind if (h & HPPA_IOSPACE) 671 1.2.4.2 rmind *(volatile uint8_t *)h = vv; 672 1.2.4.2 rmind else { 673 1.2.4.2 rmind struct dino_softc *sc = v; 674 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 675 1.2.4.2 rmind 676 1.2.4.2 rmind r->pci_addr = h; 677 1.2.4.2 rmind *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv; 678 1.2.4.2 rmind } 679 1.2.4.2 rmind } 680 1.2.4.2 rmind 681 1.2.4.2 rmind void 682 1.2.4.2 rmind dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 683 1.2.4.2 rmind { 684 1.2.4.2 rmind volatile uint16_t *p; 685 1.2.4.2 rmind 686 1.2.4.2 rmind h += o; 687 1.2.4.2 rmind if (h & HPPA_IOSPACE) 688 1.2.4.2 rmind p = (volatile uint16_t *)h; 689 1.2.4.2 rmind else { 690 1.2.4.2 rmind struct dino_softc *sc = v; 691 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 692 1.2.4.2 rmind 693 1.2.4.2 rmind r->pci_addr = h; 694 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 695 1.2.4.2 rmind if (h & 2) 696 1.2.4.2 rmind p++; 697 1.2.4.2 rmind } 698 1.2.4.2 rmind 699 1.2.4.2 rmind *p = htole16(vv); 700 1.2.4.2 rmind } 701 1.2.4.2 rmind 702 1.2.4.2 rmind void 703 1.2.4.2 rmind dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 704 1.2.4.2 rmind { 705 1.2.4.2 rmind h += o; 706 1.2.4.2 rmind vv = htole32(vv); 707 1.2.4.2 rmind if (h & HPPA_IOSPACE) 708 1.2.4.2 rmind *(volatile uint32_t *)h = vv; 709 1.2.4.2 rmind else { 710 1.2.4.2 rmind struct dino_softc *sc = v; 711 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 712 1.2.4.2 rmind 713 1.2.4.2 rmind r->pci_addr = h; 714 1.2.4.2 rmind r->pci_io_data = vv; 715 1.2.4.2 rmind } 716 1.2.4.2 rmind } 717 1.2.4.2 rmind 718 1.2.4.2 rmind void 719 1.2.4.2 rmind dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 720 1.2.4.2 rmind { 721 1.2.4.2 rmind h += o; 722 1.2.4.2 rmind if (h & HPPA_IOSPACE) 723 1.2.4.2 rmind *(volatile uint64_t *)h = htole64(vv); 724 1.2.4.2 rmind else 725 1.2.4.2 rmind panic("dino_w8: not implemented"); 726 1.2.4.2 rmind } 727 1.2.4.2 rmind 728 1.2.4.2 rmind 729 1.2.4.2 rmind void 730 1.2.4.2 rmind dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 731 1.2.4.2 rmind { 732 1.2.4.2 rmind volatile uint8_t *p; 733 1.2.4.2 rmind 734 1.2.4.2 rmind h += o; 735 1.2.4.2 rmind if (h & HPPA_IOSPACE) 736 1.2.4.2 rmind p = (volatile uint8_t *)h; 737 1.2.4.2 rmind else { 738 1.2.4.2 rmind struct dino_softc *sc = v; 739 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 740 1.2.4.2 rmind 741 1.2.4.2 rmind r->pci_addr = h; 742 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 743 1.2.4.2 rmind } 744 1.2.4.2 rmind 745 1.2.4.2 rmind while (c--) 746 1.2.4.2 rmind *a++ = *p; 747 1.2.4.2 rmind } 748 1.2.4.2 rmind 749 1.2.4.2 rmind void 750 1.2.4.2 rmind dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 751 1.2.4.2 rmind { 752 1.2.4.2 rmind volatile uint16_t *p; 753 1.2.4.2 rmind 754 1.2.4.2 rmind h += o; 755 1.2.4.2 rmind if (h & HPPA_IOSPACE) 756 1.2.4.2 rmind p = (volatile uint16_t *)h; 757 1.2.4.2 rmind else { 758 1.2.4.2 rmind struct dino_softc *sc = v; 759 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 760 1.2.4.2 rmind 761 1.2.4.2 rmind r->pci_addr = h; 762 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 763 1.2.4.2 rmind if (h & 2) 764 1.2.4.2 rmind p++; 765 1.2.4.2 rmind } 766 1.2.4.2 rmind 767 1.2.4.2 rmind while (c--) 768 1.2.4.2 rmind *a++ = le16toh(*p); 769 1.2.4.2 rmind } 770 1.2.4.2 rmind 771 1.2.4.2 rmind void 772 1.2.4.2 rmind dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 773 1.2.4.2 rmind { 774 1.2.4.2 rmind volatile uint32_t *p; 775 1.2.4.2 rmind 776 1.2.4.2 rmind h += o; 777 1.2.4.2 rmind if (h & HPPA_IOSPACE) 778 1.2.4.2 rmind p = (volatile uint32_t *)h; 779 1.2.4.2 rmind else { 780 1.2.4.2 rmind struct dino_softc *sc = v; 781 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 782 1.2.4.2 rmind 783 1.2.4.2 rmind r->pci_addr = h; 784 1.2.4.2 rmind p = (volatile uint32_t *)&r->pci_io_data; 785 1.2.4.2 rmind } 786 1.2.4.2 rmind 787 1.2.4.2 rmind while (c--) 788 1.2.4.2 rmind *a++ = le32toh(*p); 789 1.2.4.2 rmind } 790 1.2.4.2 rmind 791 1.2.4.2 rmind void 792 1.2.4.2 rmind dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 793 1.2.4.2 rmind { 794 1.2.4.2 rmind panic("dino_rm_8: not implemented"); 795 1.2.4.2 rmind } 796 1.2.4.2 rmind 797 1.2.4.2 rmind void 798 1.2.4.2 rmind dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 799 1.2.4.2 rmind { 800 1.2.4.2 rmind volatile uint8_t *p; 801 1.2.4.2 rmind 802 1.2.4.2 rmind h += o; 803 1.2.4.2 rmind if (h & HPPA_IOSPACE) 804 1.2.4.2 rmind p = (volatile uint8_t *)h; 805 1.2.4.2 rmind else { 806 1.2.4.2 rmind struct dino_softc *sc = v; 807 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 808 1.2.4.2 rmind 809 1.2.4.2 rmind r->pci_addr = h; 810 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 811 1.2.4.2 rmind } 812 1.2.4.2 rmind 813 1.2.4.2 rmind while (c--) 814 1.2.4.2 rmind *p = *a++; 815 1.2.4.2 rmind } 816 1.2.4.2 rmind 817 1.2.4.2 rmind void 818 1.2.4.2 rmind dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 819 1.2.4.2 rmind { 820 1.2.4.2 rmind volatile uint16_t *p; 821 1.2.4.2 rmind 822 1.2.4.2 rmind h += o; 823 1.2.4.2 rmind if (h & HPPA_IOSPACE) 824 1.2.4.2 rmind p = (volatile uint16_t *)h; 825 1.2.4.2 rmind else { 826 1.2.4.2 rmind struct dino_softc *sc = v; 827 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 828 1.2.4.2 rmind 829 1.2.4.2 rmind r->pci_addr = h; 830 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 831 1.2.4.2 rmind if (h & 2) 832 1.2.4.2 rmind p++; 833 1.2.4.2 rmind } 834 1.2.4.2 rmind 835 1.2.4.2 rmind while (c--) 836 1.2.4.2 rmind *p = htole16(*a++); 837 1.2.4.2 rmind } 838 1.2.4.2 rmind 839 1.2.4.2 rmind void 840 1.2.4.2 rmind dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 841 1.2.4.2 rmind { 842 1.2.4.2 rmind volatile uint32_t *p; 843 1.2.4.2 rmind 844 1.2.4.2 rmind h += o; 845 1.2.4.2 rmind if (h & HPPA_IOSPACE) 846 1.2.4.2 rmind p = (volatile uint32_t *)h; 847 1.2.4.2 rmind else { 848 1.2.4.2 rmind struct dino_softc *sc = v; 849 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 850 1.2.4.2 rmind 851 1.2.4.2 rmind r->pci_addr = h; 852 1.2.4.2 rmind p = (volatile uint32_t *)&r->pci_io_data; 853 1.2.4.2 rmind } 854 1.2.4.2 rmind 855 1.2.4.2 rmind while (c--) 856 1.2.4.2 rmind *p = htole32(*a++); 857 1.2.4.2 rmind } 858 1.2.4.2 rmind 859 1.2.4.2 rmind void 860 1.2.4.2 rmind dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 861 1.2.4.2 rmind { 862 1.2.4.2 rmind panic("dino_wm_8: not implemented"); 863 1.2.4.2 rmind } 864 1.2.4.2 rmind 865 1.2.4.2 rmind void 866 1.2.4.2 rmind dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 867 1.2.4.2 rmind { 868 1.2.4.2 rmind volatile uint8_t *p; 869 1.2.4.2 rmind 870 1.2.4.2 rmind h += o; 871 1.2.4.2 rmind if (h & HPPA_IOSPACE) 872 1.2.4.2 rmind p = (volatile uint8_t *)h; 873 1.2.4.2 rmind else { 874 1.2.4.2 rmind struct dino_softc *sc = v; 875 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 876 1.2.4.2 rmind 877 1.2.4.2 rmind r->pci_addr = h; 878 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 879 1.2.4.2 rmind } 880 1.2.4.2 rmind 881 1.2.4.2 rmind while (c--) 882 1.2.4.2 rmind *p = vv; 883 1.2.4.2 rmind } 884 1.2.4.2 rmind 885 1.2.4.2 rmind void 886 1.2.4.2 rmind dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 887 1.2.4.2 rmind { 888 1.2.4.2 rmind volatile uint16_t *p; 889 1.2.4.2 rmind 890 1.2.4.2 rmind h += o; 891 1.2.4.2 rmind if (h & HPPA_IOSPACE) 892 1.2.4.2 rmind p = (volatile uint16_t *)h; 893 1.2.4.2 rmind else { 894 1.2.4.2 rmind struct dino_softc *sc = v; 895 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 896 1.2.4.2 rmind 897 1.2.4.2 rmind r->pci_addr = h; 898 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 899 1.2.4.2 rmind if (h & 2) 900 1.2.4.2 rmind p++; 901 1.2.4.2 rmind } 902 1.2.4.2 rmind 903 1.2.4.2 rmind while (c--) 904 1.2.4.2 rmind *p = htole16(vv); 905 1.2.4.2 rmind } 906 1.2.4.2 rmind 907 1.2.4.2 rmind void 908 1.2.4.2 rmind dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 909 1.2.4.2 rmind { 910 1.2.4.2 rmind volatile uint32_t *p; 911 1.2.4.2 rmind 912 1.2.4.2 rmind h += o; 913 1.2.4.2 rmind if (h & HPPA_IOSPACE) 914 1.2.4.2 rmind p = (volatile uint32_t *)h; 915 1.2.4.2 rmind else { 916 1.2.4.2 rmind struct dino_softc *sc = v; 917 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 918 1.2.4.2 rmind 919 1.2.4.2 rmind r->pci_addr = h; 920 1.2.4.2 rmind p = (volatile uint32_t *)&r->pci_io_data; 921 1.2.4.2 rmind } 922 1.2.4.2 rmind 923 1.2.4.2 rmind while (c--) 924 1.2.4.2 rmind *p = htole32(vv); 925 1.2.4.2 rmind } 926 1.2.4.2 rmind 927 1.2.4.2 rmind void 928 1.2.4.2 rmind dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 929 1.2.4.2 rmind { 930 1.2.4.2 rmind panic("dino_sm_8: not implemented"); 931 1.2.4.2 rmind } 932 1.2.4.2 rmind 933 1.2.4.2 rmind void 934 1.2.4.2 rmind dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 935 1.2.4.2 rmind uint16_t *a, bus_size_t c) 936 1.2.4.2 rmind { 937 1.2.4.2 rmind volatile uint16_t *p; 938 1.2.4.2 rmind 939 1.2.4.2 rmind h += o; 940 1.2.4.2 rmind if (h & HPPA_IOSPACE) 941 1.2.4.2 rmind p = (volatile uint16_t *)h; 942 1.2.4.2 rmind else { 943 1.2.4.2 rmind struct dino_softc *sc = v; 944 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 945 1.2.4.2 rmind 946 1.2.4.2 rmind r->pci_addr = h; 947 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 948 1.2.4.2 rmind if (h & 2) 949 1.2.4.2 rmind p++; 950 1.2.4.2 rmind } 951 1.2.4.2 rmind 952 1.2.4.2 rmind while (c--) 953 1.2.4.2 rmind *a++ = *p; 954 1.2.4.2 rmind } 955 1.2.4.2 rmind 956 1.2.4.2 rmind void 957 1.2.4.2 rmind dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 958 1.2.4.2 rmind uint32_t *a, bus_size_t c) 959 1.2.4.2 rmind { 960 1.2.4.2 rmind volatile uint32_t *p; 961 1.2.4.2 rmind 962 1.2.4.2 rmind h += o; 963 1.2.4.2 rmind if (h & HPPA_IOSPACE) 964 1.2.4.2 rmind p = (volatile uint32_t *)h; 965 1.2.4.2 rmind else { 966 1.2.4.2 rmind struct dino_softc *sc = v; 967 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 968 1.2.4.2 rmind 969 1.2.4.2 rmind r->pci_addr = h; 970 1.2.4.2 rmind p = (volatile uint32_t *)&r->pci_io_data; 971 1.2.4.2 rmind } 972 1.2.4.2 rmind 973 1.2.4.2 rmind while (c--) 974 1.2.4.2 rmind *a++ = *p; 975 1.2.4.2 rmind } 976 1.2.4.2 rmind 977 1.2.4.2 rmind void 978 1.2.4.2 rmind dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 979 1.2.4.2 rmind uint64_t *a, bus_size_t c) 980 1.2.4.2 rmind { 981 1.2.4.2 rmind panic("dino_rrm_8: not implemented"); 982 1.2.4.2 rmind } 983 1.2.4.2 rmind 984 1.2.4.2 rmind void 985 1.2.4.2 rmind dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 986 1.2.4.2 rmind const uint16_t *a, bus_size_t c) 987 1.2.4.2 rmind { 988 1.2.4.2 rmind volatile uint16_t *p; 989 1.2.4.2 rmind 990 1.2.4.2 rmind h += o; 991 1.2.4.2 rmind if (h & HPPA_IOSPACE) 992 1.2.4.2 rmind p = (volatile uint16_t *)h; 993 1.2.4.2 rmind else { 994 1.2.4.2 rmind struct dino_softc *sc = v; 995 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 996 1.2.4.2 rmind 997 1.2.4.2 rmind r->pci_addr = h; 998 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 999 1.2.4.2 rmind if (h & 2) 1000 1.2.4.2 rmind p++; 1001 1.2.4.2 rmind } 1002 1.2.4.2 rmind 1003 1.2.4.2 rmind while (c--) 1004 1.2.4.2 rmind *p = *a++; 1005 1.2.4.2 rmind } 1006 1.2.4.2 rmind 1007 1.2.4.2 rmind void 1008 1.2.4.2 rmind dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1009 1.2.4.2 rmind const uint32_t *a, bus_size_t c) 1010 1.2.4.2 rmind { 1011 1.2.4.2 rmind volatile uint32_t *p; 1012 1.2.4.2 rmind 1013 1.2.4.2 rmind h += o; 1014 1.2.4.2 rmind if (h & HPPA_IOSPACE) 1015 1.2.4.2 rmind p = (volatile uint32_t *)h; 1016 1.2.4.2 rmind else { 1017 1.2.4.2 rmind struct dino_softc *sc = v; 1018 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1019 1.2.4.2 rmind 1020 1.2.4.2 rmind r->pci_addr = h; 1021 1.2.4.2 rmind p = (volatile uint32_t *)&r->pci_io_data; 1022 1.2.4.2 rmind } 1023 1.2.4.2 rmind 1024 1.2.4.2 rmind while (c--) 1025 1.2.4.2 rmind *p = *a++; 1026 1.2.4.2 rmind } 1027 1.2.4.2 rmind 1028 1.2.4.2 rmind void 1029 1.2.4.2 rmind dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1030 1.2.4.2 rmind const uint64_t *a, bus_size_t c) 1031 1.2.4.2 rmind { 1032 1.2.4.2 rmind panic("dino_wrm_8: not implemented"); 1033 1.2.4.2 rmind } 1034 1.2.4.2 rmind 1035 1.2.4.2 rmind void 1036 1.2.4.2 rmind dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 1037 1.2.4.2 rmind { 1038 1.2.4.2 rmind volatile uint8_t *p; 1039 1.2.4.2 rmind 1040 1.2.4.2 rmind h += o; 1041 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1042 1.2.4.2 rmind p = (volatile uint8_t *)h; 1043 1.2.4.2 rmind while (c--) 1044 1.2.4.2 rmind *a++ = *p++; 1045 1.2.4.2 rmind } else { 1046 1.2.4.2 rmind struct dino_softc *sc = v; 1047 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1048 1.2.4.2 rmind 1049 1.2.4.2 rmind for (; c--; h++) { 1050 1.2.4.2 rmind r->pci_addr = h; 1051 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1052 1.2.4.2 rmind *a++ = *p; 1053 1.2.4.2 rmind } 1054 1.2.4.2 rmind } 1055 1.2.4.2 rmind } 1056 1.2.4.2 rmind 1057 1.2.4.2 rmind void 1058 1.2.4.2 rmind dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 1059 1.2.4.2 rmind { 1060 1.2.4.2 rmind volatile uint16_t *p, data; 1061 1.2.4.2 rmind 1062 1.2.4.2 rmind h += o; 1063 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1064 1.2.4.2 rmind p = (volatile uint16_t *)h; 1065 1.2.4.2 rmind while (c--) { 1066 1.2.4.2 rmind data = *p++; 1067 1.2.4.2 rmind *a++ = le16toh(data); 1068 1.2.4.2 rmind } 1069 1.2.4.2 rmind } else { 1070 1.2.4.2 rmind struct dino_softc *sc = v; 1071 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1072 1.2.4.2 rmind 1073 1.2.4.2 rmind for (; c--; h += 2) { 1074 1.2.4.2 rmind r->pci_addr = h; 1075 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 1076 1.2.4.2 rmind if (h & 2) 1077 1.2.4.2 rmind p++; 1078 1.2.4.2 rmind data = *p; 1079 1.2.4.2 rmind *a++ = le16toh(data); 1080 1.2.4.2 rmind } 1081 1.2.4.2 rmind } 1082 1.2.4.2 rmind } 1083 1.2.4.2 rmind 1084 1.2.4.2 rmind void 1085 1.2.4.2 rmind dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 1086 1.2.4.2 rmind { 1087 1.2.4.2 rmind volatile uint32_t *p, data; 1088 1.2.4.2 rmind 1089 1.2.4.2 rmind h += o; 1090 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1091 1.2.4.2 rmind p = (volatile uint32_t *)h; 1092 1.2.4.2 rmind while (c--) { 1093 1.2.4.2 rmind data = *p++; 1094 1.2.4.2 rmind *a++ = le32toh(data); 1095 1.2.4.2 rmind } 1096 1.2.4.2 rmind } else { 1097 1.2.4.2 rmind struct dino_softc *sc = v; 1098 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1099 1.2.4.2 rmind 1100 1.2.4.2 rmind for (; c--; h += 4) { 1101 1.2.4.2 rmind r->pci_addr = h; 1102 1.2.4.2 rmind data = r->pci_io_data; 1103 1.2.4.2 rmind *a++ = le32toh(data); 1104 1.2.4.2 rmind } 1105 1.2.4.2 rmind } 1106 1.2.4.2 rmind } 1107 1.2.4.2 rmind 1108 1.2.4.2 rmind void 1109 1.2.4.2 rmind dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 1110 1.2.4.2 rmind { 1111 1.2.4.2 rmind panic("dino_rr_8: not implemented"); 1112 1.2.4.2 rmind } 1113 1.2.4.2 rmind 1114 1.2.4.2 rmind void 1115 1.2.4.2 rmind dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 1116 1.2.4.2 rmind { 1117 1.2.4.2 rmind volatile uint8_t *p; 1118 1.2.4.2 rmind 1119 1.2.4.2 rmind h += o; 1120 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1121 1.2.4.2 rmind p = (volatile uint8_t *)h; 1122 1.2.4.2 rmind while (c--) 1123 1.2.4.2 rmind *p++ = *a++; 1124 1.2.4.2 rmind } else { 1125 1.2.4.2 rmind struct dino_softc *sc = v; 1126 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1127 1.2.4.2 rmind 1128 1.2.4.2 rmind for (; c--; h++) { 1129 1.2.4.2 rmind r->pci_addr = h; 1130 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1131 1.2.4.2 rmind *p = *a++; 1132 1.2.4.2 rmind } 1133 1.2.4.2 rmind } 1134 1.2.4.2 rmind } 1135 1.2.4.2 rmind 1136 1.2.4.2 rmind void 1137 1.2.4.2 rmind dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 1138 1.2.4.2 rmind { 1139 1.2.4.2 rmind volatile uint16_t *p, data; 1140 1.2.4.2 rmind 1141 1.2.4.2 rmind h += o; 1142 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1143 1.2.4.2 rmind p = (volatile uint16_t *)h; 1144 1.2.4.2 rmind while (c--) { 1145 1.2.4.2 rmind data = *a++; 1146 1.2.4.2 rmind *p++ = htole16(data); 1147 1.2.4.2 rmind } 1148 1.2.4.2 rmind } else { 1149 1.2.4.2 rmind struct dino_softc *sc = v; 1150 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1151 1.2.4.2 rmind 1152 1.2.4.2 rmind for (; c--; h += 2) { 1153 1.2.4.2 rmind r->pci_addr = h; 1154 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 1155 1.2.4.2 rmind if (h & 2) 1156 1.2.4.2 rmind p++; 1157 1.2.4.2 rmind data = *a++; 1158 1.2.4.2 rmind *p = htole16(data); 1159 1.2.4.2 rmind } 1160 1.2.4.2 rmind } 1161 1.2.4.2 rmind } 1162 1.2.4.2 rmind 1163 1.2.4.2 rmind void 1164 1.2.4.2 rmind dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 1165 1.2.4.2 rmind { 1166 1.2.4.2 rmind volatile uint32_t *p, data; 1167 1.2.4.2 rmind 1168 1.2.4.2 rmind h += o; 1169 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1170 1.2.4.2 rmind p = (volatile uint32_t *)h; 1171 1.2.4.2 rmind while (c--) { 1172 1.2.4.2 rmind data = *a++; 1173 1.2.4.2 rmind *p++ = htole32(data); 1174 1.2.4.2 rmind } 1175 1.2.4.2 rmind } else { 1176 1.2.4.2 rmind struct dino_softc *sc = v; 1177 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1178 1.2.4.2 rmind 1179 1.2.4.2 rmind for (; c--; h += 4) { 1180 1.2.4.2 rmind r->pci_addr = h; 1181 1.2.4.2 rmind data = *a++; 1182 1.2.4.2 rmind r->pci_io_data = htole32(data); 1183 1.2.4.2 rmind } 1184 1.2.4.2 rmind } 1185 1.2.4.2 rmind } 1186 1.2.4.2 rmind 1187 1.2.4.2 rmind void 1188 1.2.4.2 rmind dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 1189 1.2.4.2 rmind { 1190 1.2.4.2 rmind panic("dino_wr_8: not implemented"); 1191 1.2.4.2 rmind } 1192 1.2.4.2 rmind 1193 1.2.4.2 rmind void 1194 1.2.4.2 rmind dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1195 1.2.4.2 rmind uint16_t *a, bus_size_t c) 1196 1.2.4.2 rmind { 1197 1.2.4.2 rmind volatile uint16_t *p; 1198 1.2.4.2 rmind 1199 1.2.4.2 rmind h += o; 1200 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1201 1.2.4.2 rmind p = (volatile uint16_t *)h; 1202 1.2.4.2 rmind while (c--) 1203 1.2.4.2 rmind *a++ = *p++; 1204 1.2.4.2 rmind } else { 1205 1.2.4.2 rmind struct dino_softc *sc = v; 1206 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1207 1.2.4.2 rmind 1208 1.2.4.2 rmind for (; c--; h += 2) { 1209 1.2.4.2 rmind r->pci_addr = h; 1210 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 1211 1.2.4.2 rmind if (h & 2) 1212 1.2.4.2 rmind p++; 1213 1.2.4.2 rmind *a++ = *p; 1214 1.2.4.2 rmind } 1215 1.2.4.2 rmind } 1216 1.2.4.2 rmind } 1217 1.2.4.2 rmind 1218 1.2.4.2 rmind void 1219 1.2.4.2 rmind dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1220 1.2.4.2 rmind uint32_t *a, bus_size_t c) 1221 1.2.4.2 rmind { 1222 1.2.4.2 rmind volatile uint32_t *p; 1223 1.2.4.2 rmind 1224 1.2.4.2 rmind h += o; 1225 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1226 1.2.4.2 rmind p = (volatile uint32_t *)h; 1227 1.2.4.2 rmind while (c--) 1228 1.2.4.2 rmind *a++ = *p++; 1229 1.2.4.2 rmind } else { 1230 1.2.4.2 rmind struct dino_softc *sc = v; 1231 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1232 1.2.4.2 rmind 1233 1.2.4.2 rmind for (; c--; h += 4) { 1234 1.2.4.2 rmind r->pci_addr = h; 1235 1.2.4.2 rmind *a++ = r->pci_io_data; 1236 1.2.4.2 rmind } 1237 1.2.4.2 rmind } 1238 1.2.4.2 rmind } 1239 1.2.4.2 rmind 1240 1.2.4.2 rmind void 1241 1.2.4.2 rmind dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1242 1.2.4.2 rmind uint64_t *a, bus_size_t c) 1243 1.2.4.2 rmind { 1244 1.2.4.2 rmind panic("dino_rrr_8: not implemented"); 1245 1.2.4.2 rmind } 1246 1.2.4.2 rmind 1247 1.2.4.2 rmind void 1248 1.2.4.2 rmind dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1249 1.2.4.2 rmind const uint16_t *a, bus_size_t c) 1250 1.2.4.2 rmind { 1251 1.2.4.2 rmind volatile uint16_t *p; 1252 1.2.4.2 rmind 1253 1.2.4.2 rmind h += o; 1254 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1255 1.2.4.2 rmind p = (volatile uint16_t *)h; 1256 1.2.4.2 rmind while (c--) 1257 1.2.4.2 rmind *p++ = *a++; 1258 1.2.4.2 rmind } else { 1259 1.2.4.2 rmind struct dino_softc *sc = v; 1260 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1261 1.2.4.2 rmind 1262 1.2.4.2 rmind for (; c--; h += 2) { 1263 1.2.4.2 rmind r->pci_addr = h; 1264 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 1265 1.2.4.2 rmind if (h & 2) 1266 1.2.4.2 rmind p++; 1267 1.2.4.2 rmind *p = *a++; 1268 1.2.4.2 rmind } 1269 1.2.4.2 rmind } 1270 1.2.4.2 rmind } 1271 1.2.4.2 rmind 1272 1.2.4.2 rmind void 1273 1.2.4.2 rmind dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1274 1.2.4.2 rmind const uint32_t *a, bus_size_t c) 1275 1.2.4.2 rmind { 1276 1.2.4.2 rmind volatile uint32_t *p; 1277 1.2.4.2 rmind 1278 1.2.4.2 rmind c /= 4; 1279 1.2.4.2 rmind h += o; 1280 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1281 1.2.4.2 rmind p = (volatile uint32_t *)h; 1282 1.2.4.2 rmind while (c--) 1283 1.2.4.2 rmind *p++ = *a++; 1284 1.2.4.2 rmind } else { 1285 1.2.4.2 rmind struct dino_softc *sc = v; 1286 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1287 1.2.4.2 rmind 1288 1.2.4.2 rmind for (; c--; h += 4) { 1289 1.2.4.2 rmind r->pci_addr = h; 1290 1.2.4.2 rmind r->pci_io_data = *a++; 1291 1.2.4.2 rmind } 1292 1.2.4.2 rmind } 1293 1.2.4.2 rmind } 1294 1.2.4.2 rmind 1295 1.2.4.2 rmind void 1296 1.2.4.2 rmind dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1297 1.2.4.2 rmind const uint64_t *a, bus_size_t c) 1298 1.2.4.2 rmind { 1299 1.2.4.2 rmind panic("dino_wrr_8: not implemented"); 1300 1.2.4.2 rmind } 1301 1.2.4.2 rmind 1302 1.2.4.2 rmind void 1303 1.2.4.2 rmind dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1304 1.2.4.2 rmind { 1305 1.2.4.2 rmind volatile uint8_t *p; 1306 1.2.4.2 rmind 1307 1.2.4.2 rmind h += o; 1308 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1309 1.2.4.2 rmind p = (volatile uint8_t *)h; 1310 1.2.4.2 rmind while (c--) 1311 1.2.4.2 rmind *p++ = vv; 1312 1.2.4.2 rmind } else { 1313 1.2.4.2 rmind struct dino_softc *sc = v; 1314 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1315 1.2.4.2 rmind 1316 1.2.4.2 rmind for (; c--; h++) { 1317 1.2.4.2 rmind r->pci_addr = h; 1318 1.2.4.2 rmind p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1319 1.2.4.2 rmind *p = vv; 1320 1.2.4.2 rmind } 1321 1.2.4.2 rmind } 1322 1.2.4.2 rmind } 1323 1.2.4.2 rmind 1324 1.2.4.2 rmind void 1325 1.2.4.2 rmind dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1326 1.2.4.2 rmind { 1327 1.2.4.2 rmind volatile uint16_t *p; 1328 1.2.4.2 rmind 1329 1.2.4.2 rmind h += o; 1330 1.2.4.2 rmind vv = htole16(vv); 1331 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1332 1.2.4.2 rmind p = (volatile uint16_t *)h; 1333 1.2.4.2 rmind while (c--) 1334 1.2.4.2 rmind *p++ = vv; 1335 1.2.4.2 rmind } else { 1336 1.2.4.2 rmind struct dino_softc *sc = v; 1337 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1338 1.2.4.2 rmind 1339 1.2.4.2 rmind for (; c--; h += 2) { 1340 1.2.4.2 rmind r->pci_addr = h; 1341 1.2.4.2 rmind p = (volatile uint16_t *)&r->pci_io_data; 1342 1.2.4.2 rmind if (h & 2) 1343 1.2.4.2 rmind p++; 1344 1.2.4.2 rmind *p = vv; 1345 1.2.4.2 rmind } 1346 1.2.4.2 rmind } 1347 1.2.4.2 rmind } 1348 1.2.4.2 rmind 1349 1.2.4.2 rmind void 1350 1.2.4.2 rmind dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1351 1.2.4.2 rmind { 1352 1.2.4.2 rmind volatile uint32_t *p; 1353 1.2.4.2 rmind 1354 1.2.4.2 rmind h += o; 1355 1.2.4.2 rmind vv = htole32(vv); 1356 1.2.4.2 rmind if (h & HPPA_IOSPACE) { 1357 1.2.4.2 rmind p = (volatile uint32_t *)h; 1358 1.2.4.2 rmind while (c--) 1359 1.2.4.2 rmind *p++ = vv; 1360 1.2.4.2 rmind } else { 1361 1.2.4.2 rmind struct dino_softc *sc = v; 1362 1.2.4.2 rmind volatile struct dino_regs *r = sc->sc_regs; 1363 1.2.4.2 rmind 1364 1.2.4.2 rmind for (; c--; h += 4) { 1365 1.2.4.2 rmind r->pci_addr = h; 1366 1.2.4.2 rmind r->pci_io_data = vv; 1367 1.2.4.2 rmind } 1368 1.2.4.2 rmind } 1369 1.2.4.2 rmind } 1370 1.2.4.2 rmind 1371 1.2.4.2 rmind void 1372 1.2.4.2 rmind dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1373 1.2.4.2 rmind { 1374 1.2.4.2 rmind panic("dino_sr_8: not implemented"); 1375 1.2.4.2 rmind } 1376 1.2.4.2 rmind 1377 1.2.4.2 rmind void 1378 1.2.4.2 rmind dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1379 1.2.4.2 rmind bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1380 1.2.4.2 rmind { 1381 1.2.4.2 rmind while (c--) 1382 1.2.4.2 rmind dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1383 1.2.4.2 rmind } 1384 1.2.4.2 rmind 1385 1.2.4.2 rmind void 1386 1.2.4.2 rmind dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1387 1.2.4.2 rmind bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1388 1.2.4.2 rmind { 1389 1.2.4.2 rmind while (c--) { 1390 1.2.4.2 rmind dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1391 1.2.4.2 rmind o1 += 2; 1392 1.2.4.2 rmind o2 += 2; 1393 1.2.4.2 rmind } 1394 1.2.4.2 rmind } 1395 1.2.4.2 rmind 1396 1.2.4.2 rmind void 1397 1.2.4.2 rmind dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1398 1.2.4.2 rmind bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1399 1.2.4.2 rmind { 1400 1.2.4.2 rmind while (c--) { 1401 1.2.4.2 rmind dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1402 1.2.4.2 rmind o1 += 4; 1403 1.2.4.2 rmind o2 += 4; 1404 1.2.4.2 rmind } 1405 1.2.4.2 rmind } 1406 1.2.4.2 rmind 1407 1.2.4.2 rmind void 1408 1.2.4.2 rmind dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1409 1.2.4.2 rmind bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1410 1.2.4.2 rmind { 1411 1.2.4.2 rmind while (c--) { 1412 1.2.4.2 rmind dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1413 1.2.4.2 rmind o1 += 8; 1414 1.2.4.2 rmind o2 += 8; 1415 1.2.4.2 rmind } 1416 1.2.4.2 rmind } 1417 1.2.4.2 rmind 1418 1.2.4.2 rmind 1419 1.2.4.2 rmind const struct hppa_bus_space_tag dino_iomemt = { 1420 1.2.4.2 rmind NULL, 1421 1.2.4.2 rmind 1422 1.2.4.2 rmind NULL, dino_unmap, dino_subregion, NULL, dino_free, 1423 1.2.4.2 rmind dino_barrier, dino_vaddr, dino_mmap, 1424 1.2.4.2 rmind dino_r1, dino_r2, dino_r4, dino_r8, 1425 1.2.4.2 rmind dino_w1, dino_w2, dino_w4, dino_w8, 1426 1.2.4.2 rmind dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1427 1.2.4.2 rmind dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1428 1.2.4.2 rmind dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1429 1.2.4.2 rmind dino_rrm_2, dino_rrm_4, dino_rrm_8, 1430 1.2.4.2 rmind dino_wrm_2, dino_wrm_4, dino_wrm_8, 1431 1.2.4.2 rmind dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1432 1.2.4.2 rmind dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1433 1.2.4.2 rmind dino_rrr_2, dino_rrr_4, dino_rrr_8, 1434 1.2.4.2 rmind dino_wrr_2, dino_wrr_4, dino_wrr_8, 1435 1.2.4.2 rmind dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1436 1.2.4.2 rmind dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1437 1.2.4.2 rmind }; 1438 1.2.4.2 rmind 1439 1.2.4.2 rmind int 1440 1.2.4.2 rmind dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1441 1.2.4.2 rmind bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1442 1.2.4.2 rmind { 1443 1.2.4.2 rmind struct dino_softc *sc = v; 1444 1.2.4.2 rmind 1445 1.2.4.2 rmind /* TODO check the addresses, boundary, enable dma */ 1446 1.2.4.2 rmind 1447 1.2.4.2 rmind return bus_dmamap_create(sc->sc_dmat, size, nsegments, 1448 1.2.4.2 rmind maxsegsz, boundary, flags, dmamp); 1449 1.2.4.2 rmind } 1450 1.2.4.2 rmind 1451 1.2.4.2 rmind void 1452 1.2.4.2 rmind dino_dmamap_destroy(void *v, bus_dmamap_t map) 1453 1.2.4.2 rmind { 1454 1.2.4.2 rmind struct dino_softc *sc = v; 1455 1.2.4.2 rmind 1456 1.2.4.2 rmind bus_dmamap_destroy(sc->sc_dmat, map); 1457 1.2.4.2 rmind } 1458 1.2.4.2 rmind 1459 1.2.4.2 rmind int 1460 1.2.4.2 rmind dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1461 1.2.4.2 rmind struct proc *p, int flags) 1462 1.2.4.2 rmind { 1463 1.2.4.2 rmind struct dino_softc *sc = v; 1464 1.2.4.2 rmind 1465 1.2.4.2 rmind return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); 1466 1.2.4.2 rmind } 1467 1.2.4.2 rmind 1468 1.2.4.2 rmind int 1469 1.2.4.2 rmind dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1470 1.2.4.2 rmind { 1471 1.2.4.2 rmind struct dino_softc *sc = v; 1472 1.2.4.2 rmind 1473 1.2.4.2 rmind return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); 1474 1.2.4.2 rmind } 1475 1.2.4.2 rmind 1476 1.2.4.2 rmind int 1477 1.2.4.2 rmind dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1478 1.2.4.2 rmind { 1479 1.2.4.2 rmind struct dino_softc *sc = v; 1480 1.2.4.2 rmind 1481 1.2.4.2 rmind return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); 1482 1.2.4.2 rmind } 1483 1.2.4.2 rmind 1484 1.2.4.2 rmind int 1485 1.2.4.2 rmind dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1486 1.2.4.2 rmind int nsegs, bus_size_t size, int flags) 1487 1.2.4.2 rmind { 1488 1.2.4.2 rmind struct dino_softc *sc = v; 1489 1.2.4.2 rmind 1490 1.2.4.2 rmind return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); 1491 1.2.4.2 rmind } 1492 1.2.4.2 rmind 1493 1.2.4.2 rmind void 1494 1.2.4.2 rmind dino_dmamap_unload(void *v, bus_dmamap_t map) 1495 1.2.4.2 rmind { 1496 1.2.4.2 rmind struct dino_softc *sc = v; 1497 1.2.4.2 rmind 1498 1.2.4.2 rmind bus_dmamap_unload(sc->sc_dmat, map); 1499 1.2.4.2 rmind } 1500 1.2.4.2 rmind 1501 1.2.4.2 rmind void 1502 1.2.4.2 rmind dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1503 1.2.4.2 rmind bus_size_t len, int ops) 1504 1.2.4.2 rmind { 1505 1.2.4.2 rmind struct dino_softc *sc = v; 1506 1.2.4.2 rmind 1507 1.2.4.2 rmind return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); 1508 1.2.4.2 rmind } 1509 1.2.4.2 rmind 1510 1.2.4.2 rmind int 1511 1.2.4.2 rmind dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1512 1.2.4.2 rmind bus_size_t boundary, bus_dma_segment_t *segs, 1513 1.2.4.2 rmind int nsegs, int *rsegs, int flags) 1514 1.2.4.2 rmind { 1515 1.2.4.2 rmind struct dino_softc *sc = v; 1516 1.2.4.2 rmind 1517 1.2.4.2 rmind return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1518 1.2.4.2 rmind segs, nsegs, rsegs, flags); 1519 1.2.4.2 rmind } 1520 1.2.4.2 rmind 1521 1.2.4.2 rmind void 1522 1.2.4.2 rmind dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1523 1.2.4.2 rmind { 1524 1.2.4.2 rmind struct dino_softc *sc = v; 1525 1.2.4.2 rmind 1526 1.2.4.2 rmind bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1527 1.2.4.2 rmind } 1528 1.2.4.2 rmind 1529 1.2.4.2 rmind int 1530 1.2.4.2 rmind dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1531 1.2.4.2 rmind void **kvap, int flags) 1532 1.2.4.2 rmind { 1533 1.2.4.2 rmind struct dino_softc *sc = v; 1534 1.2.4.2 rmind 1535 1.2.4.2 rmind return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); 1536 1.2.4.2 rmind } 1537 1.2.4.2 rmind 1538 1.2.4.2 rmind void 1539 1.2.4.2 rmind dino_dmamem_unmap(void *v, void *kva, size_t size) 1540 1.2.4.2 rmind { 1541 1.2.4.2 rmind struct dino_softc *sc = v; 1542 1.2.4.2 rmind 1543 1.2.4.2 rmind bus_dmamem_unmap(sc->sc_dmat, kva, size); 1544 1.2.4.2 rmind } 1545 1.2.4.2 rmind 1546 1.2.4.2 rmind paddr_t 1547 1.2.4.2 rmind dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1548 1.2.4.2 rmind int prot, int flags) 1549 1.2.4.2 rmind { 1550 1.2.4.2 rmind struct dino_softc *sc = v; 1551 1.2.4.2 rmind 1552 1.2.4.2 rmind return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); 1553 1.2.4.2 rmind } 1554 1.2.4.2 rmind 1555 1.2.4.2 rmind const struct hppa_bus_dma_tag dino_dmat = { 1556 1.2.4.2 rmind NULL, 1557 1.2.4.2 rmind dino_dmamap_create, dino_dmamap_destroy, 1558 1.2.4.2 rmind dino_dmamap_load, dino_dmamap_load_mbuf, 1559 1.2.4.2 rmind dino_dmamap_load_uio, dino_dmamap_load_raw, 1560 1.2.4.2 rmind dino_dmamap_unload, dino_dmamap_sync, 1561 1.2.4.2 rmind 1562 1.2.4.2 rmind dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1563 1.2.4.2 rmind dino_dmamem_unmap, dino_dmamem_mmap 1564 1.2.4.2 rmind }; 1565 1.2.4.2 rmind 1566 1.2.4.2 rmind const struct hppa_pci_chipset_tag dino_pc = { 1567 1.2.4.2 rmind NULL, 1568 1.2.4.2 rmind dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, 1569 1.2.4.2 rmind dino_conf_read, dino_conf_write, 1570 1.2.4.2 rmind dino_intr_map, dino_intr_string, 1571 1.2.4.2 rmind dino_intr_establish, dino_intr_disestablish, 1572 1.2.4.2 rmind #if NCARDBUS > 0 1573 1.2.4.2 rmind dino_alloc_parent 1574 1.2.4.2 rmind #else 1575 1.2.4.2 rmind NULL 1576 1.2.4.2 rmind #endif 1577 1.2.4.2 rmind }; 1578 1.2.4.2 rmind 1579 1.2.4.2 rmind int 1580 1.2.4.2 rmind dinomatch(device_t parent, cfdata_t cfdata, void *aux) 1581 1.2.4.2 rmind { 1582 1.2.4.2 rmind struct confargs *ca = aux; 1583 1.2.4.2 rmind 1584 1.2.4.2 rmind /* there will be only one */ 1585 1.2.4.2 rmind if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 1586 1.2.4.2 rmind ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 1587 1.2.4.2 rmind return 0; 1588 1.2.4.2 rmind 1589 1.2.4.2 rmind /* do not match on the elroy family */ 1590 1.2.4.2 rmind if (ca->ca_type.iodc_model == 0x78) 1591 1.2.4.2 rmind return 0; 1592 1.2.4.2 rmind 1593 1.2.4.2 rmind return 1; 1594 1.2.4.2 rmind } 1595 1.2.4.2 rmind 1596 1.2.4.2 rmind void 1597 1.2.4.2 rmind dinoattach(device_t parent, device_t self, void *aux) 1598 1.2.4.2 rmind { 1599 1.2.4.2 rmind struct dino_softc *sc = device_private(self); 1600 1.2.4.2 rmind struct confargs *ca = (struct confargs *)aux, nca; 1601 1.2.4.2 rmind struct pcibus_attach_args pba; 1602 1.2.4.2 rmind volatile struct dino_regs *r; 1603 1.2.4.2 rmind struct cpu_info *ci = &cpus[0]; 1604 1.2.4.2 rmind const char *p = NULL; 1605 1.2.4.2 rmind int s, ver; 1606 1.2.4.2 rmind 1607 1.2.4.2 rmind sc->sc_dv = self; 1608 1.2.4.2 rmind sc->sc_bt = ca->ca_iot; 1609 1.2.4.2 rmind sc->sc_dmat = ca->ca_dmatag; 1610 1.2.4.2 rmind 1611 1.2.4.2 rmind ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 1612 1.2.4.2 rmind if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 1613 1.2.4.2 rmind aprint_error_dev(self, ": can't allocate interrupt"); 1614 1.2.4.2 rmind return; 1615 1.2.4.2 rmind } 1616 1.2.4.2 rmind 1617 1.2.4.2 rmind if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1618 1.2.4.2 rmind aprint_error(": can't map space\n"); 1619 1.2.4.2 rmind return; 1620 1.2.4.2 rmind } 1621 1.2.4.2 rmind 1622 1.2.4.2 rmind sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1623 1.2.4.2 rmind #ifdef trust_the_firmware_to_proper_initialize_everything 1624 1.2.4.2 rmind r->io_addr_en = 0; 1625 1.2.4.2 rmind r->io_control = 0x80; 1626 1.2.4.2 rmind r->pamr = 0; 1627 1.2.4.2 rmind r->papr = 0; 1628 1.2.4.2 rmind r->io_fbb_en |= 1; 1629 1.2.4.2 rmind r->damode = 0; 1630 1.2.4.2 rmind r->gmask &= ~1; /* allow GSC bus req */ 1631 1.2.4.2 rmind r->pciror = 0; 1632 1.2.4.2 rmind r->pciwor = 0; 1633 1.2.4.2 rmind r->brdg_feat = 0xc0000000; 1634 1.2.4.2 rmind #endif 1635 1.2.4.2 rmind 1636 1.2.4.2 rmind snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1637 1.2.4.2 rmind "%s_io", device_xname(self)); 1638 1.2.4.2 rmind if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1639 1.2.4.2 rmind NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { 1640 1.2.4.2 rmind aprint_error(": can't allocate I/O extent map\n"); 1641 1.2.4.2 rmind bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE); 1642 1.2.4.2 rmind return; 1643 1.2.4.2 rmind } 1644 1.2.4.2 rmind 1645 1.2.4.2 rmind /* interrupts guts */ 1646 1.2.4.2 rmind s = splhigh(); 1647 1.2.4.2 rmind r->icr = 0; 1648 1.2.4.2 rmind r->imr = ~0; 1649 1.2.4.2 rmind (void)r->irr0; 1650 1.2.4.2 rmind r->imr = 0; 1651 1.2.4.2 rmind r->iar0 = ci->ci_hpa | (31 - ca->ca_irq); 1652 1.2.4.2 rmind splx(s); 1653 1.2.4.2 rmind /* Establish the interrupt register. */ 1654 1.2.4.2 rmind hppa_interrupt_register_establish(ci, &sc->sc_ir); 1655 1.2.4.2 rmind sc->sc_ir.ir_name = device_xname(self); 1656 1.2.4.2 rmind sc->sc_ir.ir_mask = &r->imr; 1657 1.2.4.2 rmind sc->sc_ir.ir_req = &r->irr0; 1658 1.2.4.2 rmind sc->sc_ir.ir_level = &r->ilr; 1659 1.2.4.2 rmind /* Add the I/O interrupt register. */ 1660 1.2.4.2 rmind 1661 1.2.4.2 rmind sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir, 1662 1.2.4.2 rmind &ci->ci_ir, ca->ca_irq); 1663 1.2.4.2 rmind 1664 1.2.4.2 rmind /* TODO establish the bus error interrupt */ 1665 1.2.4.2 rmind 1666 1.2.4.2 rmind ver = ca->ca_type.iodc_revision; 1667 1.2.4.2 rmind switch ((ca->ca_type.iodc_model << 4) | 1668 1.2.4.2 rmind (ca->ca_type.iodc_revision >> 4)) { 1669 1.2.4.2 rmind case 0x05d: 1670 1.2.4.2 rmind p = "Dino (card)"; /* j2240 */ 1671 1.2.4.2 rmind /* FALLTHROUGH */ 1672 1.2.4.2 rmind case 0x680: 1673 1.2.4.2 rmind if (!p) 1674 1.2.4.2 rmind p = "Dino"; 1675 1.2.4.2 rmind switch (ver & 0xf) { 1676 1.2.4.2 rmind case 0: ver = 0x20; break; 1677 1.2.4.2 rmind case 1: ver = 0x21; break; 1678 1.2.4.2 rmind case 2: ver = 0x30; break; 1679 1.2.4.2 rmind case 3: ver = 0x31; break; 1680 1.2.4.2 rmind } 1681 1.2.4.2 rmind break; 1682 1.2.4.2 rmind 1683 1.2.4.2 rmind case 0x682: 1684 1.2.4.2 rmind p = "Cujo"; 1685 1.2.4.2 rmind switch (ver & 0xf) { 1686 1.2.4.2 rmind case 0: ver = 0x10; break; 1687 1.2.4.2 rmind case 1: ver = 0x20; break; 1688 1.2.4.2 rmind } 1689 1.2.4.2 rmind break; 1690 1.2.4.2 rmind 1691 1.2.4.2 rmind default: 1692 1.2.4.2 rmind p = "Mojo"; 1693 1.2.4.2 rmind break; 1694 1.2.4.2 rmind } 1695 1.2.4.2 rmind 1696 1.2.4.2 rmind sc->sc_ver = ver; 1697 1.2.4.2 rmind aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); 1698 1.2.4.2 rmind 1699 1.2.4.2 rmind sc->sc_iot = dino_iomemt; 1700 1.2.4.2 rmind sc->sc_iot.hbt_cookie = sc; 1701 1.2.4.2 rmind sc->sc_iot.hbt_map = dino_iomap; 1702 1.2.4.2 rmind sc->sc_iot.hbt_alloc = dino_ioalloc; 1703 1.2.4.2 rmind sc->sc_memt = dino_iomemt; 1704 1.2.4.2 rmind sc->sc_memt.hbt_cookie = sc; 1705 1.2.4.2 rmind sc->sc_memt.hbt_map = dino_memmap; 1706 1.2.4.2 rmind sc->sc_memt.hbt_alloc = dino_memalloc; 1707 1.2.4.2 rmind sc->sc_pc = dino_pc; 1708 1.2.4.2 rmind sc->sc_pc._cookie = sc; 1709 1.2.4.2 rmind sc->sc_dmatag = dino_dmat; 1710 1.2.4.2 rmind sc->sc_dmatag._cookie = sc; 1711 1.2.4.2 rmind 1712 1.2.4.2 rmind /* scan for ps2 kbd/ms, serial, and flying toasters */ 1713 1.2.4.2 rmind nca = *ca; 1714 1.2.4.2 rmind 1715 1.2.4.2 rmind nca.ca_hpabase = 0; 1716 1.2.4.2 rmind nca.ca_nmodules = MAXMODBUS; 1717 1.2.4.2 rmind pdc_scanbus(self, &nca, dino_callback); 1718 1.2.4.2 rmind 1719 1.2.4.2 rmind memset(&pba, 0, sizeof(pba)); 1720 1.2.4.2 rmind pba.pba_iot = &sc->sc_iot; 1721 1.2.4.2 rmind pba.pba_memt = &sc->sc_memt; 1722 1.2.4.2 rmind pba.pba_dmat = &sc->sc_dmatag; 1723 1.2.4.2 rmind pba.pba_pc = &sc->sc_pc; 1724 1.2.4.2 rmind pba.pba_bus = 0; 1725 1.2.4.2 rmind pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 1726 1.2.4.2 rmind config_found_ia(self, "pcibus", &pba, pcibusprint); 1727 1.2.4.2 rmind } 1728 1.2.4.2 rmind 1729 1.2.4.2 rmind static device_t 1730 1.2.4.2 rmind dino_callback(device_t self, struct confargs *ca) 1731 1.2.4.2 rmind { 1732 1.2.4.2 rmind 1733 1.2.4.2 rmind return config_found_sm_loc(self, "dino", NULL, ca, mbprint, mbsubmatch); 1734 1.2.4.2 rmind } 1735
Indexes created Thu Oct 02 07:10:07 GMT 2025