dino.c revision 1.1
1 /* $NetBSD: dino.c,v 1.1 2014/02/24 07:23:42 skrll Exp $ */ 2 3 /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 2003 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.1 2014/02/24 07:23:42 skrll Exp $"); 33 34 /* #include "cardbus.h" */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/reboot.h> 40 #include <sys/malloc.h> 41 #include <sys/extent.h> 42 43 #include <machine/iomod.h> 44 #include <machine/autoconf.h> 45 #include <machine/intr.h> 46 47 #include <hppa/include/vmparam.h> 48 #include <hppa/dev/cpudevs.h> 49 50 #if NCARDBUS > 0 51 #include <dev/cardbus/rbus.h> 52 #endif 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #define DINO_MEM_CHUNK 0x800000 59 60 /* from machdep.c */ 61 extern struct extent *hppa_io_extent; 62 63 struct dino_regs { 64 /* HPA Supervisory Register Set */ 65 uint32_t pad0; /* 0x000 */ 66 uint32_t iar0; /* 0x004 rw intr addr reg 0 */ 67 uint32_t iodc; /* 0x008 rw iodc data/addr */ 68 uint32_t irr0; /* 0x00c r intr req reg 0 */ 69 uint32_t iar1; /* 0x010 rw intr addr reg 1 */ 70 uint32_t irr1; /* 0x014 r intr req reg 1 */ 71 uint32_t imr; /* 0x018 rw intr mask reg */ 72 uint32_t ipr; /* 0x01c rw intr pending reg */ 73 uint32_t toc_addr; /* 0x020 rw TOC addr reg */ 74 uint32_t icr; /* 0x024 rw intr control reg */ 75 uint32_t ilr; /* 0x028 r intr level reg */ 76 uint32_t pad1; /* 0x02c */ 77 uint32_t io_command; /* 0x030 w command register */ 78 uint32_t io_status; /* 0x034 r status register */ 79 uint32_t io_control; /* 0x038 rw control register */ 80 uint32_t pad2; /* 0x03c AUX registers follow */ 81 82 /* HPA Auxiliary Register Set */ 83 uint32_t io_gsc_err_addr;/* 0x040 GSC error address */ 84 uint32_t io_err_info; /* 0x044 error info register */ 85 uint32_t io_pci_err_addr;/* 0x048 PCI error address */ 86 uint32_t pad3[4]; /* 0x04c */ 87 uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 88 uint32_t io_addr_en; /* 0x060 address enable reg */ 89 uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 90 uint32_t pci_conf_data; /* 0x068 PCI conf data reg */ 91 uint32_t pci_io_data; /* 0x06c PCI io data reg */ 92 uint32_t pci_mem_data; /* 0x070 PCI memory data reg */ 93 uint32_t pad4[0x740/4]; /* 0x074 */ 94 95 /* HPA Bus (GSC) Specific-Dependent Register Set */ 96 uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 97 uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 98 99 /* HPA HVERSION (Dino)-Dependent Register Set */ 100 uint32_t gmask; /* 0x800 GSC arbitration mask */ 101 uint32_t pamr; /* 0x804 PCI arbitration mask */ 102 uint32_t papr; /* 0x808 PCI arbitration priority */ 103 uint32_t damode; /* 0x80c PCI arbitration mode */ 104 uint32_t pcicmd; /* 0x810 PCI command register */ 105 uint32_t pcists; /* 0x814 PCI status register */ 106 uint32_t pad6; /* 0x818 */ 107 uint32_t mltim; /* 0x81c PCI master latency timer */ 108 uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 109 uint32_t pciror; /* 0x824 PCI read optimization reg */ 110 uint32_t pciwor; /* 0x828 PCI write optimization reg */ 111 uint32_t pad7; /* 0x82c */ 112 uint32_t tltim; /* 0x830 PCI target latency reg */ 113 }; 114 115 struct dino_softc { 116 device_t sc_dv; 117 118 int sc_ver; 119 void *sc_ih; 120 struct hppa_interrupt_register sc_ir; 121 bus_space_tag_t sc_bt; 122 bus_space_handle_t sc_bh; 123 bus_dma_tag_t sc_dmat; 124 volatile struct dino_regs *sc_regs; 125 126 struct hppa_pci_chipset_tag sc_pc; 127 struct hppa_bus_space_tag sc_iot; 128 char sc_ioexname[20]; 129 struct extent *sc_ioex; 130 struct hppa_bus_space_tag sc_memt; 131 int sc_memrefcount[30]; 132 struct hppa_bus_dma_tag sc_dmatag; 133 }; 134 135 int dinomatch(device_t, struct cfdata *, void *); 136 void dinoattach(device_t, device_t, void *); 137 static device_t dino_callback(device_t, struct confargs *); 138 139 CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, 140 NULL); 141 142 void dino_attach_hook(device_t, device_t, 143 struct pcibus_attach_args *); 144 void dino_enable_bus(struct dino_softc *, int); 145 int dino_maxdevs(void *, int); 146 pcitag_t dino_make_tag(void *, int, int, int); 147 void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 148 pcireg_t dino_conf_read(void *, pcitag_t, int); 149 void dino_conf_write(void *, pcitag_t, int, pcireg_t); 150 151 int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 152 const char *dino_intr_string(void *, pci_intr_handle_t); 153 void *dino_intr_establish(void *, pci_intr_handle_t, int, 154 int (*)(void *), void *); 155 void dino_intr_disestablish(void *, void *); 156 157 void *dino_alloc_parent(device_t, struct pci_attach_args *, int); 158 159 int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 160 int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 161 int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 162 bus_space_handle_t *); 163 int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 164 bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 165 int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 166 bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 167 void dino_unmap(void *, bus_space_handle_t, bus_size_t); 168 void dino_free(void *, bus_space_handle_t, bus_size_t); 169 void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 170 void *dino_vaddr(void *, bus_space_handle_t); 171 paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int); 172 173 uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 174 uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 175 uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 176 uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 177 void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t); 178 void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 179 void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 180 void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t); 181 void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 182 void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 183 void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 184 void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 185 void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 186 bus_size_t); 187 void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 188 bus_size_t); 189 void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 190 bus_size_t); 191 void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 192 bus_size_t); 193 void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 194 void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 195 void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 196 void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 197 void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 198 bus_size_t); 199 void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 200 bus_size_t); 201 void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 202 bus_size_t); 203 void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 204 bus_size_t); 205 void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 206 bus_size_t); 207 void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 208 bus_size_t); 209 void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 210 void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 211 void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 212 void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 213 void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 214 bus_size_t); 215 void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 216 bus_size_t); 217 void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 218 bus_size_t); 219 void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 220 bus_size_t); 221 void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 222 bus_size_t); 223 void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 224 bus_size_t); 225 void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 226 bus_size_t); 227 void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 228 bus_size_t); 229 void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 230 bus_size_t); 231 void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 232 bus_size_t); 233 void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 234 void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 235 void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 236 void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 237 void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 238 bus_size_t, bus_size_t); 239 void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 240 bus_size_t, bus_size_t); 241 void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 242 bus_size_t, bus_size_t); 243 void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 244 bus_size_t, bus_size_t); 245 int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 246 bus_dmamap_t *); 247 void dino_dmamap_destroy(void *, bus_dmamap_t); 248 int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, 249 int); 250 int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 251 int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 252 int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 253 bus_size_t, int); 254 void dino_dmamap_unload(void *, bus_dmamap_t); 255 void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 256 int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 257 bus_dma_segment_t *, int, int *, int); 258 void dino_dmamem_free(void *, bus_dma_segment_t *, int); 259 int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int); 260 void dino_dmamem_unmap(void *, void *, size_t); 261 paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 262 263 264 void 265 dino_attach_hook(device_t parent, device_t self, 266 struct pcibus_attach_args *pba) 267 { 268 struct dino_softc *sc = pba->pba_pc->_cookie; 269 270 /* 271 * The firmware enables only devices that are needed for booting. 272 * So other devices will fail to map PCI MEM / IO when they attach. 273 * Therefore we recursively walk all buses to simply enable everything. 274 */ 275 dino_enable_bus(sc, 0); 276 } 277 278 void 279 dino_enable_bus(struct dino_softc *sc, int bus) 280 { 281 int func; 282 int dev; 283 pcitag_t tag; 284 pcireg_t data; 285 pcireg_t class; 286 287 for (dev = 0; dev < 32; dev++) { 288 tag = dino_make_tag(sc, bus, dev, 0); 289 if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) { 290 for (func = 0; func < 8; func++) { 291 tag = dino_make_tag(sc, bus, dev, func); 292 if (dino_conf_read(sc, tag, 0) != 0xffffffff) { 293 data = dino_conf_read(sc, tag, 294 PCI_COMMAND_STATUS_REG); 295 dino_conf_write(sc, tag, 296 PCI_COMMAND_STATUS_REG, 297 PCI_COMMAND_IO_ENABLE | 298 PCI_COMMAND_MEM_ENABLE | 299 PCI_COMMAND_MASTER_ENABLE | data); 300 } 301 } 302 class = dino_conf_read(sc, tag, PCI_CLASS_REG); 303 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 304 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI) 305 dino_enable_bus(sc, bus + 1); 306 } 307 } 308 } 309 310 int 311 dino_maxdevs(void *v, int bus) 312 { 313 return 32; 314 } 315 316 pcitag_t 317 dino_make_tag(void *v, int bus, int dev, int func) 318 { 319 if (bus > 255 || dev > 31 || func > 7) 320 panic("dino_make_tag: bad request"); 321 322 return (bus << 16) | (dev << 11) | (func << 8); 323 } 324 325 void 326 dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 327 { 328 *bus = (tag >> 16) & 0xff; 329 *dev = (tag >> 11) & 0x1f; 330 *func= (tag >> 8) & 0x07; 331 } 332 333 pcireg_t 334 dino_conf_read(void *v, pcitag_t tag, int reg) 335 { 336 struct dino_softc *sc = v; 337 volatile struct dino_regs *r = sc->sc_regs; 338 pcireg_t data; 339 uint32_t pamr; 340 341 /* fix arbitration errata by disabling all pci devs on config read */ 342 pamr = r->pamr; 343 r->pamr = 0; 344 345 r->pci_addr = tag | reg; 346 data = r->pci_conf_data; 347 348 /* restore arbitration */ 349 r->pamr = pamr; 350 351 return le32toh(data); 352 } 353 354 void 355 dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 356 { 357 struct dino_softc *sc = v; 358 volatile struct dino_regs *r = sc->sc_regs; 359 uint32_t pamr; 360 361 /* fix arbitration errata by disabling all pci devs on config read */ 362 pamr = r->pamr; 363 r->pamr = 0; 364 365 r->pci_addr = tag | reg; 366 r->pci_conf_data = htole32(data); 367 368 /* fix coalescing config and io writes by interleaving w/ a read */ 369 r->pci_addr = tag | PCI_ID_REG; 370 (void)r->pci_conf_data; 371 372 /* restore arbitration */ 373 r->pamr = pamr; 374 } 375 376 int 377 dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 378 { 379 int line = pa->pa_intrline; 380 381 if (line == 0xff) 382 return 1; 383 384 *ihp = line; 385 386 return 0; 387 } 388 389 const char * 390 dino_intr_string(void *v, pci_intr_handle_t ih) 391 { 392 static char buf[32]; 393 394 snprintf(buf, 32, "irq %ld", ih); 395 return buf; 396 } 397 398 extern int cold; 399 400 401 void * 402 dino_intr_establish(void *v, pci_intr_handle_t ih, 403 int pri, int (*handler)(void *), void *arg) 404 { 405 struct dino_softc *sc = v; 406 407 return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih); 408 } 409 410 void 411 dino_intr_disestablish(void *v, void *cookie) 412 { 413 /* XXX Implement me */ 414 } 415 416 417 #if NCARDBUS > 0 418 void * 419 dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io) 420 { 421 struct dino_softc *sc = pa->pa_pc->_cookie; 422 struct extent *ex; 423 bus_space_tag_t tag; 424 bus_addr_t start; 425 bus_size_t size; 426 427 if (io) { 428 ex = sc->sc_ioex; 429 tag = pa->pa_iot; 430 start = 0xa000; 431 size = 0x1000; 432 } else { 433 ex = hppa_io_extent; 434 tag = pa->pa_memt; 435 start = ex->ex_start; /* XXX or 0xf0800000? */ 436 size = DINO_MEM_CHUNK; 437 } 438 439 if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 440 EX_NOBOUNDARY, EX_NOWAIT, &start)) 441 return NULL; 442 extent_free(ex, start, size, EX_NOWAIT); 443 return rbus_new_root_share(tag, ex, start, size, start); 444 } 445 #endif 446 447 int 448 dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 449 int flags, bus_space_handle_t *bshp) 450 { 451 struct dino_softc *sc = v; 452 int error; 453 454 if (!(flags & BUS_SPACE_MAP_NOEXTENT) && 455 (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 456 return error; 457 458 if (bshp) 459 *bshp = bpa; 460 461 return 0; 462 } 463 464 int 465 dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 466 int flags, bus_space_handle_t *bshp) 467 { 468 struct dino_softc *sc = v; 469 volatile struct dino_regs *r = sc->sc_regs; 470 uint32_t reg; 471 int error; 472 473 reg = r->io_addr_en; 474 reg |= 1 << ((bpa >> 23) & 0x1f); 475 #ifdef DEBUG 476 if (reg & 0x80000001) 477 panic("mapping outside the mem extent range"); 478 #endif 479 if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) 480 return error; 481 ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; 482 /* map into the upper bus space, if not yet mapped this 8M */ 483 if (reg != r->io_addr_en) 484 r->io_addr_en = reg; 485 return 0; 486 } 487 488 int 489 dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 490 bus_size_t size, bus_space_handle_t *nbshp) 491 { 492 *nbshp = bsh + offset; 493 return 0; 494 } 495 496 int 497 dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 498 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 499 bus_space_handle_t *bshp) 500 { 501 struct dino_softc *sc = v; 502 struct extent *ex = sc->sc_ioex; 503 bus_addr_t bpa; 504 int error; 505 506 if (rstart < ex->ex_start || rend > ex->ex_end) 507 panic("dino_ioalloc: bad region start/end"); 508 509 if ((error = extent_alloc_subregion(ex, rstart, rend, size, 510 align, boundary, EX_NOWAIT, &bpa))) 511 return error; 512 513 if (addrp) 514 *addrp = bpa; 515 if (bshp) 516 *bshp = bpa; 517 518 return 0; 519 } 520 521 int 522 dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 523 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 524 bus_space_handle_t *bshp) 525 { 526 struct dino_softc *sc = v; 527 volatile struct dino_regs *r = sc->sc_regs; 528 uint32_t reg; 529 int i, error; 530 531 /* 532 * Allow allocation only when PCI MEM is already mapped. 533 * Needed to avoid allocation of I/O space used by devices that 534 * have no driver in the current kernel. 535 * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. 536 */ 537 reg = r->io_addr_en; 538 if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) 539 return -1; 540 /* Find used PCI MEM and narrow allocateble region down to it. */ 541 for (i = 1; i < 31; i++) 542 if ((reg & 1 << i) != 0) { 543 rstart = HPPA_IOSPACE | i << 23; 544 rend = (HPPA_IOSPACE | (i + 1) << 23) - 1; 545 break; 546 } 547 if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, 548 boundary, flags, addrp, bshp))) 549 return error; 550 ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; 551 return 0; 552 } 553 554 void 555 dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 556 { 557 struct dino_softc *sc = v; 558 volatile struct dino_regs *r = sc->sc_regs; 559 560 if (bsh & HPPA_IOSPACE) { 561 bus_space_unmap(sc->sc_bt, bsh, size); 562 if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) 563 /* Unmap the upper PCI MEM space. */ 564 r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); 565 } else { 566 /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ 567 if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) 568 printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 569 "dino_unmap: can't free region\n", bsh, size); 570 } 571 } 572 573 void 574 dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 575 { 576 /* should be enough */ 577 dino_unmap(v, bh, size); 578 } 579 580 void 581 dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 582 { 583 sync_caches(); 584 } 585 586 void* 587 dino_vaddr(void *v, bus_space_handle_t h) 588 { 589 struct dino_softc *sc = v; 590 591 return bus_space_vaddr(sc->sc_bt, h); 592 } 593 594 paddr_t 595 dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 596 { 597 return -1; 598 } 599 600 uint8_t 601 dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 602 { 603 h += o; 604 if (h & HPPA_IOSPACE) 605 return *(volatile uint8_t *)h; 606 else { 607 struct dino_softc *sc = v; 608 volatile struct dino_regs *r = sc->sc_regs; 609 610 r->pci_addr = h; 611 return *((volatile uint8_t *)&r->pci_io_data + (h & 3)); 612 } 613 } 614 615 uint16_t 616 dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 617 { 618 volatile uint16_t *p; 619 620 h += o; 621 if (h & HPPA_IOSPACE) 622 p = (volatile uint16_t *)h; 623 else { 624 struct dino_softc *sc = v; 625 volatile struct dino_regs *r = sc->sc_regs; 626 627 r->pci_addr = h; 628 p = (volatile uint16_t *)&r->pci_io_data; 629 if (h & 2) 630 p++; 631 } 632 return le16toh(*p); 633 } 634 635 uint32_t 636 dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 637 { 638 uint32_t data; 639 640 h += o; 641 if (h & HPPA_IOSPACE) 642 data = *(volatile uint32_t *)h; 643 else { 644 struct dino_softc *sc = v; 645 volatile struct dino_regs *r = sc->sc_regs; 646 647 r->pci_addr = h; 648 data = r->pci_io_data; 649 } 650 651 return le32toh(data); 652 } 653 654 uint64_t 655 dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 656 { 657 uint64_t data; 658 659 h += o; 660 if (h & HPPA_IOSPACE) 661 data = *(volatile uint64_t *)h; 662 else 663 panic("dino_r8: not implemented"); 664 665 return le64toh(data); 666 } 667 668 void 669 dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv) 670 { 671 h += o; 672 if (h & HPPA_IOSPACE) 673 *(volatile uint8_t *)h = vv; 674 else { 675 struct dino_softc *sc = v; 676 volatile struct dino_regs *r = sc->sc_regs; 677 678 r->pci_addr = h; 679 *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv; 680 } 681 } 682 683 void 684 dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 685 { 686 volatile uint16_t *p; 687 688 h += o; 689 if (h & HPPA_IOSPACE) 690 p = (volatile uint16_t *)h; 691 else { 692 struct dino_softc *sc = v; 693 volatile struct dino_regs *r = sc->sc_regs; 694 695 r->pci_addr = h; 696 p = (volatile uint16_t *)&r->pci_io_data; 697 if (h & 2) 698 p++; 699 } 700 701 *p = htole16(vv); 702 } 703 704 void 705 dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 706 { 707 h += o; 708 vv = htole32(vv); 709 if (h & HPPA_IOSPACE) 710 *(volatile uint32_t *)h = vv; 711 else { 712 struct dino_softc *sc = v; 713 volatile struct dino_regs *r = sc->sc_regs; 714 715 r->pci_addr = h; 716 r->pci_io_data = vv; 717 } 718 } 719 720 void 721 dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 722 { 723 h += o; 724 if (h & HPPA_IOSPACE) 725 *(volatile uint64_t *)h = htole64(vv); 726 else 727 panic("dino_w8: not implemented"); 728 } 729 730 731 void 732 dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 733 { 734 volatile uint8_t *p; 735 736 h += o; 737 if (h & HPPA_IOSPACE) 738 p = (volatile uint8_t *)h; 739 else { 740 struct dino_softc *sc = v; 741 volatile struct dino_regs *r = sc->sc_regs; 742 743 r->pci_addr = h; 744 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 745 } 746 747 while (c--) 748 *a++ = *p; 749 } 750 751 void 752 dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 753 { 754 volatile uint16_t *p; 755 756 h += o; 757 if (h & HPPA_IOSPACE) 758 p = (volatile uint16_t *)h; 759 else { 760 struct dino_softc *sc = v; 761 volatile struct dino_regs *r = sc->sc_regs; 762 763 r->pci_addr = h; 764 p = (volatile uint16_t *)&r->pci_io_data; 765 if (h & 2) 766 p++; 767 } 768 769 while (c--) 770 *a++ = le16toh(*p); 771 } 772 773 void 774 dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 775 { 776 volatile uint32_t *p; 777 778 h += o; 779 if (h & HPPA_IOSPACE) 780 p = (volatile uint32_t *)h; 781 else { 782 struct dino_softc *sc = v; 783 volatile struct dino_regs *r = sc->sc_regs; 784 785 r->pci_addr = h; 786 p = (volatile uint32_t *)&r->pci_io_data; 787 } 788 789 while (c--) 790 *a++ = le32toh(*p); 791 } 792 793 void 794 dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 795 { 796 panic("dino_rm_8: not implemented"); 797 } 798 799 void 800 dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 801 { 802 volatile uint8_t *p; 803 804 h += o; 805 if (h & HPPA_IOSPACE) 806 p = (volatile uint8_t *)h; 807 else { 808 struct dino_softc *sc = v; 809 volatile struct dino_regs *r = sc->sc_regs; 810 811 r->pci_addr = h; 812 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 813 } 814 815 while (c--) 816 *p = *a++; 817 } 818 819 void 820 dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 821 { 822 volatile uint16_t *p; 823 824 h += o; 825 if (h & HPPA_IOSPACE) 826 p = (volatile uint16_t *)h; 827 else { 828 struct dino_softc *sc = v; 829 volatile struct dino_regs *r = sc->sc_regs; 830 831 r->pci_addr = h; 832 p = (volatile uint16_t *)&r->pci_io_data; 833 if (h & 2) 834 p++; 835 } 836 837 while (c--) 838 *p = htole16(*a++); 839 } 840 841 void 842 dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 843 { 844 volatile uint32_t *p; 845 846 h += o; 847 if (h & HPPA_IOSPACE) 848 p = (volatile uint32_t *)h; 849 else { 850 struct dino_softc *sc = v; 851 volatile struct dino_regs *r = sc->sc_regs; 852 853 r->pci_addr = h; 854 p = (volatile uint32_t *)&r->pci_io_data; 855 } 856 857 while (c--) 858 *p = htole32(*a++); 859 } 860 861 void 862 dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 863 { 864 panic("dino_wm_8: not implemented"); 865 } 866 867 void 868 dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 869 { 870 volatile uint8_t *p; 871 872 h += o; 873 if (h & HPPA_IOSPACE) 874 p = (volatile uint8_t *)h; 875 else { 876 struct dino_softc *sc = v; 877 volatile struct dino_regs *r = sc->sc_regs; 878 879 r->pci_addr = h; 880 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 881 } 882 883 while (c--) 884 *p = vv; 885 } 886 887 void 888 dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 889 { 890 volatile uint16_t *p; 891 892 h += o; 893 if (h & HPPA_IOSPACE) 894 p = (volatile uint16_t *)h; 895 else { 896 struct dino_softc *sc = v; 897 volatile struct dino_regs *r = sc->sc_regs; 898 899 r->pci_addr = h; 900 p = (volatile uint16_t *)&r->pci_io_data; 901 if (h & 2) 902 p++; 903 } 904 905 while (c--) 906 *p = htole16(vv); 907 } 908 909 void 910 dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 911 { 912 volatile uint32_t *p; 913 914 h += o; 915 if (h & HPPA_IOSPACE) 916 p = (volatile uint32_t *)h; 917 else { 918 struct dino_softc *sc = v; 919 volatile struct dino_regs *r = sc->sc_regs; 920 921 r->pci_addr = h; 922 p = (volatile uint32_t *)&r->pci_io_data; 923 } 924 925 while (c--) 926 *p = htole32(vv); 927 } 928 929 void 930 dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 931 { 932 panic("dino_sm_8: not implemented"); 933 } 934 935 void 936 dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 937 uint16_t *a, bus_size_t c) 938 { 939 volatile uint16_t *p; 940 941 h += o; 942 if (h & HPPA_IOSPACE) 943 p = (volatile uint16_t *)h; 944 else { 945 struct dino_softc *sc = v; 946 volatile struct dino_regs *r = sc->sc_regs; 947 948 r->pci_addr = h; 949 p = (volatile uint16_t *)&r->pci_io_data; 950 if (h & 2) 951 p++; 952 } 953 954 while (c--) 955 *a++ = *p; 956 } 957 958 void 959 dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 960 uint32_t *a, bus_size_t c) 961 { 962 volatile uint32_t *p; 963 964 h += o; 965 if (h & HPPA_IOSPACE) 966 p = (volatile uint32_t *)h; 967 else { 968 struct dino_softc *sc = v; 969 volatile struct dino_regs *r = sc->sc_regs; 970 971 r->pci_addr = h; 972 p = (volatile uint32_t *)&r->pci_io_data; 973 } 974 975 while (c--) 976 *a++ = *p; 977 } 978 979 void 980 dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 981 uint64_t *a, bus_size_t c) 982 { 983 panic("dino_rrm_8: not implemented"); 984 } 985 986 void 987 dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 988 const uint16_t *a, bus_size_t c) 989 { 990 volatile uint16_t *p; 991 992 h += o; 993 if (h & HPPA_IOSPACE) 994 p = (volatile uint16_t *)h; 995 else { 996 struct dino_softc *sc = v; 997 volatile struct dino_regs *r = sc->sc_regs; 998 999 r->pci_addr = h; 1000 p = (volatile uint16_t *)&r->pci_io_data; 1001 if (h & 2) 1002 p++; 1003 } 1004 1005 while (c--) 1006 *p = *a++; 1007 } 1008 1009 void 1010 dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1011 const uint32_t *a, bus_size_t c) 1012 { 1013 volatile uint32_t *p; 1014 1015 h += o; 1016 if (h & HPPA_IOSPACE) 1017 p = (volatile uint32_t *)h; 1018 else { 1019 struct dino_softc *sc = v; 1020 volatile struct dino_regs *r = sc->sc_regs; 1021 1022 r->pci_addr = h; 1023 p = (volatile uint32_t *)&r->pci_io_data; 1024 } 1025 1026 while (c--) 1027 *p = *a++; 1028 } 1029 1030 void 1031 dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1032 const uint64_t *a, bus_size_t c) 1033 { 1034 panic("dino_wrm_8: not implemented"); 1035 } 1036 1037 void 1038 dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 1039 { 1040 volatile uint8_t *p; 1041 1042 h += o; 1043 if (h & HPPA_IOSPACE) { 1044 p = (volatile uint8_t *)h; 1045 while (c--) 1046 *a++ = *p++; 1047 } else { 1048 struct dino_softc *sc = v; 1049 volatile struct dino_regs *r = sc->sc_regs; 1050 1051 for (; c--; h++) { 1052 r->pci_addr = h; 1053 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1054 *a++ = *p; 1055 } 1056 } 1057 } 1058 1059 void 1060 dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 1061 { 1062 volatile uint16_t *p, data; 1063 1064 h += o; 1065 if (h & HPPA_IOSPACE) { 1066 p = (volatile uint16_t *)h; 1067 while (c--) { 1068 data = *p++; 1069 *a++ = le16toh(data); 1070 } 1071 } else { 1072 struct dino_softc *sc = v; 1073 volatile struct dino_regs *r = sc->sc_regs; 1074 1075 for (; c--; h += 2) { 1076 r->pci_addr = h; 1077 p = (volatile uint16_t *)&r->pci_io_data; 1078 if (h & 2) 1079 p++; 1080 data = *p; 1081 *a++ = le16toh(data); 1082 } 1083 } 1084 } 1085 1086 void 1087 dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 1088 { 1089 volatile uint32_t *p, data; 1090 1091 h += o; 1092 if (h & HPPA_IOSPACE) { 1093 p = (volatile uint32_t *)h; 1094 while (c--) { 1095 data = *p++; 1096 *a++ = le32toh(data); 1097 } 1098 } else { 1099 struct dino_softc *sc = v; 1100 volatile struct dino_regs *r = sc->sc_regs; 1101 1102 for (; c--; h += 4) { 1103 r->pci_addr = h; 1104 data = r->pci_io_data; 1105 *a++ = le32toh(data); 1106 } 1107 } 1108 } 1109 1110 void 1111 dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 1112 { 1113 panic("dino_rr_8: not implemented"); 1114 } 1115 1116 void 1117 dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 1118 { 1119 volatile uint8_t *p; 1120 1121 h += o; 1122 if (h & HPPA_IOSPACE) { 1123 p = (volatile uint8_t *)h; 1124 while (c--) 1125 *p++ = *a++; 1126 } else { 1127 struct dino_softc *sc = v; 1128 volatile struct dino_regs *r = sc->sc_regs; 1129 1130 for (; c--; h++) { 1131 r->pci_addr = h; 1132 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1133 *p = *a++; 1134 } 1135 } 1136 } 1137 1138 void 1139 dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 1140 { 1141 volatile uint16_t *p, data; 1142 1143 h += o; 1144 if (h & HPPA_IOSPACE) { 1145 p = (volatile uint16_t *)h; 1146 while (c--) { 1147 data = *a++; 1148 *p++ = htole16(data); 1149 } 1150 } else { 1151 struct dino_softc *sc = v; 1152 volatile struct dino_regs *r = sc->sc_regs; 1153 1154 for (; c--; h += 2) { 1155 r->pci_addr = h; 1156 p = (volatile uint16_t *)&r->pci_io_data; 1157 if (h & 2) 1158 p++; 1159 data = *a++; 1160 *p = htole16(data); 1161 } 1162 } 1163 } 1164 1165 void 1166 dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 1167 { 1168 volatile uint32_t *p, data; 1169 1170 h += o; 1171 if (h & HPPA_IOSPACE) { 1172 p = (volatile uint32_t *)h; 1173 while (c--) { 1174 data = *a++; 1175 *p++ = htole32(data); 1176 } 1177 } else { 1178 struct dino_softc *sc = v; 1179 volatile struct dino_regs *r = sc->sc_regs; 1180 1181 for (; c--; h += 4) { 1182 r->pci_addr = h; 1183 data = *a++; 1184 r->pci_io_data = htole32(data); 1185 } 1186 } 1187 } 1188 1189 void 1190 dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 1191 { 1192 panic("dino_wr_8: not implemented"); 1193 } 1194 1195 void 1196 dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1197 uint16_t *a, bus_size_t c) 1198 { 1199 volatile uint16_t *p; 1200 1201 h += o; 1202 if (h & HPPA_IOSPACE) { 1203 p = (volatile uint16_t *)h; 1204 while (c--) 1205 *a++ = *p++; 1206 } else { 1207 struct dino_softc *sc = v; 1208 volatile struct dino_regs *r = sc->sc_regs; 1209 1210 for (; c--; h += 2) { 1211 r->pci_addr = h; 1212 p = (volatile uint16_t *)&r->pci_io_data; 1213 if (h & 2) 1214 p++; 1215 *a++ = *p; 1216 } 1217 } 1218 } 1219 1220 void 1221 dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1222 uint32_t *a, bus_size_t c) 1223 { 1224 volatile uint32_t *p; 1225 1226 h += o; 1227 if (h & HPPA_IOSPACE) { 1228 p = (volatile uint32_t *)h; 1229 while (c--) 1230 *a++ = *p++; 1231 } else { 1232 struct dino_softc *sc = v; 1233 volatile struct dino_regs *r = sc->sc_regs; 1234 1235 for (; c--; h += 4) { 1236 r->pci_addr = h; 1237 *a++ = r->pci_io_data; 1238 } 1239 } 1240 } 1241 1242 void 1243 dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1244 uint64_t *a, bus_size_t c) 1245 { 1246 panic("dino_rrr_8: not implemented"); 1247 } 1248 1249 void 1250 dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1251 const uint16_t *a, bus_size_t c) 1252 { 1253 volatile uint16_t *p; 1254 1255 h += o; 1256 if (h & HPPA_IOSPACE) { 1257 p = (volatile uint16_t *)h; 1258 while (c--) 1259 *p++ = *a++; 1260 } else { 1261 struct dino_softc *sc = v; 1262 volatile struct dino_regs *r = sc->sc_regs; 1263 1264 for (; c--; h += 2) { 1265 r->pci_addr = h; 1266 p = (volatile uint16_t *)&r->pci_io_data; 1267 if (h & 2) 1268 p++; 1269 *p = *a++; 1270 } 1271 } 1272 } 1273 1274 void 1275 dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1276 const uint32_t *a, bus_size_t c) 1277 { 1278 volatile uint32_t *p; 1279 1280 c /= 4; 1281 h += o; 1282 if (h & HPPA_IOSPACE) { 1283 p = (volatile uint32_t *)h; 1284 while (c--) 1285 *p++ = *a++; 1286 } else { 1287 struct dino_softc *sc = v; 1288 volatile struct dino_regs *r = sc->sc_regs; 1289 1290 for (; c--; h += 4) { 1291 r->pci_addr = h; 1292 r->pci_io_data = *a++; 1293 } 1294 } 1295 } 1296 1297 void 1298 dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1299 const uint64_t *a, bus_size_t c) 1300 { 1301 panic("dino_wrr_8: not implemented"); 1302 } 1303 1304 void 1305 dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1306 { 1307 volatile uint8_t *p; 1308 1309 h += o; 1310 if (h & HPPA_IOSPACE) { 1311 p = (volatile uint8_t *)h; 1312 while (c--) 1313 *p++ = vv; 1314 } else { 1315 struct dino_softc *sc = v; 1316 volatile struct dino_regs *r = sc->sc_regs; 1317 1318 for (; c--; h++) { 1319 r->pci_addr = h; 1320 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1321 *p = vv; 1322 } 1323 } 1324 } 1325 1326 void 1327 dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1328 { 1329 volatile uint16_t *p; 1330 1331 h += o; 1332 vv = htole16(vv); 1333 if (h & HPPA_IOSPACE) { 1334 p = (volatile uint16_t *)h; 1335 while (c--) 1336 *p++ = vv; 1337 } else { 1338 struct dino_softc *sc = v; 1339 volatile struct dino_regs *r = sc->sc_regs; 1340 1341 for (; c--; h += 2) { 1342 r->pci_addr = h; 1343 p = (volatile uint16_t *)&r->pci_io_data; 1344 if (h & 2) 1345 p++; 1346 *p = vv; 1347 } 1348 } 1349 } 1350 1351 void 1352 dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1353 { 1354 volatile uint32_t *p; 1355 1356 h += o; 1357 vv = htole32(vv); 1358 if (h & HPPA_IOSPACE) { 1359 p = (volatile uint32_t *)h; 1360 while (c--) 1361 *p++ = vv; 1362 } else { 1363 struct dino_softc *sc = v; 1364 volatile struct dino_regs *r = sc->sc_regs; 1365 1366 for (; c--; h += 4) { 1367 r->pci_addr = h; 1368 r->pci_io_data = vv; 1369 } 1370 } 1371 } 1372 1373 void 1374 dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1375 { 1376 panic("dino_sr_8: not implemented"); 1377 } 1378 1379 void 1380 dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1381 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1382 { 1383 while (c--) 1384 dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1385 } 1386 1387 void 1388 dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1389 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1390 { 1391 while (c--) { 1392 dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1393 o1 += 2; 1394 o2 += 2; 1395 } 1396 } 1397 1398 void 1399 dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1400 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1401 { 1402 while (c--) { 1403 dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1404 o1 += 4; 1405 o2 += 4; 1406 } 1407 } 1408 1409 void 1410 dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1411 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1412 { 1413 while (c--) { 1414 dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1415 o1 += 8; 1416 o2 += 8; 1417 } 1418 } 1419 1420 1421 const struct hppa_bus_space_tag dino_iomemt = { 1422 NULL, 1423 1424 NULL, dino_unmap, dino_subregion, NULL, dino_free, 1425 dino_barrier, dino_vaddr, dino_mmap, 1426 dino_r1, dino_r2, dino_r4, dino_r8, 1427 dino_w1, dino_w2, dino_w4, dino_w8, 1428 dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1429 dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1430 dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1431 dino_rrm_2, dino_rrm_4, dino_rrm_8, 1432 dino_wrm_2, dino_wrm_4, dino_wrm_8, 1433 dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1434 dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1435 dino_rrr_2, dino_rrr_4, dino_rrr_8, 1436 dino_wrr_2, dino_wrr_4, dino_wrr_8, 1437 dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1438 dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1439 }; 1440 1441 int 1442 dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1443 bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1444 { 1445 struct dino_softc *sc = v; 1446 1447 /* TODO check the addresses, boundary, enable dma */ 1448 1449 return bus_dmamap_create(sc->sc_dmat, size, nsegments, 1450 maxsegsz, boundary, flags, dmamp); 1451 } 1452 1453 void 1454 dino_dmamap_destroy(void *v, bus_dmamap_t map) 1455 { 1456 struct dino_softc *sc = v; 1457 1458 bus_dmamap_destroy(sc->sc_dmat, map); 1459 } 1460 1461 int 1462 dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1463 struct proc *p, int flags) 1464 { 1465 struct dino_softc *sc = v; 1466 1467 return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); 1468 } 1469 1470 int 1471 dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1472 { 1473 struct dino_softc *sc = v; 1474 1475 return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); 1476 } 1477 1478 int 1479 dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1480 { 1481 struct dino_softc *sc = v; 1482 1483 return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); 1484 } 1485 1486 int 1487 dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1488 int nsegs, bus_size_t size, int flags) 1489 { 1490 struct dino_softc *sc = v; 1491 1492 return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); 1493 } 1494 1495 void 1496 dino_dmamap_unload(void *v, bus_dmamap_t map) 1497 { 1498 struct dino_softc *sc = v; 1499 1500 bus_dmamap_unload(sc->sc_dmat, map); 1501 } 1502 1503 void 1504 dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1505 bus_size_t len, int ops) 1506 { 1507 struct dino_softc *sc = v; 1508 1509 return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); 1510 } 1511 1512 int 1513 dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1514 bus_size_t boundary, bus_dma_segment_t *segs, 1515 int nsegs, int *rsegs, int flags) 1516 { 1517 struct dino_softc *sc = v; 1518 1519 return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1520 segs, nsegs, rsegs, flags); 1521 } 1522 1523 void 1524 dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1525 { 1526 struct dino_softc *sc = v; 1527 1528 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1529 } 1530 1531 int 1532 dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1533 void **kvap, int flags) 1534 { 1535 struct dino_softc *sc = v; 1536 1537 return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); 1538 } 1539 1540 void 1541 dino_dmamem_unmap(void *v, void *kva, size_t size) 1542 { 1543 struct dino_softc *sc = v; 1544 1545 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1546 } 1547 1548 paddr_t 1549 dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1550 int prot, int flags) 1551 { 1552 struct dino_softc *sc = v; 1553 1554 return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); 1555 } 1556 1557 const struct hppa_bus_dma_tag dino_dmat = { 1558 NULL, 1559 dino_dmamap_create, dino_dmamap_destroy, 1560 dino_dmamap_load, dino_dmamap_load_mbuf, 1561 dino_dmamap_load_uio, dino_dmamap_load_raw, 1562 dino_dmamap_unload, dino_dmamap_sync, 1563 1564 dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1565 dino_dmamem_unmap, dino_dmamem_mmap 1566 }; 1567 1568 const struct hppa_pci_chipset_tag dino_pc = { 1569 NULL, 1570 dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, 1571 dino_conf_read, dino_conf_write, 1572 dino_intr_map, dino_intr_string, 1573 dino_intr_establish, dino_intr_disestablish, 1574 #if NCARDBUS > 0 1575 dino_alloc_parent 1576 #else 1577 NULL 1578 #endif 1579 }; 1580 1581 int 1582 dinomatch(device_t parent, cfdata_t cfdata, void *aux) 1583 { 1584 struct confargs *ca = aux; 1585 1586 /* there will be only one */ 1587 if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 1588 ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 1589 return 0; 1590 1591 /* do not match on the elroy family */ 1592 if (ca->ca_type.iodc_model == 0x78) 1593 return 0; 1594 1595 return 1; 1596 } 1597 1598 void 1599 dinoattach(device_t parent, device_t self, void *aux) 1600 { 1601 struct dino_softc *sc = device_private(self); 1602 struct confargs *ca = (struct confargs *)aux, nca; 1603 struct pcibus_attach_args pba; 1604 volatile struct dino_regs *r; 1605 struct cpu_info *ci = &cpus[0]; 1606 const char *p = NULL; 1607 int s, ver; 1608 1609 sc->sc_dv = self; 1610 sc->sc_bt = ca->ca_iot; 1611 sc->sc_dmat = ca->ca_dmatag; 1612 1613 ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 1614 if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 1615 aprint_error_dev(self, ": can't allocate interrupt"); 1616 return; 1617 } 1618 1619 if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1620 aprint_error(": can't map space\n"); 1621 return; 1622 } 1623 1624 sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1625 #ifdef trust_the_firmware_to_proper_initialize_everything 1626 r->io_addr_en = 0; 1627 r->io_control = 0x80; 1628 r->pamr = 0; 1629 r->papr = 0; 1630 r->io_fbb_en |= 1; 1631 r->damode = 0; 1632 r->gmask &= ~1; /* allow GSC bus req */ 1633 r->pciror = 0; 1634 r->pciwor = 0; 1635 r->brdg_feat = 0xc0000000; 1636 #endif 1637 1638 snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1639 "%s_io", device_xname(self)); 1640 if ((sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1641 NULL, 0, EX_NOWAIT | EX_MALLOCOK)) == NULL) { 1642 aprint_error(": can't allocate I/O extent map\n"); 1643 bus_space_unmap(sc->sc_bt, sc->sc_bh, PAGE_SIZE); 1644 return; 1645 } 1646 1647 /* interrupts guts */ 1648 s = splhigh(); 1649 r->icr = 0; 1650 r->imr = ~0; 1651 (void)r->irr0; 1652 r->imr = 0; 1653 r->iar0 = ci->ci_hpa | (31 - ca->ca_irq); 1654 splx(s); 1655 /* Establish the interrupt register. */ 1656 hppa_interrupt_register_establish(ci, &sc->sc_ir); 1657 sc->sc_ir.ir_name = device_xname(self); 1658 sc->sc_ir.ir_mask = &r->imr; 1659 sc->sc_ir.ir_req = &r->irr0; 1660 sc->sc_ir.ir_level = &r->ilr; 1661 /* Add the I/O interrupt register. */ 1662 1663 sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir, 1664 &ci->ci_ir, ca->ca_irq); 1665 1666 /* TODO establish the bus error interrupt */ 1667 1668 ver = ca->ca_type.iodc_revision; 1669 switch ((ca->ca_type.iodc_model << 4) | 1670 (ca->ca_type.iodc_revision >> 4)) { 1671 case 0x05d: 1672 p = "Dino (card)"; /* j2240 */ 1673 /* FALLTHROUGH */ 1674 case 0x680: 1675 if (!p) 1676 p = "Dino"; 1677 switch (ver & 0xf) { 1678 case 0: ver = 0x20; break; 1679 case 1: ver = 0x21; break; 1680 case 2: ver = 0x30; break; 1681 case 3: ver = 0x31; break; 1682 } 1683 break; 1684 1685 case 0x682: 1686 p = "Cujo"; 1687 switch (ver & 0xf) { 1688 case 0: ver = 0x10; break; 1689 case 1: ver = 0x20; break; 1690 } 1691 break; 1692 1693 default: 1694 p = "Mojo"; 1695 break; 1696 } 1697 1698 sc->sc_ver = ver; 1699 aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); 1700 1701 sc->sc_iot = dino_iomemt; 1702 sc->sc_iot.hbt_cookie = sc; 1703 sc->sc_iot.hbt_map = dino_iomap; 1704 sc->sc_iot.hbt_alloc = dino_ioalloc; 1705 sc->sc_memt = dino_iomemt; 1706 sc->sc_memt.hbt_cookie = sc; 1707 sc->sc_memt.hbt_map = dino_memmap; 1708 sc->sc_memt.hbt_alloc = dino_memalloc; 1709 sc->sc_pc = dino_pc; 1710 sc->sc_pc._cookie = sc; 1711 sc->sc_dmatag = dino_dmat; 1712 sc->sc_dmatag._cookie = sc; 1713 1714 /* scan for ps2 kbd/ms, serial, and flying toasters */ 1715 nca = *ca; 1716 1717 nca.ca_hpabase = 0; 1718 nca.ca_nmodules = MAXMODBUS; 1719 pdc_scanbus(self, &nca, dino_callback); 1720 1721 memset(&pba, 0, sizeof(pba)); 1722 pba.pba_iot = &sc->sc_iot; 1723 pba.pba_memt = &sc->sc_memt; 1724 pba.pba_dmat = &sc->sc_dmatag; 1725 pba.pba_pc = &sc->sc_pc; 1726 pba.pba_bus = 0; 1727 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 1728 config_found_ia(self, "pcibus", &pba, pcibusprint); 1729 } 1730 1731 static device_t 1732 dino_callback(device_t self, struct confargs *ca) 1733 { 1734 1735 return config_found_sm_loc(self, "dino", NULL, ca, mbprint, mbsubmatch); 1736 } 1737
Indexes created Thu Sep 25 16:09:42 GMT 2025