dino.c revision 1.7
1 /* $NetBSD: dino.c,v 1.7 2020/10/16 17:59:46 macallan Exp $ */ 2 3 /* $OpenBSD: dino.c,v 1.5 2004/02/13 20:39:31 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 2003 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #include <sys/cdefs.h> 32 __KERNEL_RCSID(0, "$NetBSD: dino.c,v 1.7 2020/10/16 17:59:46 macallan Exp $"); 33 34 /* #include "cardbus.h" */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/reboot.h> 40 #include <sys/malloc.h> 41 #include <sys/extent.h> 42 43 #include <machine/iomod.h> 44 #include <machine/autoconf.h> 45 #include <machine/intr.h> 46 47 #include <hppa/include/vmparam.h> 48 #include <hppa/dev/cpudevs.h> 49 50 #if NCARDBUS > 0 51 #include <dev/cardbus/rbus.h> 52 #endif 53 54 #include <dev/pci/pcireg.h> 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcidevs.h> 57 58 #define DINO_MEM_CHUNK 0x800000 59 60 /* from machdep.c */ 61 extern struct extent *hppa_io_extent; 62 63 struct dino_regs { 64 /* HPA Supervisory Register Set */ 65 uint32_t pad0; /* 0x000 */ 66 uint32_t iar0; /* 0x004 rw intr addr reg 0 */ 67 uint32_t iodc; /* 0x008 rw iodc data/addr */ 68 uint32_t irr0; /* 0x00c r intr req reg 0 */ 69 uint32_t iar1; /* 0x010 rw intr addr reg 1 */ 70 uint32_t irr1; /* 0x014 r intr req reg 1 */ 71 uint32_t imr; /* 0x018 rw intr mask reg */ 72 uint32_t ipr; /* 0x01c rw intr pending reg */ 73 uint32_t toc_addr; /* 0x020 rw TOC addr reg */ 74 uint32_t icr; /* 0x024 rw intr control reg */ 75 uint32_t ilr; /* 0x028 r intr level reg */ 76 uint32_t pad1; /* 0x02c */ 77 uint32_t io_command; /* 0x030 w command register */ 78 uint32_t io_status; /* 0x034 r status register */ 79 uint32_t io_control; /* 0x038 rw control register */ 80 uint32_t pad2; /* 0x03c AUX registers follow */ 81 82 /* HPA Auxiliary Register Set */ 83 uint32_t io_gsc_err_addr;/* 0x040 GSC error address */ 84 uint32_t io_err_info; /* 0x044 error info register */ 85 uint32_t io_pci_err_addr;/* 0x048 PCI error address */ 86 uint32_t pad3[4]; /* 0x04c */ 87 uint32_t io_fbb_en; /* 0x05c fast back2back enable reg */ 88 uint32_t io_addr_en; /* 0x060 address enable reg */ 89 uint32_t pci_addr; /* 0x064 PCI conf/io/mem addr reg */ 90 uint32_t pci_conf_data; /* 0x068 PCI conf data reg */ 91 uint32_t pci_io_data; /* 0x06c PCI io data reg */ 92 uint32_t pci_mem_data; /* 0x070 PCI memory data reg */ 93 uint32_t pad4[0x740/4]; /* 0x074 */ 94 95 /* HPA Bus (GSC) Specific-Dependent Register Set */ 96 uint32_t gsc2x_config; /* 0x7b4 GSC2X config reg */ 97 uint32_t pad5[0x48/4]; /* 0x7b8: BSRS registers follow */ 98 99 /* HPA HVERSION (Dino)-Dependent Register Set */ 100 uint32_t gmask; /* 0x800 GSC arbitration mask */ 101 uint32_t pamr; /* 0x804 PCI arbitration mask */ 102 uint32_t papr; /* 0x808 PCI arbitration priority */ 103 uint32_t damode; /* 0x80c PCI arbitration mode */ 104 uint32_t pcicmd; /* 0x810 PCI command register */ 105 uint32_t pcists; /* 0x814 PCI status register */ 106 uint32_t pad6; /* 0x818 */ 107 uint32_t mltim; /* 0x81c PCI master latency timer */ 108 uint32_t brdg_feat; /* 0x820 PCI bridge feature enable */ 109 uint32_t pciror; /* 0x824 PCI read optimization reg */ 110 uint32_t pciwor; /* 0x828 PCI write optimization reg */ 111 uint32_t pad7; /* 0x82c */ 112 uint32_t tltim; /* 0x830 PCI target latency reg */ 113 }; 114 115 struct dino_softc { 116 device_t sc_dv; 117 118 int sc_ver; 119 void *sc_ih; 120 struct hppa_interrupt_register sc_ir; 121 bus_space_tag_t sc_bt; 122 bus_space_handle_t sc_bh; 123 bus_dma_tag_t sc_dmat; 124 125 struct hppa_bus_dma_tag sc_dmatag; 126 struct hppa_bus_space_tag sc_memt; 127 128 volatile struct dino_regs *sc_regs; 129 130 struct hppa_pci_chipset_tag sc_pc; 131 struct hppa_bus_space_tag sc_iot; 132 133 struct extent *sc_ioex; 134 int sc_memrefcount[30]; 135 136 char sc_ioexname[20]; 137 }; 138 139 int dinomatch(device_t, struct cfdata *, void *); 140 void dinoattach(device_t, device_t, void *); 141 static device_t dino_callback(device_t, struct confargs *); 142 143 CFATTACH_DECL_NEW(dino, sizeof(struct dino_softc), dinomatch, dinoattach, NULL, 144 NULL); 145 146 void dino_attach_hook(device_t, device_t, 147 struct pcibus_attach_args *); 148 void dino_enable_bus(struct dino_softc *, int); 149 int dino_maxdevs(void *, int); 150 pcitag_t dino_make_tag(void *, int, int, int); 151 void dino_decompose_tag(void *, pcitag_t, int *, int *, int *); 152 pcireg_t dino_conf_read(void *, pcitag_t, int); 153 void dino_conf_write(void *, pcitag_t, int, pcireg_t); 154 155 int dino_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 156 const char *dino_intr_string(void *, pci_intr_handle_t, char *, size_t); 157 void *dino_intr_establish(void *, pci_intr_handle_t, int, 158 int (*)(void *), void *); 159 void dino_intr_disestablish(void *, void *); 160 161 void *dino_alloc_parent(device_t, struct pci_attach_args *, int); 162 163 int dino_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 164 int dino_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 165 int dino_subregion(void *, bus_space_handle_t, bus_size_t, bus_size_t, 166 bus_space_handle_t *); 167 int dino_ioalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, 168 bus_size_t, bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 169 int dino_memalloc(void *, bus_addr_t, bus_addr_t, bus_size_t, bus_size_t, 170 bus_size_t, int, bus_addr_t *, bus_space_handle_t *); 171 void dino_unmap(void *, bus_space_handle_t, bus_size_t); 172 void dino_free(void *, bus_space_handle_t, bus_size_t); 173 void dino_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 174 void *dino_vaddr(void *, bus_space_handle_t); 175 paddr_t dino_mmap(void *, bus_addr_t, off_t, int, int); 176 177 uint8_t dino_r1(void *, bus_space_handle_t, bus_size_t); 178 uint16_t dino_r2(void *, bus_space_handle_t, bus_size_t); 179 uint32_t dino_r4(void *, bus_space_handle_t, bus_size_t); 180 uint64_t dino_r8(void *, bus_space_handle_t, bus_size_t); 181 void dino_w1(void *, bus_space_handle_t, bus_size_t, uint8_t); 182 void dino_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 183 void dino_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 184 void dino_w8(void *, bus_space_handle_t, bus_size_t, uint64_t); 185 void dino_rm_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 186 void dino_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 187 void dino_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 188 void dino_rm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 189 void dino_wm_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 190 bus_size_t); 191 void dino_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 192 bus_size_t); 193 void dino_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 194 bus_size_t); 195 void dino_wm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 196 bus_size_t); 197 void dino_sm_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 198 void dino_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 199 void dino_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 200 void dino_sm_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 201 void dino_rrm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 202 bus_size_t); 203 void dino_rrm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 204 bus_size_t); 205 void dino_rrm_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 206 bus_size_t); 207 void dino_wrm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 208 bus_size_t); 209 void dino_wrm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 210 bus_size_t); 211 void dino_wrm_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 212 bus_size_t); 213 void dino_rr_1(void *, bus_space_handle_t, bus_size_t, uint8_t *, bus_size_t); 214 void dino_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 215 void dino_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 216 void dino_rr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, bus_size_t); 217 void dino_wr_1(void *, bus_space_handle_t, bus_size_t, const uint8_t *, 218 bus_size_t); 219 void dino_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 220 bus_size_t); 221 void dino_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 222 bus_size_t); 223 void dino_wr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 224 bus_size_t); 225 void dino_rrr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, 226 bus_size_t); 227 void dino_rrr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, 228 bus_size_t); 229 void dino_rrr_8(void *, bus_space_handle_t, bus_size_t, uint64_t *, 230 bus_size_t); 231 void dino_wrr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, 232 bus_size_t); 233 void dino_wrr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, 234 bus_size_t); 235 void dino_wrr_8(void *, bus_space_handle_t, bus_size_t, const uint64_t *, 236 bus_size_t); 237 void dino_sr_1(void *, bus_space_handle_t, bus_size_t, uint8_t, bus_size_t); 238 void dino_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 239 void dino_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 240 void dino_sr_8(void *, bus_space_handle_t, bus_size_t, uint64_t, bus_size_t); 241 void dino_cp_1(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 242 bus_size_t, bus_size_t); 243 void dino_cp_2(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 244 bus_size_t, bus_size_t); 245 void dino_cp_4(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 246 bus_size_t, bus_size_t); 247 void dino_cp_8(void *, bus_space_handle_t, bus_size_t, bus_space_handle_t, 248 bus_size_t, bus_size_t); 249 int dino_dmamap_create(void *, bus_size_t, int, bus_size_t, bus_size_t, int, 250 bus_dmamap_t *); 251 void dino_dmamap_destroy(void *, bus_dmamap_t); 252 int dino_dmamap_load(void *, bus_dmamap_t, void *, bus_size_t, struct proc *, 253 int); 254 int dino_dmamap_load_mbuf(void *, bus_dmamap_t, struct mbuf *, int); 255 int dino_dmamap_load_uio(void *, bus_dmamap_t, struct uio *, int); 256 int dino_dmamap_load_raw(void *, bus_dmamap_t, bus_dma_segment_t *, int, 257 bus_size_t, int); 258 void dino_dmamap_unload(void *, bus_dmamap_t); 259 void dino_dmamap_sync(void *, bus_dmamap_t, bus_addr_t, bus_size_t, int); 260 int dino_dmamem_alloc(void *, bus_size_t, bus_size_t, bus_size_t, 261 bus_dma_segment_t *, int, int *, int); 262 void dino_dmamem_free(void *, bus_dma_segment_t *, int); 263 int dino_dmamem_map(void *, bus_dma_segment_t *, int, size_t, void **, int); 264 void dino_dmamem_unmap(void *, void *, size_t); 265 paddr_t dino_dmamem_mmap(void *, bus_dma_segment_t *, int, off_t, int, int); 266 267 268 void 269 dino_attach_hook(device_t parent, device_t self, 270 struct pcibus_attach_args *pba) 271 { 272 struct dino_softc *sc = pba->pba_pc->_cookie; 273 274 /* 275 * The firmware enables only devices that are needed for booting. 276 * So other devices will fail to map PCI MEM / IO when they attach. 277 * Therefore we recursively walk all buses to simply enable everything. 278 */ 279 dino_enable_bus(sc, 0); 280 } 281 282 void 283 dino_enable_bus(struct dino_softc *sc, int bus) 284 { 285 int func; 286 int dev; 287 pcitag_t tag; 288 pcireg_t data; 289 pcireg_t class; 290 291 for (dev = 0; dev < 32; dev++) { 292 tag = dino_make_tag(sc, bus, dev, 0); 293 if (tag != -1 && dino_conf_read(sc, tag, 0) != 0xffffffff) { 294 for (func = 0; func < 8; func++) { 295 tag = dino_make_tag(sc, bus, dev, func); 296 if (dino_conf_read(sc, tag, 0) != 0xffffffff) { 297 data = dino_conf_read(sc, tag, 298 PCI_COMMAND_STATUS_REG); 299 dino_conf_write(sc, tag, 300 PCI_COMMAND_STATUS_REG, 301 PCI_COMMAND_IO_ENABLE | 302 PCI_COMMAND_MEM_ENABLE | 303 PCI_COMMAND_MASTER_ENABLE | data); 304 } 305 } 306 class = dino_conf_read(sc, tag, PCI_CLASS_REG); 307 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && 308 PCI_SUBCLASS(class) == PCI_SUBCLASS_BRIDGE_PCI) 309 dino_enable_bus(sc, bus + 1); 310 } 311 } 312 } 313 314 int 315 dino_maxdevs(void *v, int bus) 316 { 317 return 32; 318 } 319 320 pcitag_t 321 dino_make_tag(void *v, int bus, int dev, int func) 322 { 323 if (bus > 255 || dev > 31 || func > 7) 324 panic("dino_make_tag: bad request"); 325 326 return (bus << 16) | (dev << 11) | (func << 8); 327 } 328 329 void 330 dino_decompose_tag(void *v, pcitag_t tag, int *bus, int *dev, int *func) 331 { 332 *bus = (tag >> 16) & 0xff; 333 *dev = (tag >> 11) & 0x1f; 334 *func= (tag >> 8) & 0x07; 335 } 336 337 pcireg_t 338 dino_conf_read(void *v, pcitag_t tag, int reg) 339 { 340 struct dino_softc *sc = v; 341 volatile struct dino_regs *r = sc->sc_regs; 342 pcireg_t data; 343 uint32_t pamr; 344 345 if ((unsigned int)reg >= PCI_CONF_SIZE) 346 return (pcireg_t) -1; 347 348 /* 349 * XXX 350 * accessing dev 1f / func 7 on the 2nd Dino causes a machine check 351 * exception on my C200 352 */ 353 if ((tag & 0xff00) == 0xff00) return -1; 354 355 /* fix arbitration errata by disabling all pci devs on config read */ 356 pamr = r->pamr; 357 r->pamr = 0; 358 359 r->pci_addr = tag | reg; 360 data = r->pci_conf_data; 361 362 /* restore arbitration */ 363 r->pamr = pamr; 364 365 return le32toh(data); 366 } 367 368 void 369 dino_conf_write(void *v, pcitag_t tag, int reg, pcireg_t data) 370 { 371 struct dino_softc *sc = v; 372 volatile struct dino_regs *r = sc->sc_regs; 373 uint32_t pamr; 374 375 if ((unsigned int)reg >= PCI_CONF_SIZE) 376 return; 377 378 /* 379 * XXX 380 * accessing dev 1f / func 7 on the 2nd Dino causes a machine check 381 * exception on my C200 382 */ 383 if ((tag & 0xff00) == 0xff00) return; 384 385 /* fix arbitration errata by disabling all pci devs on config read */ 386 pamr = r->pamr; 387 r->pamr = 0; 388 389 r->pci_addr = tag | reg; 390 r->pci_conf_data = htole32(data); 391 392 /* fix coalescing config and io writes by interleaving w/ a read */ 393 r->pci_addr = tag | PCI_ID_REG; 394 (void)r->pci_conf_data; 395 396 /* restore arbitration */ 397 r->pamr = pamr; 398 } 399 400 int 401 dino_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 402 { 403 int line = pa->pa_intrline; 404 405 if (line == 0xff) 406 return 1; 407 408 *ihp = line; 409 410 return 0; 411 } 412 413 const char * 414 dino_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 415 { 416 snprintf(buf, len, "irq %ld", ih); 417 return buf; 418 } 419 420 extern int cold; 421 422 423 void * 424 dino_intr_establish(void *v, pci_intr_handle_t ih, 425 int pri, int (*handler)(void *), void *arg) 426 { 427 struct dino_softc *sc = v; 428 429 return hppa_intr_establish(pri, handler, arg, &sc->sc_ir, ih); 430 } 431 432 void 433 dino_intr_disestablish(void *v, void *cookie) 434 { 435 /* XXX Implement me */ 436 } 437 438 439 #if NCARDBUS > 0 440 void * 441 dino_alloc_parent(device_t self, struct pci_attach_args *pa, int io) 442 { 443 struct dino_softc *sc = pa->pa_pc->_cookie; 444 struct extent *ex; 445 bus_space_tag_t tag; 446 bus_addr_t start; 447 bus_size_t size; 448 449 if (io) { 450 ex = sc->sc_ioex; 451 tag = pa->pa_iot; 452 start = 0xa000; 453 size = 0x1000; 454 } else { 455 ex = hppa_io_extent; 456 tag = pa->pa_memt; 457 start = ex->ex_start; /* XXX or 0xf0800000? */ 458 size = DINO_MEM_CHUNK; 459 } 460 461 if (extent_alloc_subregion(ex, start, ex->ex_end, size, size, 462 EX_NOBOUNDARY, EX_NOWAIT, &start)) 463 return NULL; 464 extent_free(ex, start, size, EX_NOWAIT); 465 return rbus_new_root_share(tag, ex, start, size, start); 466 } 467 #endif 468 469 int 470 dino_iomap(void *v, bus_addr_t bpa, bus_size_t size, 471 int flags, bus_space_handle_t *bshp) 472 { 473 struct dino_softc *sc = v; 474 int error; 475 476 if (!(flags & BUS_SPACE_MAP_NOEXTENT) && 477 (error = extent_alloc_region(sc->sc_ioex, bpa, size, EX_NOWAIT))) 478 return error; 479 480 if (bshp) 481 *bshp = bpa; 482 483 return 0; 484 } 485 486 int 487 dino_memmap(void *v, bus_addr_t bpa, bus_size_t size, 488 int flags, bus_space_handle_t *bshp) 489 { 490 struct dino_softc *sc = v; 491 volatile struct dino_regs *r = sc->sc_regs; 492 uint32_t reg; 493 int error; 494 495 reg = r->io_addr_en; 496 reg |= 1 << ((bpa >> 23) & 0x1f); 497 #ifdef DEBUG 498 if (reg & 0x80000001) 499 panic("mapping outside the mem extent range"); 500 #endif 501 if ((error = bus_space_map(sc->sc_bt, bpa, size, flags, bshp))) 502 return error; 503 ++sc->sc_memrefcount[((bpa >> 23) & 0x1f)]; 504 /* map into the upper bus space, if not yet mapped this 8M */ 505 if (reg != r->io_addr_en) 506 r->io_addr_en = reg; 507 return 0; 508 } 509 510 int 511 dino_subregion(void *v, bus_space_handle_t bsh, bus_size_t offset, 512 bus_size_t size, bus_space_handle_t *nbshp) 513 { 514 *nbshp = bsh + offset; 515 return 0; 516 } 517 518 int 519 dino_ioalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 520 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 521 bus_space_handle_t *bshp) 522 { 523 struct dino_softc *sc = v; 524 struct extent *ex = sc->sc_ioex; 525 bus_addr_t bpa; 526 int error; 527 528 if (rstart < ex->ex_start || rend > ex->ex_end) 529 panic("dino_ioalloc: bad region start/end"); 530 531 if ((error = extent_alloc_subregion(ex, rstart, rend, size, 532 align, boundary, EX_NOWAIT, &bpa))) 533 return error; 534 535 if (addrp) 536 *addrp = bpa; 537 if (bshp) 538 *bshp = bpa; 539 540 return 0; 541 } 542 543 int 544 dino_memalloc(void *v, bus_addr_t rstart, bus_addr_t rend, bus_size_t size, 545 bus_size_t align, bus_size_t boundary, int flags, bus_addr_t *addrp, 546 bus_space_handle_t *bshp) 547 { 548 struct dino_softc *sc = v; 549 volatile struct dino_regs *r = sc->sc_regs; 550 uint32_t reg; 551 int i, error; 552 553 /* 554 * Allow allocation only when PCI MEM is already mapped. 555 * Needed to avoid allocation of I/O space used by devices that 556 * have no driver in the current kernel. 557 * Dino can map PCI MEM in the range 0xf0800000..0xff800000 only. 558 */ 559 reg = r->io_addr_en; 560 if (rstart < 0xf0800000 || rend >= 0xff800000 || reg == 0) 561 return -1; 562 /* Find used PCI MEM and narrow allocateble region down to it. */ 563 for (i = 1; i < 31; i++) 564 if ((reg & 1 << i) != 0) { 565 rstart = HPPA_IOSPACE | i << 23; 566 rend = (HPPA_IOSPACE | (i + 1) << 23) - 1; 567 break; 568 } 569 if ((error = bus_space_alloc(sc->sc_bt, rstart, rend, size, align, 570 boundary, flags, addrp, bshp))) 571 return error; 572 ++sc->sc_memrefcount[((*bshp >> 23) & 0x1f)]; 573 return 0; 574 } 575 576 void 577 dino_unmap(void *v, bus_space_handle_t bsh, bus_size_t size) 578 { 579 struct dino_softc *sc = v; 580 volatile struct dino_regs *r = sc->sc_regs; 581 582 if (bsh & HPPA_IOSPACE) { 583 bus_space_unmap(sc->sc_bt, bsh, size); 584 if (--sc->sc_memrefcount[((bsh >> 23) & 0x1f)] == 0) 585 /* Unmap the upper PCI MEM space. */ 586 r->io_addr_en &= ~(1 << ((bsh >> 23) & 0x1f)); 587 } else { 588 /* XXX gotta follow the BUS_SPACE_MAP_NOEXTENT flag */ 589 if (extent_free(sc->sc_ioex, bsh, size, EX_NOWAIT)) 590 printf("dino_unmap: ps 0x%lx, size 0x%lx\n" 591 "dino_unmap: can't free region\n", bsh, size); 592 } 593 } 594 595 void 596 dino_free(void *v, bus_space_handle_t bh, bus_size_t size) 597 { 598 /* should be enough */ 599 dino_unmap(v, bh, size); 600 } 601 602 void 603 dino_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 604 { 605 sync_caches(); 606 } 607 608 void* 609 dino_vaddr(void *v, bus_space_handle_t h) 610 { 611 struct dino_softc *sc = v; 612 613 return bus_space_vaddr(sc->sc_bt, h); 614 } 615 616 paddr_t 617 dino_mmap(void *v, bus_addr_t addr, off_t off, int prot, int flags) 618 { 619 return -1; 620 } 621 622 uint8_t 623 dino_r1(void *v, bus_space_handle_t h, bus_size_t o) 624 { 625 h += o; 626 if (h & HPPA_IOSPACE) 627 return *(volatile uint8_t *)h; 628 else { 629 struct dino_softc *sc = v; 630 volatile struct dino_regs *r = sc->sc_regs; 631 632 r->pci_addr = h; 633 return *((volatile uint8_t *)&r->pci_io_data + (h & 3)); 634 } 635 } 636 637 uint16_t 638 dino_r2(void *v, bus_space_handle_t h, bus_size_t o) 639 { 640 volatile uint16_t *p; 641 642 h += o; 643 if (h & HPPA_IOSPACE) 644 p = (volatile uint16_t *)h; 645 else { 646 struct dino_softc *sc = v; 647 volatile struct dino_regs *r = sc->sc_regs; 648 649 r->pci_addr = h; 650 p = (volatile uint16_t *)&r->pci_io_data; 651 if (h & 2) 652 p++; 653 } 654 return le16toh(*p); 655 } 656 657 uint32_t 658 dino_r4(void *v, bus_space_handle_t h, bus_size_t o) 659 { 660 uint32_t data; 661 662 h += o; 663 if (h & HPPA_IOSPACE) 664 data = *(volatile uint32_t *)h; 665 else { 666 struct dino_softc *sc = v; 667 volatile struct dino_regs *r = sc->sc_regs; 668 669 r->pci_addr = h; 670 data = r->pci_io_data; 671 } 672 673 return le32toh(data); 674 } 675 676 uint64_t 677 dino_r8(void *v, bus_space_handle_t h, bus_size_t o) 678 { 679 uint64_t data; 680 681 h += o; 682 if (h & HPPA_IOSPACE) 683 data = *(volatile uint64_t *)h; 684 else 685 panic("dino_r8: not implemented"); 686 687 return le64toh(data); 688 } 689 690 void 691 dino_w1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv) 692 { 693 h += o; 694 if (h & HPPA_IOSPACE) 695 *(volatile uint8_t *)h = vv; 696 else { 697 struct dino_softc *sc = v; 698 volatile struct dino_regs *r = sc->sc_regs; 699 700 r->pci_addr = h; 701 *((volatile uint8_t *)&r->pci_io_data + (h & 3)) = vv; 702 } 703 } 704 705 void 706 dino_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 707 { 708 volatile uint16_t *p; 709 710 h += o; 711 if (h & HPPA_IOSPACE) 712 p = (volatile uint16_t *)h; 713 else { 714 struct dino_softc *sc = v; 715 volatile struct dino_regs *r = sc->sc_regs; 716 717 r->pci_addr = h; 718 p = (volatile uint16_t *)&r->pci_io_data; 719 if (h & 2) 720 p++; 721 } 722 723 *p = htole16(vv); 724 } 725 726 void 727 dino_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 728 { 729 h += o; 730 vv = htole32(vv); 731 if (h & HPPA_IOSPACE) 732 *(volatile uint32_t *)h = vv; 733 else { 734 struct dino_softc *sc = v; 735 volatile struct dino_regs *r = sc->sc_regs; 736 737 r->pci_addr = h; 738 r->pci_io_data = vv; 739 } 740 } 741 742 void 743 dino_w8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv) 744 { 745 h += o; 746 if (h & HPPA_IOSPACE) 747 *(volatile uint64_t *)h = htole64(vv); 748 else 749 panic("dino_w8: not implemented"); 750 } 751 752 753 void 754 dino_rm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 755 { 756 volatile uint8_t *p; 757 758 h += o; 759 if (h & HPPA_IOSPACE) 760 p = (volatile uint8_t *)h; 761 else { 762 struct dino_softc *sc = v; 763 volatile struct dino_regs *r = sc->sc_regs; 764 765 r->pci_addr = h; 766 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 767 } 768 769 while (c--) 770 *a++ = *p; 771 } 772 773 void 774 dino_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 775 { 776 volatile uint16_t *p; 777 778 h += o; 779 if (h & HPPA_IOSPACE) 780 p = (volatile uint16_t *)h; 781 else { 782 struct dino_softc *sc = v; 783 volatile struct dino_regs *r = sc->sc_regs; 784 785 r->pci_addr = h; 786 p = (volatile uint16_t *)&r->pci_io_data; 787 if (h & 2) 788 p++; 789 } 790 791 while (c--) 792 *a++ = le16toh(*p); 793 } 794 795 void 796 dino_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 797 { 798 volatile uint32_t *p; 799 800 h += o; 801 if (h & HPPA_IOSPACE) 802 p = (volatile uint32_t *)h; 803 else { 804 struct dino_softc *sc = v; 805 volatile struct dino_regs *r = sc->sc_regs; 806 807 r->pci_addr = h; 808 p = (volatile uint32_t *)&r->pci_io_data; 809 } 810 811 while (c--) 812 *a++ = le32toh(*p); 813 } 814 815 void 816 dino_rm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 817 { 818 panic("dino_rm_8: not implemented"); 819 } 820 821 void 822 dino_wm_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 823 { 824 volatile uint8_t *p; 825 826 h += o; 827 if (h & HPPA_IOSPACE) 828 p = (volatile uint8_t *)h; 829 else { 830 struct dino_softc *sc = v; 831 volatile struct dino_regs *r = sc->sc_regs; 832 833 r->pci_addr = h; 834 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 835 } 836 837 while (c--) 838 *p = *a++; 839 } 840 841 void 842 dino_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 843 { 844 volatile uint16_t *p; 845 846 h += o; 847 if (h & HPPA_IOSPACE) 848 p = (volatile uint16_t *)h; 849 else { 850 struct dino_softc *sc = v; 851 volatile struct dino_regs *r = sc->sc_regs; 852 853 r->pci_addr = h; 854 p = (volatile uint16_t *)&r->pci_io_data; 855 if (h & 2) 856 p++; 857 } 858 859 while (c--) 860 *p = htole16(*a++); 861 } 862 863 void 864 dino_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 865 { 866 volatile uint32_t *p; 867 868 h += o; 869 if (h & HPPA_IOSPACE) 870 p = (volatile uint32_t *)h; 871 else { 872 struct dino_softc *sc = v; 873 volatile struct dino_regs *r = sc->sc_regs; 874 875 r->pci_addr = h; 876 p = (volatile uint32_t *)&r->pci_io_data; 877 } 878 879 while (c--) 880 *p = htole32(*a++); 881 } 882 883 void 884 dino_wm_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 885 { 886 panic("dino_wm_8: not implemented"); 887 } 888 889 void 890 dino_sm_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 891 { 892 volatile uint8_t *p; 893 894 h += o; 895 if (h & HPPA_IOSPACE) 896 p = (volatile uint8_t *)h; 897 else { 898 struct dino_softc *sc = v; 899 volatile struct dino_regs *r = sc->sc_regs; 900 901 r->pci_addr = h; 902 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 903 } 904 905 while (c--) 906 *p = vv; 907 } 908 909 void 910 dino_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 911 { 912 volatile uint16_t *p; 913 914 h += o; 915 if (h & HPPA_IOSPACE) 916 p = (volatile uint16_t *)h; 917 else { 918 struct dino_softc *sc = v; 919 volatile struct dino_regs *r = sc->sc_regs; 920 921 r->pci_addr = h; 922 p = (volatile uint16_t *)&r->pci_io_data; 923 if (h & 2) 924 p++; 925 } 926 927 while (c--) 928 *p = htole16(vv); 929 } 930 931 void 932 dino_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 933 { 934 volatile uint32_t *p; 935 936 h += o; 937 if (h & HPPA_IOSPACE) 938 p = (volatile uint32_t *)h; 939 else { 940 struct dino_softc *sc = v; 941 volatile struct dino_regs *r = sc->sc_regs; 942 943 r->pci_addr = h; 944 p = (volatile uint32_t *)&r->pci_io_data; 945 } 946 947 while (c--) 948 *p = htole32(vv); 949 } 950 951 void 952 dino_sm_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 953 { 954 panic("dino_sm_8: not implemented"); 955 } 956 957 void 958 dino_rrm_2(void *v, bus_space_handle_t h, bus_size_t o, 959 uint16_t *a, bus_size_t c) 960 { 961 volatile uint16_t *p; 962 963 h += o; 964 if (h & HPPA_IOSPACE) 965 p = (volatile uint16_t *)h; 966 else { 967 struct dino_softc *sc = v; 968 volatile struct dino_regs *r = sc->sc_regs; 969 970 r->pci_addr = h; 971 p = (volatile uint16_t *)&r->pci_io_data; 972 if (h & 2) 973 p++; 974 } 975 976 while (c--) 977 *a++ = *p; 978 } 979 980 void 981 dino_rrm_4(void *v, bus_space_handle_t h, bus_size_t o, 982 uint32_t *a, bus_size_t c) 983 { 984 volatile uint32_t *p; 985 986 h += o; 987 if (h & HPPA_IOSPACE) 988 p = (volatile uint32_t *)h; 989 else { 990 struct dino_softc *sc = v; 991 volatile struct dino_regs *r = sc->sc_regs; 992 993 r->pci_addr = h; 994 p = (volatile uint32_t *)&r->pci_io_data; 995 } 996 997 while (c--) 998 *a++ = *p; 999 } 1000 1001 void 1002 dino_rrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1003 uint64_t *a, bus_size_t c) 1004 { 1005 panic("dino_rrm_8: not implemented"); 1006 } 1007 1008 void 1009 dino_wrm_2(void *v, bus_space_handle_t h, bus_size_t o, 1010 const uint16_t *a, bus_size_t c) 1011 { 1012 volatile uint16_t *p; 1013 1014 h += o; 1015 if (h & HPPA_IOSPACE) 1016 p = (volatile uint16_t *)h; 1017 else { 1018 struct dino_softc *sc = v; 1019 volatile struct dino_regs *r = sc->sc_regs; 1020 1021 r->pci_addr = h; 1022 p = (volatile uint16_t *)&r->pci_io_data; 1023 if (h & 2) 1024 p++; 1025 } 1026 1027 while (c--) 1028 *p = *a++; 1029 } 1030 1031 void 1032 dino_wrm_4(void *v, bus_space_handle_t h, bus_size_t o, 1033 const uint32_t *a, bus_size_t c) 1034 { 1035 volatile uint32_t *p; 1036 1037 h += o; 1038 if (h & HPPA_IOSPACE) 1039 p = (volatile uint32_t *)h; 1040 else { 1041 struct dino_softc *sc = v; 1042 volatile struct dino_regs *r = sc->sc_regs; 1043 1044 r->pci_addr = h; 1045 p = (volatile uint32_t *)&r->pci_io_data; 1046 } 1047 1048 while (c--) 1049 *p = *a++; 1050 } 1051 1052 void 1053 dino_wrm_8(void *v, bus_space_handle_t h, bus_size_t o, 1054 const uint64_t *a, bus_size_t c) 1055 { 1056 panic("dino_wrm_8: not implemented"); 1057 } 1058 1059 void 1060 dino_rr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t *a, bus_size_t c) 1061 { 1062 volatile uint8_t *p; 1063 1064 h += o; 1065 if (h & HPPA_IOSPACE) { 1066 p = (volatile uint8_t *)h; 1067 while (c--) 1068 *a++ = *p++; 1069 } else { 1070 struct dino_softc *sc = v; 1071 volatile struct dino_regs *r = sc->sc_regs; 1072 1073 for (; c--; h++) { 1074 r->pci_addr = h; 1075 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1076 *a++ = *p; 1077 } 1078 } 1079 } 1080 1081 void 1082 dino_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 1083 { 1084 volatile uint16_t *p, data; 1085 1086 h += o; 1087 if (h & HPPA_IOSPACE) { 1088 p = (volatile uint16_t *)h; 1089 while (c--) { 1090 data = *p++; 1091 *a++ = le16toh(data); 1092 } 1093 } else { 1094 struct dino_softc *sc = v; 1095 volatile struct dino_regs *r = sc->sc_regs; 1096 1097 for (; c--; h += 2) { 1098 r->pci_addr = h; 1099 p = (volatile uint16_t *)&r->pci_io_data; 1100 if (h & 2) 1101 p++; 1102 data = *p; 1103 *a++ = le16toh(data); 1104 } 1105 } 1106 } 1107 1108 void 1109 dino_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 1110 { 1111 volatile uint32_t *p, data; 1112 1113 h += o; 1114 if (h & HPPA_IOSPACE) { 1115 p = (volatile uint32_t *)h; 1116 while (c--) { 1117 data = *p++; 1118 *a++ = le32toh(data); 1119 } 1120 } else { 1121 struct dino_softc *sc = v; 1122 volatile struct dino_regs *r = sc->sc_regs; 1123 1124 for (; c--; h += 4) { 1125 r->pci_addr = h; 1126 data = r->pci_io_data; 1127 *a++ = le32toh(data); 1128 } 1129 } 1130 } 1131 1132 void 1133 dino_rr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t *a, bus_size_t c) 1134 { 1135 panic("dino_rr_8: not implemented"); 1136 } 1137 1138 void 1139 dino_wr_1(void *v, bus_space_handle_t h, bus_size_t o, const uint8_t *a, bus_size_t c) 1140 { 1141 volatile uint8_t *p; 1142 1143 h += o; 1144 if (h & HPPA_IOSPACE) { 1145 p = (volatile uint8_t *)h; 1146 while (c--) 1147 *p++ = *a++; 1148 } else { 1149 struct dino_softc *sc = v; 1150 volatile struct dino_regs *r = sc->sc_regs; 1151 1152 for (; c--; h++) { 1153 r->pci_addr = h; 1154 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1155 *p = *a++; 1156 } 1157 } 1158 } 1159 1160 void 1161 dino_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 1162 { 1163 volatile uint16_t *p, data; 1164 1165 h += o; 1166 if (h & HPPA_IOSPACE) { 1167 p = (volatile uint16_t *)h; 1168 while (c--) { 1169 data = *a++; 1170 *p++ = htole16(data); 1171 } 1172 } else { 1173 struct dino_softc *sc = v; 1174 volatile struct dino_regs *r = sc->sc_regs; 1175 1176 for (; c--; h += 2) { 1177 r->pci_addr = h; 1178 p = (volatile uint16_t *)&r->pci_io_data; 1179 if (h & 2) 1180 p++; 1181 data = *a++; 1182 *p = htole16(data); 1183 } 1184 } 1185 } 1186 1187 void 1188 dino_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 1189 { 1190 volatile uint32_t *p, data; 1191 1192 h += o; 1193 if (h & HPPA_IOSPACE) { 1194 p = (volatile uint32_t *)h; 1195 while (c--) { 1196 data = *a++; 1197 *p++ = htole32(data); 1198 } 1199 } else { 1200 struct dino_softc *sc = v; 1201 volatile struct dino_regs *r = sc->sc_regs; 1202 1203 for (; c--; h += 4) { 1204 r->pci_addr = h; 1205 data = *a++; 1206 r->pci_io_data = htole32(data); 1207 } 1208 } 1209 } 1210 1211 void 1212 dino_wr_8(void *v, bus_space_handle_t h, bus_size_t o, const uint64_t *a, bus_size_t c) 1213 { 1214 panic("dino_wr_8: not implemented"); 1215 } 1216 1217 void 1218 dino_rrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1219 uint16_t *a, bus_size_t c) 1220 { 1221 volatile uint16_t *p; 1222 1223 h += o; 1224 if (h & HPPA_IOSPACE) { 1225 p = (volatile uint16_t *)h; 1226 while (c--) 1227 *a++ = *p++; 1228 } else { 1229 struct dino_softc *sc = v; 1230 volatile struct dino_regs *r = sc->sc_regs; 1231 1232 for (; c--; h += 2) { 1233 r->pci_addr = h; 1234 p = (volatile uint16_t *)&r->pci_io_data; 1235 if (h & 2) 1236 p++; 1237 *a++ = *p; 1238 } 1239 } 1240 } 1241 1242 void 1243 dino_rrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1244 uint32_t *a, bus_size_t c) 1245 { 1246 volatile uint32_t *p; 1247 1248 h += o; 1249 if (h & HPPA_IOSPACE) { 1250 p = (volatile uint32_t *)h; 1251 while (c--) 1252 *a++ = *p++; 1253 } else { 1254 struct dino_softc *sc = v; 1255 volatile struct dino_regs *r = sc->sc_regs; 1256 1257 for (; c--; h += 4) { 1258 r->pci_addr = h; 1259 *a++ = r->pci_io_data; 1260 } 1261 } 1262 } 1263 1264 void 1265 dino_rrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1266 uint64_t *a, bus_size_t c) 1267 { 1268 panic("dino_rrr_8: not implemented"); 1269 } 1270 1271 void 1272 dino_wrr_2(void *v, bus_space_handle_t h, bus_size_t o, 1273 const uint16_t *a, bus_size_t c) 1274 { 1275 volatile uint16_t *p; 1276 1277 h += o; 1278 if (h & HPPA_IOSPACE) { 1279 p = (volatile uint16_t *)h; 1280 while (c--) 1281 *p++ = *a++; 1282 } else { 1283 struct dino_softc *sc = v; 1284 volatile struct dino_regs *r = sc->sc_regs; 1285 1286 for (; c--; h += 2) { 1287 r->pci_addr = h; 1288 p = (volatile uint16_t *)&r->pci_io_data; 1289 if (h & 2) 1290 p++; 1291 *p = *a++; 1292 } 1293 } 1294 } 1295 1296 void 1297 dino_wrr_4(void *v, bus_space_handle_t h, bus_size_t o, 1298 const uint32_t *a, bus_size_t c) 1299 { 1300 volatile uint32_t *p; 1301 1302 c /= 4; 1303 h += o; 1304 if (h & HPPA_IOSPACE) { 1305 p = (volatile uint32_t *)h; 1306 while (c--) 1307 *p++ = *a++; 1308 } else { 1309 struct dino_softc *sc = v; 1310 volatile struct dino_regs *r = sc->sc_regs; 1311 1312 for (; c--; h += 4) { 1313 r->pci_addr = h; 1314 r->pci_io_data = *a++; 1315 } 1316 } 1317 } 1318 1319 void 1320 dino_wrr_8(void *v, bus_space_handle_t h, bus_size_t o, 1321 const uint64_t *a, bus_size_t c) 1322 { 1323 panic("dino_wrr_8: not implemented"); 1324 } 1325 1326 void 1327 dino_sr_1(void *v, bus_space_handle_t h, bus_size_t o, uint8_t vv, bus_size_t c) 1328 { 1329 volatile uint8_t *p; 1330 1331 h += o; 1332 if (h & HPPA_IOSPACE) { 1333 p = (volatile uint8_t *)h; 1334 while (c--) 1335 *p++ = vv; 1336 } else { 1337 struct dino_softc *sc = v; 1338 volatile struct dino_regs *r = sc->sc_regs; 1339 1340 for (; c--; h++) { 1341 r->pci_addr = h; 1342 p = (volatile uint8_t *)&r->pci_io_data + (h & 3); 1343 *p = vv; 1344 } 1345 } 1346 } 1347 1348 void 1349 dino_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 1350 { 1351 volatile uint16_t *p; 1352 1353 h += o; 1354 vv = htole16(vv); 1355 if (h & HPPA_IOSPACE) { 1356 p = (volatile uint16_t *)h; 1357 while (c--) 1358 *p++ = vv; 1359 } else { 1360 struct dino_softc *sc = v; 1361 volatile struct dino_regs *r = sc->sc_regs; 1362 1363 for (; c--; h += 2) { 1364 r->pci_addr = h; 1365 p = (volatile uint16_t *)&r->pci_io_data; 1366 if (h & 2) 1367 p++; 1368 *p = vv; 1369 } 1370 } 1371 } 1372 1373 void 1374 dino_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 1375 { 1376 volatile uint32_t *p; 1377 1378 h += o; 1379 vv = htole32(vv); 1380 if (h & HPPA_IOSPACE) { 1381 p = (volatile uint32_t *)h; 1382 while (c--) 1383 *p++ = vv; 1384 } else { 1385 struct dino_softc *sc = v; 1386 volatile struct dino_regs *r = sc->sc_regs; 1387 1388 for (; c--; h += 4) { 1389 r->pci_addr = h; 1390 r->pci_io_data = vv; 1391 } 1392 } 1393 } 1394 1395 void 1396 dino_sr_8(void *v, bus_space_handle_t h, bus_size_t o, uint64_t vv, bus_size_t c) 1397 { 1398 panic("dino_sr_8: not implemented"); 1399 } 1400 1401 void 1402 dino_cp_1(void *v, bus_space_handle_t h1, bus_size_t o1, 1403 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1404 { 1405 while (c--) 1406 dino_w1(v, h1, o1++, dino_r1(v, h2, o2++)); 1407 } 1408 1409 void 1410 dino_cp_2(void *v, bus_space_handle_t h1, bus_size_t o1, 1411 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1412 { 1413 while (c--) { 1414 dino_w2(v, h1, o1, dino_r2(v, h2, o2)); 1415 o1 += 2; 1416 o2 += 2; 1417 } 1418 } 1419 1420 void 1421 dino_cp_4(void *v, bus_space_handle_t h1, bus_size_t o1, 1422 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1423 { 1424 while (c--) { 1425 dino_w4(v, h1, o1, dino_r4(v, h2, o2)); 1426 o1 += 4; 1427 o2 += 4; 1428 } 1429 } 1430 1431 void 1432 dino_cp_8(void *v, bus_space_handle_t h1, bus_size_t o1, 1433 bus_space_handle_t h2, bus_size_t o2, bus_size_t c) 1434 { 1435 while (c--) { 1436 dino_w8(v, h1, o1, dino_r8(v, h2, o2)); 1437 o1 += 8; 1438 o2 += 8; 1439 } 1440 } 1441 1442 1443 const struct hppa_bus_space_tag dino_iomemt = { 1444 NULL, 1445 1446 NULL, dino_unmap, dino_subregion, NULL, dino_free, 1447 dino_barrier, dino_vaddr, dino_mmap, 1448 dino_r1, dino_r2, dino_r4, dino_r8, 1449 dino_w1, dino_w2, dino_w4, dino_w8, 1450 dino_rm_1, dino_rm_2, dino_rm_4, dino_rm_8, 1451 dino_wm_1, dino_wm_2, dino_wm_4, dino_wm_8, 1452 dino_sm_1, dino_sm_2, dino_sm_4, dino_sm_8, 1453 dino_rrm_2, dino_rrm_4, dino_rrm_8, 1454 dino_wrm_2, dino_wrm_4, dino_wrm_8, 1455 dino_rr_1, dino_rr_2, dino_rr_4, dino_rr_8, 1456 dino_wr_1, dino_wr_2, dino_wr_4, dino_wr_8, 1457 dino_rrr_2, dino_rrr_4, dino_rrr_8, 1458 dino_wrr_2, dino_wrr_4, dino_wrr_8, 1459 dino_sr_1, dino_sr_2, dino_sr_4, dino_sr_8, 1460 dino_cp_1, dino_cp_2, dino_cp_4, dino_cp_8 1461 }; 1462 1463 int 1464 dino_dmamap_create(void *v, bus_size_t size, int nsegments, 1465 bus_size_t maxsegsz, bus_size_t boundary, int flags, bus_dmamap_t *dmamp) 1466 { 1467 struct dino_softc *sc = v; 1468 1469 /* TODO check the addresses, boundary, enable dma */ 1470 1471 return bus_dmamap_create(sc->sc_dmat, size, nsegments, 1472 maxsegsz, boundary, flags, dmamp); 1473 } 1474 1475 void 1476 dino_dmamap_destroy(void *v, bus_dmamap_t map) 1477 { 1478 struct dino_softc *sc = v; 1479 1480 bus_dmamap_destroy(sc->sc_dmat, map); 1481 } 1482 1483 int 1484 dino_dmamap_load(void *v, bus_dmamap_t map, void *addr, bus_size_t size, 1485 struct proc *p, int flags) 1486 { 1487 struct dino_softc *sc = v; 1488 1489 return bus_dmamap_load(sc->sc_dmat, map, addr, size, p, flags); 1490 } 1491 1492 int 1493 dino_dmamap_load_mbuf(void *v, bus_dmamap_t map, struct mbuf *m, int flags) 1494 { 1495 struct dino_softc *sc = v; 1496 1497 return bus_dmamap_load_mbuf(sc->sc_dmat, map, m, flags); 1498 } 1499 1500 int 1501 dino_dmamap_load_uio(void *v, bus_dmamap_t map, struct uio *uio, int flags) 1502 { 1503 struct dino_softc *sc = v; 1504 1505 return bus_dmamap_load_uio(sc->sc_dmat, map, uio, flags); 1506 } 1507 1508 int 1509 dino_dmamap_load_raw(void *v, bus_dmamap_t map, bus_dma_segment_t *segs, 1510 int nsegs, bus_size_t size, int flags) 1511 { 1512 struct dino_softc *sc = v; 1513 1514 return bus_dmamap_load_raw(sc->sc_dmat, map, segs, nsegs, size, flags); 1515 } 1516 1517 void 1518 dino_dmamap_unload(void *v, bus_dmamap_t map) 1519 { 1520 struct dino_softc *sc = v; 1521 1522 bus_dmamap_unload(sc->sc_dmat, map); 1523 } 1524 1525 void 1526 dino_dmamap_sync(void *v, bus_dmamap_t map, bus_addr_t off, 1527 bus_size_t len, int ops) 1528 { 1529 struct dino_softc *sc = v; 1530 1531 return bus_dmamap_sync(sc->sc_dmat, map, off, len, ops); 1532 } 1533 1534 int 1535 dino_dmamem_alloc(void *v, bus_size_t size, bus_size_t alignment, 1536 bus_size_t boundary, bus_dma_segment_t *segs, 1537 int nsegs, int *rsegs, int flags) 1538 { 1539 struct dino_softc *sc = v; 1540 1541 return bus_dmamem_alloc(sc->sc_dmat, size, alignment, boundary, 1542 segs, nsegs, rsegs, flags); 1543 } 1544 1545 void 1546 dino_dmamem_free(void *v, bus_dma_segment_t *segs, int nsegs) 1547 { 1548 struct dino_softc *sc = v; 1549 1550 bus_dmamem_free(sc->sc_dmat, segs, nsegs); 1551 } 1552 1553 int 1554 dino_dmamem_map(void *v, bus_dma_segment_t *segs, int nsegs, size_t size, 1555 void **kvap, int flags) 1556 { 1557 struct dino_softc *sc = v; 1558 1559 return bus_dmamem_map(sc->sc_dmat, segs, nsegs, size, kvap, flags); 1560 } 1561 1562 void 1563 dino_dmamem_unmap(void *v, void *kva, size_t size) 1564 { 1565 struct dino_softc *sc = v; 1566 1567 bus_dmamem_unmap(sc->sc_dmat, kva, size); 1568 } 1569 1570 paddr_t 1571 dino_dmamem_mmap(void *v, bus_dma_segment_t *segs, int nsegs, off_t off, 1572 int prot, int flags) 1573 { 1574 struct dino_softc *sc = v; 1575 1576 return bus_dmamem_mmap(sc->sc_dmat, segs, nsegs, off, prot, flags); 1577 } 1578 1579 const struct hppa_bus_dma_tag dino_dmat = { 1580 NULL, 1581 dino_dmamap_create, dino_dmamap_destroy, 1582 dino_dmamap_load, dino_dmamap_load_mbuf, 1583 dino_dmamap_load_uio, dino_dmamap_load_raw, 1584 dino_dmamap_unload, dino_dmamap_sync, 1585 1586 dino_dmamem_alloc, dino_dmamem_free, dino_dmamem_map, 1587 dino_dmamem_unmap, dino_dmamem_mmap 1588 }; 1589 1590 const struct hppa_pci_chipset_tag dino_pc = { 1591 NULL, 1592 dino_attach_hook, dino_maxdevs, dino_make_tag, dino_decompose_tag, 1593 dino_conf_read, dino_conf_write, 1594 dino_intr_map, dino_intr_string, 1595 dino_intr_establish, dino_intr_disestablish, 1596 #if NCARDBUS > 0 1597 dino_alloc_parent 1598 #else 1599 NULL 1600 #endif 1601 }; 1602 1603 int 1604 dinomatch(device_t parent, cfdata_t cfdata, void *aux) 1605 { 1606 struct confargs *ca = aux; 1607 1608 /* there will be only one */ 1609 if (ca->ca_type.iodc_type != HPPA_TYPE_BRIDGE || 1610 ca->ca_type.iodc_sv_model != HPPA_BRIDGE_DINO) 1611 return 0; 1612 1613 /* do not match on the elroy family */ 1614 if (ca->ca_type.iodc_model == 0x78) 1615 return 0; 1616 1617 return 1; 1618 } 1619 1620 void 1621 dinoattach(device_t parent, device_t self, void *aux) 1622 { 1623 struct dino_softc *sc = device_private(self); 1624 struct confargs *ca = (struct confargs *)aux, nca; 1625 struct pcibus_attach_args pba; 1626 volatile struct dino_regs *r; 1627 struct cpu_info *ci = &cpus[0]; 1628 const char *p = NULL; 1629 int s, ver; 1630 1631 sc->sc_dv = self; 1632 sc->sc_bt = ca->ca_iot; 1633 sc->sc_dmat = ca->ca_dmatag; 1634 1635 ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 1636 if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 1637 aprint_error_dev(self, ": can't allocate interrupt"); 1638 return; 1639 } 1640 1641 if (bus_space_map(sc->sc_bt, ca->ca_hpa, PAGE_SIZE, 0, &sc->sc_bh)) { 1642 aprint_error(": can't map space\n"); 1643 return; 1644 } 1645 1646 sc->sc_regs = r = (volatile struct dino_regs *)sc->sc_bh; 1647 #ifdef trust_the_firmware_to_proper_initialize_everything 1648 r->io_addr_en = 0; 1649 r->io_control = 0x80; 1650 r->pamr = 0; 1651 r->papr = 0; 1652 r->io_fbb_en |= 1; 1653 r->damode = 0; 1654 r->gmask &= ~1; /* allow GSC bus req */ 1655 r->pciror = 0; 1656 r->pciwor = 0; 1657 r->brdg_feat = 0xc0000000; 1658 #endif 1659 1660 snprintf(sc->sc_ioexname, sizeof(sc->sc_ioexname), 1661 "%s_io", device_xname(self)); 1662 sc->sc_ioex = extent_create(sc->sc_ioexname, 0, 0xffff, 1663 NULL, 0, EX_WAITOK | EX_MALLOCOK); 1664 1665 /* interrupts guts */ 1666 s = splhigh(); 1667 r->icr = 0; 1668 r->imr = 0; 1669 (void)r->irr0; 1670 r->iar0 = ci->ci_hpa | (31 - ca->ca_irq); 1671 splx(s); 1672 /* Establish the interrupt register. */ 1673 hppa_interrupt_register_establish(ci, &sc->sc_ir); 1674 sc->sc_ir.ir_name = device_xname(self); 1675 sc->sc_ir.ir_mask = &r->imr; 1676 sc->sc_ir.ir_req = &r->irr0; 1677 sc->sc_ir.ir_level = &r->ilr; 1678 /* Add the I/O interrupt register. */ 1679 1680 sc->sc_ih = hppa_intr_establish(IPL_NONE, NULL, &sc->sc_ir, 1681 &ci->ci_ir, ca->ca_irq); 1682 1683 /* TODO establish the bus error interrupt */ 1684 1685 ver = ca->ca_type.iodc_revision; 1686 switch ((ca->ca_type.iodc_model << 4) | 1687 (ca->ca_type.iodc_revision >> 4)) { 1688 case 0x05d: 1689 p = "Dino (card)"; /* j2240 */ 1690 /* FALLTHROUGH */ 1691 case 0x680: 1692 if (!p) 1693 p = "Dino"; 1694 switch (ver & 0xf) { 1695 case 0: ver = 0x20; break; 1696 case 1: ver = 0x21; break; 1697 case 2: ver = 0x30; break; 1698 case 3: ver = 0x31; break; 1699 } 1700 break; 1701 1702 case 0x682: 1703 p = "Cujo"; 1704 switch (ver & 0xf) { 1705 case 0: ver = 0x10; break; 1706 case 1: ver = 0x20; break; 1707 } 1708 break; 1709 1710 default: 1711 p = "Mojo"; 1712 break; 1713 } 1714 1715 sc->sc_ver = ver; 1716 aprint_normal(": %s V%d.%d\n", p, ver >> 4, ver & 0xf); 1717 1718 sc->sc_iot = dino_iomemt; 1719 sc->sc_iot.hbt_cookie = sc; 1720 sc->sc_iot.hbt_map = dino_iomap; 1721 sc->sc_iot.hbt_alloc = dino_ioalloc; 1722 sc->sc_memt = dino_iomemt; 1723 sc->sc_memt.hbt_cookie = sc; 1724 sc->sc_memt.hbt_map = dino_memmap; 1725 sc->sc_memt.hbt_alloc = dino_memalloc; 1726 sc->sc_pc = dino_pc; 1727 sc->sc_pc._cookie = sc; 1728 sc->sc_dmatag = dino_dmat; 1729 sc->sc_dmatag._cookie = sc; 1730 1731 /* scan for ps2 kbd/ms, serial, and flying toasters */ 1732 nca = *ca; 1733 1734 nca.ca_hpabase = 0; 1735 nca.ca_nmodules = MAXMODBUS; 1736 pdc_scanbus(self, &nca, dino_callback); 1737 1738 memset(&pba, 0, sizeof(pba)); 1739 pba.pba_iot = &sc->sc_iot; 1740 pba.pba_memt = &sc->sc_memt; 1741 pba.pba_dmat = &sc->sc_dmatag; 1742 pba.pba_pc = &sc->sc_pc; 1743 pba.pba_bus = 0; 1744 pba.pba_flags = PCI_FLAGS_IO_OKAY | PCI_FLAGS_MEM_OKAY; 1745 config_found_ia(self, "pcibus", &pba, pcibusprint); 1746 } 1747 1748 static device_t 1749 dino_callback(device_t self, struct confargs *ca) 1750 { 1751 return config_found_sm_loc(self, "gedoens", NULL, ca, mbprint, mbsubmatch); 1752 } 1753
Indexes created Wed Sep 24 15:09:51 GMT 2025