mem.c revision 1.1.10.2
1 1.1.10.2 tls /* $NetBSD: mem.c,v 1.1.10.2 2014/08/20 00:03:04 tls Exp $ */ 2 1.1.10.2 tls 3 1.1.10.2 tls /* $OpenBSD: mem.c,v 1.30 2007/09/22 16:21:32 krw Exp $ */ 4 1.1.10.2 tls /* 5 1.1.10.2 tls * Copyright (c) 1998-2004 Michael Shalayeff 6 1.1.10.2 tls * All rights reserved. 7 1.1.10.2 tls * 8 1.1.10.2 tls * Redistribution and use in source and binary forms, with or without 9 1.1.10.2 tls * modification, are permitted provided that the following conditions 10 1.1.10.2 tls * are met: 11 1.1.10.2 tls * 1. Redistributions of source code must retain the above copyright 12 1.1.10.2 tls * notice, this list of conditions and the following disclaimer. 13 1.1.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 14 1.1.10.2 tls * notice, this list of conditions and the following disclaimer in the 15 1.1.10.2 tls * documentation and/or other materials provided with the distribution. 16 1.1.10.2 tls * 17 1.1.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 1.1.10.2 tls * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 1.1.10.2 tls * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 1.1.10.2 tls * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 21 1.1.10.2 tls * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 22 1.1.10.2 tls * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 23 1.1.10.2 tls * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 1.1.10.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 25 1.1.10.2 tls * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 1.1.10.2 tls * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 1.1.10.2 tls * THE POSSIBILITY OF SUCH DAMAGE. 28 1.1.10.2 tls */ 29 1.1.10.2 tls /* 30 1.1.10.2 tls * Copyright (c) 1991,1992,1994, The University of Utah and 31 1.1.10.2 tls * the Computer Systems Laboratory (CSL). All rights reserved. 32 1.1.10.2 tls * 33 1.1.10.2 tls * Subject to your agreements with CMU, 34 1.1.10.2 tls * permission to use, copy, modify and distribute this software and its 35 1.1.10.2 tls * documentation is hereby granted, provided that both the copyright 36 1.1.10.2 tls * notice and this permission notice appear in all copies of the 37 1.1.10.2 tls * software, derivative works or modified versions, and any portions 38 1.1.10.2 tls * thereof, and that both notices appear in supporting documentation. 39 1.1.10.2 tls * 40 1.1.10.2 tls * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 41 1.1.10.2 tls * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 42 1.1.10.2 tls * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 43 1.1.10.2 tls * 44 1.1.10.2 tls * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 45 1.1.10.2 tls * improvements that they make and grant CSL redistribution rights. 46 1.1.10.2 tls * 47 1.1.10.2 tls * Utah $Hdr: mem.c 1.9 94/12/16$ 48 1.1.10.2 tls */ 49 1.1.10.2 tls /* 50 1.1.10.2 tls * Mach Operating System 51 1.1.10.2 tls * Copyright (c) 1992 Carnegie Mellon University 52 1.1.10.2 tls * All Rights Reserved. 53 1.1.10.2 tls * 54 1.1.10.2 tls * Permission to use, copy, modify and distribute this software and its 55 1.1.10.2 tls * documentation is hereby granted, provided that both the copyright 56 1.1.10.2 tls * notice and this permission notice appear in all copies of the 57 1.1.10.2 tls * software, derivative works or modified versions, and any portions 58 1.1.10.2 tls * thereof, and that both notices appear in supporting documentation. 59 1.1.10.2 tls * 60 1.1.10.2 tls * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 61 1.1.10.2 tls * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 62 1.1.10.2 tls * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 63 1.1.10.2 tls * 64 1.1.10.2 tls * Carnegie Mellon requests users of this software to return to 65 1.1.10.2 tls * 66 1.1.10.2 tls * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 67 1.1.10.2 tls * School of Computer Science 68 1.1.10.2 tls * Carnegie Mellon University 69 1.1.10.2 tls * Pittsburgh PA 15213-3890 70 1.1.10.2 tls * 71 1.1.10.2 tls * any improvements or extensions that they make and grant Carnegie Mellon 72 1.1.10.2 tls * the rights to redistribute these changes. 73 1.1.10.2 tls */ 74 1.1.10.2 tls 75 1.1.10.2 tls #include <sys/cdefs.h> 76 1.1.10.2 tls __KERNEL_RCSID(0, "$NetBSD: mem.c,v 1.1.10.2 2014/08/20 00:03:04 tls Exp $"); 77 1.1.10.2 tls 78 1.1.10.2 tls #include <sys/param.h> 79 1.1.10.2 tls #include <sys/systm.h> 80 1.1.10.2 tls #include <sys/buf.h> 81 1.1.10.2 tls #include <sys/conf.h> 82 1.1.10.2 tls #include <sys/malloc.h> 83 1.1.10.2 tls #include <sys/proc.h> 84 1.1.10.2 tls #include <sys/uio.h> 85 1.1.10.2 tls #include <sys/types.h> 86 1.1.10.2 tls #include <sys/device.h> 87 1.1.10.2 tls #include <sys/errno.h> 88 1.1.10.2 tls #include <sys/ioctl.h> 89 1.1.10.2 tls #include <sys/file.h> 90 1.1.10.2 tls #include <sys/bus.h> 91 1.1.10.2 tls #include <sys/mutex.h> 92 1.1.10.2 tls 93 1.1.10.2 tls #include <uvm/uvm.h> 94 1.1.10.2 tls 95 1.1.10.2 tls #include <machine/iomod.h> 96 1.1.10.2 tls #include <machine/autoconf.h> 97 1.1.10.2 tls #include <machine/pmap.h> 98 1.1.10.2 tls 99 1.1.10.2 tls #include <hppa/hppa/machdep.h> 100 1.1.10.2 tls #include <hppa/dev/cpudevs.h> 101 1.1.10.2 tls #include <hppa/dev/viper.h> 102 1.1.10.2 tls 103 1.1.10.2 tls /* registers on the PCXL2 MIOC */ 104 1.1.10.2 tls struct l2_mioc { 105 1.1.10.2 tls uint32_t pad[0x20]; /* 0x000 */ 106 1.1.10.2 tls uint32_t mioc_control; /* 0x080 MIOC control bits */ 107 1.1.10.2 tls uint32_t mioc_status; /* 0x084 MIOC status bits */ 108 1.1.10.2 tls uint32_t pad1[6]; /* 0x088 */ 109 1.1.10.2 tls uint32_t sltcv; /* 0x0a0 L2 cache control */ 110 1.1.10.2 tls #define SLTCV_AVWL 0x00002000 /* extra cycle for addr valid write low */ 111 1.1.10.2 tls #define SLTCV_UP4COUT 0x00001000 /* update cache on CPU castouts */ 112 1.1.10.2 tls #define SLTCV_EDCEN 0x08000000 /* enable error correction */ 113 1.1.10.2 tls #define SLTCV_EDTAG 0x10000000 /* enable diagtag */ 114 1.1.10.2 tls #define SLTCV_CHKTP 0x20000000 /* enable parity checking */ 115 1.1.10.2 tls #define SLTCV_LOWPWR 0x40000000 /* low power mode */ 116 1.1.10.2 tls #define SLTCV_ENABLE 0x80000000 /* enable L2 cache */ 117 1.1.10.2 tls #define SLTCV_BITS "\020\15avwl\16up4cout\24edcen\25edtag\26chktp\27lowpwr\30l2ena" 118 1.1.10.2 tls uint32_t tagmask; /* 0x0a4 L2 cache tag mask */ 119 1.1.10.2 tls uint32_t diagtag; /* 0x0a8 L2 invalidates tag */ 120 1.1.10.2 tls uint32_t sltestat; /* 0x0ac L2 last logged tag read */ 121 1.1.10.2 tls uint32_t slteadd; /* 0x0b0 L2 pa of -- " -- */ 122 1.1.10.2 tls uint32_t pad2[3]; /* 0x0b4 */ 123 1.1.10.2 tls uint32_t mtcv; /* 0x0c0 MIOC timings */ 124 1.1.10.2 tls uint32_t ref; /* 0x0cc MIOC refresh timings */ 125 1.1.10.2 tls uint32_t pad3[4]; /* 0x0d0 */ 126 1.1.10.2 tls uint32_t mderradd; /* 0x0e0 addr of most evil mem error */ 127 1.1.10.2 tls uint32_t pad4; /* 0x0e4 */ 128 1.1.10.2 tls uint32_t dmaerr; /* 0x0e8 addr of most evil dma error */ 129 1.1.10.2 tls uint32_t dioerr; /* 0x0ec addr of most evil dio error */ 130 1.1.10.2 tls uint32_t gsc_timeout; /* 0x0f0 1-compl of GSC timeout delay */ 131 1.1.10.2 tls uint32_t hidmamem; /* 0x0f4 amount of phys mem installed */ 132 1.1.10.2 tls uint32_t pad5[2]; /* 0x0f8 */ 133 1.1.10.2 tls uint32_t memcomp[16]; /* 0x100 memory address comparators */ 134 1.1.10.2 tls uint32_t memmask[16]; /* 0x140 masks for -- " -- */ 135 1.1.10.2 tls uint32_t memtest; /* 0x180 test address decoding */ 136 1.1.10.2 tls uint32_t pad6[0xf]; /* 0x184 */ 137 1.1.10.2 tls uint32_t outchk; /* 0x1c0 address decoding output */ 138 1.1.10.2 tls uint32_t pad7[0x168]; /* 0x200 */ 139 1.1.10.2 tls uint32_t gsc15x_config; /* 0x7a0 writev enable */ 140 1.1.10.2 tls }; 141 1.1.10.2 tls 142 1.1.10.2 tls struct mem_softc { 143 1.1.10.2 tls device_t sc_dev; 144 1.1.10.2 tls 145 1.1.10.2 tls volatile struct vi_trs *sc_vp; 146 1.1.10.2 tls volatile struct l2_mioc *sc_l2; 147 1.1.10.2 tls }; 148 1.1.10.2 tls 149 1.1.10.2 tls int memmatch(device_t, cfdata_t, void *); 150 1.1.10.2 tls void memattach(device_t, device_t, void *); 151 1.1.10.2 tls 152 1.1.10.2 tls CFATTACH_DECL_NEW(mem, sizeof(struct mem_softc), memmatch, memattach, 153 1.1.10.2 tls NULL, NULL); 154 1.1.10.2 tls 155 1.1.10.2 tls int 156 1.1.10.2 tls memmatch(device_t parent, cfdata_t cf, void *aux) 157 1.1.10.2 tls { 158 1.1.10.2 tls struct confargs *ca = aux; 159 1.1.10.2 tls 160 1.1.10.2 tls if (ca->ca_type.iodc_type != HPPA_TYPE_MEMORY || 161 1.1.10.2 tls ca->ca_type.iodc_sv_model != HPPA_MEMORY_PDEP) 162 1.1.10.2 tls return 0; 163 1.1.10.2 tls return 1; 164 1.1.10.2 tls } 165 1.1.10.2 tls 166 1.1.10.2 tls void 167 1.1.10.2 tls memattach(device_t parent, device_t self, void *aux) 168 1.1.10.2 tls { 169 1.1.10.2 tls struct pdc_iodc_minit pdc_minit; 170 1.1.10.2 tls struct confargs *ca = aux; 171 1.1.10.2 tls struct mem_softc *sc = device_private(self); 172 1.1.10.2 tls int err, pagezero_cookie; 173 1.1.10.2 tls char bits[128]; 174 1.1.10.2 tls 175 1.1.10.2 tls sc->sc_dev = self; 176 1.1.10.2 tls 177 1.1.10.2 tls aprint_normal(":"); 178 1.1.10.2 tls 179 1.1.10.2 tls pagezero_cookie = hppa_pagezero_map(); 180 1.1.10.2 tls 181 1.1.10.2 tls /* XXX check if we are dealing w/ Viper */ 182 1.1.10.2 tls if (ca->ca_hpa == (hppa_hpa_t)VIPER_HPA) { 183 1.1.10.2 tls 184 1.1.10.2 tls sc->sc_vp = (struct vi_trs *) 185 1.1.10.2 tls &((struct iomod *)ca->ca_hpa)->priv_trs; 186 1.1.10.2 tls 187 1.1.10.2 tls /* XXX other values seem to blow it up */ 188 1.1.10.2 tls if (sc->sc_vp->vi_status.hw_rev == 0) { 189 1.1.10.2 tls uint32_t vic; 190 1.1.10.2 tls int s, settimeout; 191 1.1.10.2 tls 192 1.1.10.2 tls switch (cpu_modelno) { 193 1.1.10.2 tls case HPPA_BOARD_HP715_33: 194 1.1.10.2 tls case HPPA_BOARD_HP715S_33: 195 1.1.10.2 tls case HPPA_BOARD_HP715T_33: 196 1.1.10.2 tls case HPPA_BOARD_HP715_50: 197 1.1.10.2 tls case HPPA_BOARD_HP715S_50: 198 1.1.10.2 tls case HPPA_BOARD_HP715T_50: 199 1.1.10.2 tls case HPPA_BOARD_HP715_75: 200 1.1.10.2 tls case HPPA_BOARD_HP725_50: 201 1.1.10.2 tls case HPPA_BOARD_HP725_75: 202 1.1.10.2 tls settimeout = 1; 203 1.1.10.2 tls break; 204 1.1.10.2 tls default: 205 1.1.10.2 tls settimeout = 0; 206 1.1.10.2 tls break; 207 1.1.10.2 tls } 208 1.1.10.2 tls if (device_cfdata(self)->cf_flags & 1) 209 1.1.10.2 tls settimeout = !settimeout; 210 1.1.10.2 tls 211 1.1.10.2 tls snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL); 212 1.1.10.2 tls aprint_normal(" viper rev %x, ctrl %s", 213 1.1.10.2 tls sc->sc_vp->vi_status.hw_rev, bits); 214 1.1.10.2 tls 215 1.1.10.2 tls s = splhigh(); 216 1.1.10.2 tls vic = VI_CTRL; 217 1.1.10.2 tls ((struct vi_ctrl *)&vic)->core_den = 0; 218 1.1.10.2 tls ((struct vi_ctrl *)&vic)->sgc0_den = 0; 219 1.1.10.2 tls ((struct vi_ctrl *)&vic)->sgc1_den = 0; 220 1.1.10.2 tls ((struct vi_ctrl *)&vic)->eisa_den = 1; 221 1.1.10.2 tls ((struct vi_ctrl *)&vic)->core_prf = 1; 222 1.1.10.2 tls 223 1.1.10.2 tls if (settimeout && 224 1.1.10.2 tls ((struct vi_ctrl *)&vic)->vsc_tout == 0) 225 1.1.10.2 tls /* clks */ 226 1.1.10.2 tls ((struct vi_ctrl *)&vic)->vsc_tout = 850; 227 1.1.10.2 tls 228 1.1.10.2 tls sc->sc_vp->vi_control = vic; 229 1.1.10.2 tls 230 1.1.10.2 tls __asm __volatile("stwas %1, 0(%0)" 231 1.1.10.2 tls :: "r" (&VI_CTRL), "r" (vic) : "memory"); 232 1.1.10.2 tls splx(s); 233 1.1.10.2 tls #ifdef DEBUG 234 1.1.10.2 tls snprintb(bits, sizeof(bits), VIPER_BITS, VI_CTRL); 235 1.1.10.2 tls printf (" >> %s", bits); 236 1.1.10.2 tls #endif 237 1.1.10.2 tls } else 238 1.1.10.2 tls sc->sc_vp = NULL; 239 1.1.10.2 tls } else 240 1.1.10.2 tls sc->sc_vp = NULL; 241 1.1.10.2 tls 242 1.1.10.2 tls err = pdcproc_iodc_ninit(&pdc_minit, ca->ca_hpa, PAGE0->imm_spa_size); 243 1.1.10.2 tls if (err < 0) 244 1.1.10.2 tls pdc_minit.max_spa = PAGE0->imm_max_mem; 245 1.1.10.2 tls 246 1.1.10.2 tls hppa_pagezero_unmap(pagezero_cookie); 247 1.1.10.2 tls 248 1.1.10.2 tls aprint_normal(" size %d", pdc_minit.max_spa / (1024*1024)); 249 1.1.10.2 tls if (pdc_minit.max_spa % (1024*1024)) 250 1.1.10.2 tls aprint_normal(".%d", pdc_minit.max_spa % (1024*1024)); 251 1.1.10.2 tls aprint_normal("MB"); 252 1.1.10.2 tls 253 1.1.10.2 tls /* L2 cache controller is a part of the memory controller on PCXL2 */ 254 1.1.10.2 tls if (hppa_cpu_info->hci_cputype == hpcxl2) { 255 1.1.10.2 tls sc->sc_l2 = (struct l2_mioc *)ca->ca_hpa; 256 1.1.10.2 tls #ifdef DEBUG 257 1.1.10.2 tls snprintb(bits, sizeof(bits), SLTCV_BITS, sc->sc_l2->sltcv); 258 1.1.10.2 tls printf(", sltcv %s", bits); 259 1.1.10.2 tls #endif 260 1.1.10.2 tls /* sc->sc_l2->sltcv |= SLTCV_UP4COUT; */ 261 1.1.10.2 tls if (sc->sc_l2->sltcv & SLTCV_ENABLE) { 262 1.1.10.2 tls uint32_t tagmask = sc->sc_l2->tagmask >> 20; 263 1.1.10.2 tls aprint_normal(", %dMB L2 cache", tagmask + 1); 264 1.1.10.2 tls } 265 1.1.10.2 tls } 266 1.1.10.2 tls aprint_normal("\n"); 267 1.1.10.2 tls } 268 1.1.10.2 tls 269 1.1.10.2 tls void 270 1.1.10.2 tls viper_setintrwnd(uint32_t mask) 271 1.1.10.2 tls { 272 1.1.10.2 tls device_t dv; 273 1.1.10.2 tls struct mem_softc *sc; 274 1.1.10.2 tls 275 1.1.10.2 tls dv = device_find_by_driver_unit("mem", 0); 276 1.1.10.2 tls sc = device_private(dv); 277 1.1.10.2 tls 278 1.1.10.2 tls if (sc->sc_vp) 279 1.1.10.2 tls sc->sc_vp->vi_intrwd; 280 1.1.10.2 tls } 281 1.1.10.2 tls 282 1.1.10.2 tls void 283 1.1.10.2 tls viper_eisa_en(void) 284 1.1.10.2 tls { 285 1.1.10.2 tls device_t dv; 286 1.1.10.2 tls struct mem_softc *sc; 287 1.1.10.2 tls 288 1.1.10.2 tls dv = device_find_by_driver_unit("mem", 0); 289 1.1.10.2 tls sc = device_private(dv); 290 1.1.10.2 tls 291 1.1.10.2 tls if (sc->sc_vp) { 292 1.1.10.2 tls int pagezero_cookie; 293 1.1.10.2 tls uint32_t vic; 294 1.1.10.2 tls int s; 295 1.1.10.2 tls 296 1.1.10.2 tls pagezero_cookie = hppa_pagezero_map(); 297 1.1.10.2 tls s = splhigh(); 298 1.1.10.2 tls vic = VI_CTRL; 299 1.1.10.2 tls ((struct vi_ctrl *)&vic)->eisa_den = 0; 300 1.1.10.2 tls sc->sc_vp->vi_control = vic; 301 1.1.10.2 tls __asm __volatile("stwas %1, 0(%0)" 302 1.1.10.2 tls :: "r" (&VI_CTRL), "r" (vic) : "memory"); 303 1.1.10.2 tls splx(s); 304 1.1.10.2 tls hppa_pagezero_unmap(pagezero_cookie); 305 1.1.10.2 tls } 306 1.1.10.2 tls } 307
Indexes created Thu Oct 02 14:10:14 GMT 2025