mongoose.c revision 1.3.10.3
1 1.3.10.2 tls /* $NetBSD: mongoose.c,v 1.3.10.3 2017/12/03 11:36:16 jdolecek Exp $ */ 2 1.3.10.2 tls 3 1.3.10.2 tls /* $OpenBSD: mongoose.c,v 1.19 2010/01/01 20:28:42 kettenis Exp $ */ 4 1.3.10.2 tls 5 1.3.10.2 tls /* 6 1.3.10.2 tls * Copyright (c) 1998-2003 Michael Shalayeff 7 1.3.10.2 tls * All rights reserved. 8 1.3.10.2 tls * 9 1.3.10.2 tls * Redistribution and use in source and binary forms, with or without 10 1.3.10.2 tls * modification, are permitted provided that the following conditions 11 1.3.10.2 tls * are met: 12 1.3.10.2 tls * 1. Redistributions of source code must retain the above copyright 13 1.3.10.2 tls * notice, this list of conditions and the following disclaimer. 14 1.3.10.2 tls * 2. Redistributions in binary form must reproduce the above copyright 15 1.3.10.2 tls * notice, this list of conditions and the following disclaimer in the 16 1.3.10.2 tls * documentation and/or other materials provided with the distribution. 17 1.3.10.2 tls * 18 1.3.10.2 tls * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 1.3.10.2 tls * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 1.3.10.2 tls * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 1.3.10.2 tls * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 1.3.10.2 tls * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 1.3.10.2 tls * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 1.3.10.2 tls * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 1.3.10.2 tls * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 1.3.10.2 tls * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 1.3.10.2 tls * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 1.3.10.2 tls * THE POSSIBILITY OF SUCH DAMAGE. 29 1.3.10.2 tls */ 30 1.3.10.2 tls 31 1.3.10.2 tls #include <sys/cdefs.h> 32 1.3.10.2 tls __KERNEL_RCSID(0, "$NetBSD: mongoose.c,v 1.3.10.3 2017/12/03 11:36:16 jdolecek Exp $"); 33 1.3.10.2 tls 34 1.3.10.2 tls #define MONGOOSE_DEBUG 9 35 1.3.10.2 tls 36 1.3.10.2 tls #include <sys/param.h> 37 1.3.10.2 tls #include <sys/systm.h> 38 1.3.10.2 tls #include <sys/device.h> 39 1.3.10.2 tls #include <sys/reboot.h> 40 1.3.10.2 tls 41 1.3.10.2 tls #include <sys/bus.h> 42 1.3.10.2 tls #include <machine/iomod.h> 43 1.3.10.2 tls #include <machine/autoconf.h> 44 1.3.10.2 tls 45 1.3.10.2 tls #include <hppa/dev/cpudevs.h> 46 1.3.10.2 tls #include <hppa/dev/viper.h> 47 1.3.10.2 tls 48 1.3.10.2 tls #include <dev/eisa/eisareg.h> 49 1.3.10.2 tls #include <dev/eisa/eisavar.h> 50 1.3.10.2 tls 51 1.3.10.2 tls #include <dev/isa/isareg.h> 52 1.3.10.2 tls #include <dev/isa/isavar.h> 53 1.3.10.2 tls 54 1.3.10.2 tls /* EISA Bus Adapter registers definitions */ 55 1.3.10.2 tls #define MONGOOSE_MONGOOSE 0x10000 56 1.3.10.2 tls struct mongoose_regs { 57 1.3.10.2 tls uint8_t version; 58 1.3.10.2 tls uint8_t lock; 59 1.3.10.2 tls uint8_t liowait; 60 1.3.10.2 tls uint8_t clock; 61 1.3.10.2 tls uint8_t reserved[0xf000 - 4]; 62 1.3.10.2 tls uint8_t intack; 63 1.3.10.2 tls }; 64 1.3.10.2 tls 65 1.3.10.2 tls #define MONGOOSE_CTRL 0x00000 66 1.3.10.2 tls #define MONGOOSE_NINTS 16 67 1.3.10.2 tls struct mongoose_ctrl { 68 1.3.10.2 tls struct dma0 { 69 1.3.10.2 tls struct { 70 1.3.10.2 tls uint32_t addr : 8; 71 1.3.10.2 tls uint32_t count: 8; 72 1.3.10.2 tls } ch[4]; 73 1.3.10.2 tls uint8_t command; 74 1.3.10.2 tls uint8_t request; 75 1.3.10.2 tls uint8_t mask_channel; 76 1.3.10.2 tls uint8_t mode; 77 1.3.10.2 tls uint8_t clr_byte_ptr; 78 1.3.10.2 tls uint8_t master_clear; 79 1.3.10.2 tls uint8_t mask_clear; 80 1.3.10.2 tls uint8_t master_write; 81 1.3.10.2 tls uint8_t pad[8]; 82 1.3.10.2 tls } dma0; 83 1.3.10.2 tls 84 1.3.10.2 tls uint8_t irr0; /* 0x20 */ 85 1.3.10.2 tls uint8_t imr0; 86 1.3.10.2 tls uint8_t iack; /* 0x22 -- 2 b2b reads generate 87 1.3.10.2 tls (e)isa Iack cycle & returns int level */ 88 1.3.10.2 tls uint8_t pad0[29]; 89 1.3.10.2 tls 90 1.3.10.2 tls struct timers { 91 1.3.10.2 tls uint8_t sysclk; 92 1.3.10.2 tls uint8_t refresh; 93 1.3.10.2 tls uint8_t spkr; 94 1.3.10.2 tls uint8_t ctrl; 95 1.3.10.2 tls uint32_t pad; 96 1.3.10.2 tls } tmr[2]; /* 0x40 -- timers control */ 97 1.3.10.2 tls uint8_t pad1[16]; 98 1.3.10.2 tls 99 1.3.10.2 tls uint16_t inmi; /* 0x60 NMI control */ 100 1.3.10.2 tls uint8_t pad2[30]; 101 1.3.10.2 tls struct { 102 1.3.10.2 tls uint8_t pad0; 103 1.3.10.2 tls uint8_t ch2; 104 1.3.10.2 tls uint8_t ch3; 105 1.3.10.2 tls uint8_t ch1; 106 1.3.10.2 tls uint8_t pad1; 107 1.3.10.2 tls uint8_t pad2[3]; 108 1.3.10.2 tls uint8_t ch0; 109 1.3.10.2 tls uint8_t pad4; 110 1.3.10.2 tls uint8_t ch6; 111 1.3.10.2 tls uint8_t ch7; 112 1.3.10.2 tls uint8_t ch5; 113 1.3.10.2 tls uint8_t pad5[3]; 114 1.3.10.2 tls uint8_t pad6[16]; 115 1.3.10.2 tls } pr; /* 0x80 */ 116 1.3.10.2 tls 117 1.3.10.2 tls uint8_t irr1; /* 0xa0 */ 118 1.3.10.2 tls uint8_t imr1; 119 1.3.10.2 tls uint8_t pad3[30]; 120 1.3.10.2 tls 121 1.3.10.2 tls struct dma1 { 122 1.3.10.2 tls struct { 123 1.3.10.2 tls uint32_t addr : 8; 124 1.3.10.2 tls uint32_t pad0 : 8; 125 1.3.10.2 tls uint32_t count: 8; 126 1.3.10.2 tls uint32_t pad1 : 8; 127 1.3.10.2 tls } ch[4]; 128 1.3.10.2 tls uint8_t command; 129 1.3.10.2 tls uint8_t pad0; 130 1.3.10.2 tls uint8_t request; 131 1.3.10.2 tls uint8_t pad1; 132 1.3.10.2 tls uint8_t mask_channel; 133 1.3.10.2 tls uint8_t pad2; 134 1.3.10.2 tls uint8_t mode; 135 1.3.10.2 tls uint8_t pad3; 136 1.3.10.2 tls uint8_t clr_byte_ptr; 137 1.3.10.2 tls uint8_t pad4; 138 1.3.10.2 tls uint8_t master_clear; 139 1.3.10.2 tls uint8_t pad5; 140 1.3.10.2 tls uint8_t mask_clear; 141 1.3.10.2 tls uint8_t pad6; 142 1.3.10.2 tls uint8_t master_write; 143 1.3.10.2 tls uint8_t pad7; 144 1.3.10.2 tls } dma1; /* 0xc0 */ 145 1.3.10.2 tls 146 1.3.10.2 tls uint8_t master_req; /* 0xe0 master request register */ 147 1.3.10.2 tls uint8_t pad4[31]; 148 1.3.10.2 tls 149 1.3.10.2 tls uint8_t pad5[0x3d0]; /* 0x4d0 */ 150 1.3.10.2 tls uint8_t pic0; /* 0 - edge, 1 - level */ 151 1.3.10.2 tls uint8_t pic1; 152 1.3.10.2 tls uint8_t pad6[0x460]; 153 1.3.10.2 tls uint8_t nmi; 154 1.3.10.2 tls uint8_t nmi_ext; 155 1.3.10.2 tls #define MONGOOSE_NMI_BUSRESET 0x01 156 1.3.10.2 tls #define MONGOOSE_NMI_IOPORT_EN 0x02 157 1.3.10.2 tls #define MONGOOSE_NMI_EN 0x04 158 1.3.10.2 tls #define MONGOOSE_NMI_MTMO_EN 0x08 159 1.3.10.2 tls #define MONGOOSE_NMI_RES4 0x10 160 1.3.10.2 tls #define MONGOOSE_NMI_IOPORT_INT 0x20 161 1.3.10.2 tls #define MONGOOSE_NMI_MASTER_INT 0x40 162 1.3.10.2 tls #define MONGOOSE_NMI_INT 0x80 163 1.3.10.2 tls }; 164 1.3.10.2 tls 165 1.3.10.2 tls #define MONGOOSE_IOMAP 0x100000 166 1.3.10.2 tls 167 1.3.10.2 tls struct hppa_isa_iv { 168 1.3.10.2 tls int (*iv_handler)(void *arg); 169 1.3.10.2 tls void *iv_arg; 170 1.3.10.2 tls int iv_pri; 171 1.3.10.2 tls 172 1.3.10.2 tls struct evcnt iv_evcnt; 173 1.3.10.2 tls /* don't do sharing, we won't have many slots anyway 174 1.3.10.2 tls struct hppa_isa_iv *iv_next; 175 1.3.10.2 tls */ 176 1.3.10.2 tls }; 177 1.3.10.2 tls 178 1.3.10.2 tls struct mongoose_softc { 179 1.3.10.2 tls device_t sc_dev; 180 1.3.10.2 tls void *sc_ih; 181 1.3.10.2 tls 182 1.3.10.2 tls bus_space_tag_t sc_bt; 183 1.3.10.2 tls volatile struct mongoose_regs *sc_regs; 184 1.3.10.2 tls volatile struct mongoose_ctrl *sc_ctrl; 185 1.3.10.2 tls bus_addr_t sc_iomap; 186 1.3.10.2 tls 187 1.3.10.2 tls /* interrupts section */ 188 1.3.10.2 tls struct hppa_eisa_chipset sc_ec; 189 1.3.10.2 tls struct hppa_isa_chipset sc_ic; 190 1.3.10.2 tls struct hppa_isa_iv sc_iv[MONGOOSE_NINTS]; 191 1.3.10.2 tls 192 1.3.10.2 tls /* isa/eisa bus guts */ 193 1.3.10.2 tls struct hppa_bus_space_tag sc_eiot; 194 1.3.10.2 tls struct hppa_bus_space_tag sc_ememt; 195 1.3.10.2 tls struct hppa_bus_dma_tag sc_edmat; 196 1.3.10.2 tls struct hppa_bus_space_tag sc_iiot; 197 1.3.10.2 tls struct hppa_bus_space_tag sc_imemt; 198 1.3.10.2 tls struct hppa_bus_dma_tag sc_idmat; 199 1.3.10.2 tls }; 200 1.3.10.2 tls 201 1.3.10.2 tls union mongoose_attach_args { 202 1.3.10.2 tls struct eisabus_attach_args mongoose_eisa; 203 1.3.10.2 tls struct isabus_attach_args mongoose_isa; 204 1.3.10.2 tls }; 205 1.3.10.2 tls 206 1.3.10.2 tls void mg_eisa_attach_hook(device_t, device_t, struct eisabus_attach_args *); 207 1.3.10.2 tls int mg_intr_map(void *, u_int, eisa_intr_handle_t *); 208 1.3.10.2 tls const char *mg_intr_string(void *, int, char *, size_t); 209 1.3.10.2 tls void mg_isa_attach_hook(device_t, device_t, struct isabus_attach_args *); 210 1.3.10.2 tls void mg_isa_detach_hook(isa_chipset_tag_t, device_t); 211 1.3.10.2 tls void *mg_intr_establish(void *, int, int, int, int (*)(void *), void *); 212 1.3.10.2 tls void mg_intr_disestablish(void *, void *); 213 1.3.10.2 tls int mg_intr_check(void *, int, int); 214 1.3.10.2 tls int mg_intr(void *); 215 1.3.10.2 tls int mg_eisa_iomap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 216 1.3.10.2 tls int mg_eisa_memmap(void *, bus_addr_t, bus_size_t, int, bus_space_handle_t *); 217 1.3.10.2 tls void mg_eisa_memunmap(void *, bus_space_handle_t, bus_size_t); 218 1.3.10.2 tls void mg_isa_barrier(void *, bus_space_handle_t, bus_size_t, bus_size_t, int); 219 1.3.10.2 tls uint16_t mg_isa_r2(void *, bus_space_handle_t, bus_size_t); 220 1.3.10.2 tls uint32_t mg_isa_r4(void *, bus_space_handle_t, bus_size_t); 221 1.3.10.2 tls void mg_isa_w2(void *, bus_space_handle_t, bus_size_t, uint16_t); 222 1.3.10.2 tls void mg_isa_w4(void *, bus_space_handle_t, bus_size_t, uint32_t); 223 1.3.10.2 tls void mg_isa_rm_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 224 1.3.10.2 tls void mg_isa_rm_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 225 1.3.10.2 tls void mg_isa_wm_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); 226 1.3.10.2 tls void mg_isa_wm_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); 227 1.3.10.2 tls void mg_isa_sm_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 228 1.3.10.2 tls void mg_isa_sm_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 229 1.3.10.2 tls void mg_isa_rr_2(void *, bus_space_handle_t, bus_size_t, uint16_t *, bus_size_t); 230 1.3.10.2 tls void mg_isa_rr_4(void *, bus_space_handle_t, bus_size_t, uint32_t *, bus_size_t); 231 1.3.10.2 tls void mg_isa_wr_2(void *, bus_space_handle_t, bus_size_t, const uint16_t *, bus_size_t); 232 1.3.10.2 tls void mg_isa_wr_4(void *, bus_space_handle_t, bus_size_t, const uint32_t *, bus_size_t); 233 1.3.10.2 tls void mg_isa_sr_2(void *, bus_space_handle_t, bus_size_t, uint16_t, bus_size_t); 234 1.3.10.2 tls void mg_isa_sr_4(void *, bus_space_handle_t, bus_size_t, uint32_t, bus_size_t); 235 1.3.10.2 tls 236 1.3.10.2 tls int mgmatch(device_t, cfdata_t, void *); 237 1.3.10.2 tls void mgattach(device_t, device_t, void *); 238 1.3.10.2 tls 239 1.3.10.2 tls CFATTACH_DECL_NEW(mongoose, sizeof(struct mongoose_softc), 240 1.3.10.2 tls mgmatch, mgattach, NULL, NULL); 241 1.3.10.2 tls 242 1.3.10.2 tls /* TODO: DMA guts */ 243 1.3.10.2 tls 244 1.3.10.2 tls void 245 1.3.10.2 tls mg_eisa_attach_hook(device_t parent, device_t self, 246 1.3.10.2 tls struct eisabus_attach_args *mg) 247 1.3.10.2 tls { 248 1.3.10.2 tls } 249 1.3.10.2 tls 250 1.3.10.2 tls int 251 1.3.10.2 tls mg_intr_map(void *v, u_int irq, eisa_intr_handle_t *ehp) 252 1.3.10.2 tls { 253 1.3.10.2 tls *ehp = irq; 254 1.3.10.2 tls return 0; 255 1.3.10.2 tls } 256 1.3.10.2 tls 257 1.3.10.2 tls const char * 258 1.3.10.2 tls mg_intr_string(void *v, int irq, char *buf, size_t len) 259 1.3.10.2 tls { 260 1.3.10.2 tls snprintf (buf, len, "isa irq %d", irq); 261 1.3.10.2 tls return buf; 262 1.3.10.2 tls } 263 1.3.10.2 tls 264 1.3.10.2 tls void 265 1.3.10.2 tls mg_isa_attach_hook(device_t parent, device_t self, 266 1.3.10.2 tls struct isabus_attach_args *iba) 267 1.3.10.2 tls { 268 1.3.10.2 tls 269 1.3.10.2 tls } 270 1.3.10.2 tls 271 1.3.10.2 tls void 272 1.3.10.2 tls mg_isa_detach_hook(isa_chipset_tag_t ic, device_t self) 273 1.3.10.2 tls { 274 1.3.10.2 tls 275 1.3.10.2 tls } 276 1.3.10.2 tls 277 1.3.10.2 tls void * 278 1.3.10.2 tls mg_intr_establish(void *v, int irq, int type, int pri, 279 1.3.10.2 tls int (*handler)(void *), void *arg) 280 1.3.10.2 tls { 281 1.3.10.2 tls struct hppa_isa_iv *iv; 282 1.3.10.2 tls struct mongoose_softc *sc = v; 283 1.3.10.2 tls volatile uint8_t *imr, *pic; 284 1.3.10.2 tls 285 1.3.10.2 tls if (!sc || irq < 0 || irq >= MONGOOSE_NINTS || 286 1.3.10.2 tls (0 <= irq && irq < MONGOOSE_NINTS && sc->sc_iv[irq].iv_handler)) 287 1.3.10.2 tls return NULL; 288 1.3.10.2 tls 289 1.3.10.2 tls if (type != IST_LEVEL && type != IST_EDGE) { 290 1.3.10.2 tls aprint_debug_dev(sc->sc_dev, "bad interrupt level (%d)\n", 291 1.3.10.2 tls type); 292 1.3.10.2 tls return NULL; 293 1.3.10.2 tls } 294 1.3.10.2 tls 295 1.3.10.2 tls iv = &sc->sc_iv[irq]; 296 1.3.10.2 tls if (iv->iv_handler) { 297 1.3.10.2 tls aprint_debug_dev(sc->sc_dev, "irq %d already established\n", 298 1.3.10.2 tls irq); 299 1.3.10.2 tls return NULL; 300 1.3.10.2 tls } 301 1.3.10.2 tls 302 1.3.10.2 tls iv->iv_pri = pri; 303 1.3.10.2 tls iv->iv_handler = handler; 304 1.3.10.2 tls iv->iv_arg = arg; 305 1.3.10.2 tls 306 1.3.10.2 tls if (irq < 8) { 307 1.3.10.2 tls imr = &sc->sc_ctrl->imr0; 308 1.3.10.2 tls pic = &sc->sc_ctrl->pic0; 309 1.3.10.2 tls } else { 310 1.3.10.2 tls imr = &sc->sc_ctrl->imr1; 311 1.3.10.2 tls pic = &sc->sc_ctrl->pic1; 312 1.3.10.2 tls irq -= 8; 313 1.3.10.2 tls } 314 1.3.10.2 tls 315 1.3.10.2 tls *imr |= 1 << irq; 316 1.3.10.2 tls *pic |= (type == IST_LEVEL) << irq; 317 1.3.10.2 tls 318 1.3.10.2 tls /* TODO: ack it? */ 319 1.3.10.2 tls 320 1.3.10.2 tls return iv; 321 1.3.10.2 tls } 322 1.3.10.2 tls 323 1.3.10.2 tls void 324 1.3.10.2 tls mg_intr_disestablish(void *v, void *cookie) 325 1.3.10.2 tls { 326 1.3.10.2 tls struct hppa_isa_iv *iv = cookie; 327 1.3.10.2 tls struct mongoose_softc *sc = v; 328 1.3.10.3 jdolecek int irq; 329 1.3.10.2 tls volatile uint8_t *imr; 330 1.3.10.2 tls 331 1.3.10.2 tls if (!sc || !cookie) 332 1.3.10.2 tls return; 333 1.3.10.2 tls 334 1.3.10.3 jdolecek irq = iv - sc->sc_iv; 335 1.3.10.3 jdolecek 336 1.3.10.2 tls if (irq < 8) 337 1.3.10.2 tls imr = &sc->sc_ctrl->imr0; 338 1.3.10.2 tls else 339 1.3.10.2 tls imr = &sc->sc_ctrl->imr1; 340 1.3.10.2 tls *imr &= ~(1 << irq); 341 1.3.10.2 tls /* TODO: ack it? */ 342 1.3.10.2 tls 343 1.3.10.2 tls iv->iv_handler = NULL; 344 1.3.10.2 tls } 345 1.3.10.2 tls 346 1.3.10.2 tls int 347 1.3.10.2 tls mg_intr_check(void *v, int irq, int type) 348 1.3.10.2 tls { 349 1.3.10.2 tls return 0; 350 1.3.10.2 tls } 351 1.3.10.2 tls 352 1.3.10.2 tls int 353 1.3.10.2 tls mg_intr(void *v) 354 1.3.10.2 tls { 355 1.3.10.2 tls struct mongoose_softc *sc = v; 356 1.3.10.2 tls struct hppa_isa_iv *iv; 357 1.3.10.2 tls int s, irq = 0; 358 1.3.10.2 tls 359 1.3.10.2 tls iv = &sc->sc_iv[irq]; 360 1.3.10.2 tls s = splraise(iv->iv_pri); 361 1.3.10.2 tls (iv->iv_handler)(iv->iv_arg); 362 1.3.10.2 tls splx(s); 363 1.3.10.2 tls 364 1.3.10.2 tls return 0; 365 1.3.10.2 tls } 366 1.3.10.2 tls 367 1.3.10.2 tls int 368 1.3.10.2 tls mg_eisa_iomap(void *v, bus_addr_t addr, bus_size_t size, int cacheable, 369 1.3.10.2 tls bus_space_handle_t *bshp) 370 1.3.10.2 tls { 371 1.3.10.2 tls struct mongoose_softc *sc = v; 372 1.3.10.2 tls 373 1.3.10.2 tls /* see if it's ISA space we are mapping */ 374 1.3.10.2 tls if (0x100 <= addr && addr < 0x400) { 375 1.3.10.2 tls #define TOISA(a) ((((a) & 0x3f8) << 9) + ((a) & 7)) 376 1.3.10.2 tls size = TOISA(addr + size) - TOISA(addr); 377 1.3.10.2 tls addr = TOISA(addr); 378 1.3.10.2 tls } 379 1.3.10.2 tls 380 1.3.10.2 tls return (sc->sc_bt->hbt_map)(NULL, sc->sc_iomap + addr, size, 381 1.3.10.2 tls cacheable, bshp); 382 1.3.10.2 tls } 383 1.3.10.2 tls 384 1.3.10.2 tls int 385 1.3.10.2 tls mg_eisa_memmap(void *v, bus_addr_t addr, bus_size_t size, int cacheable, 386 1.3.10.2 tls bus_space_handle_t *bshp) 387 1.3.10.2 tls { 388 1.3.10.2 tls /* TODO: eisa memory map */ 389 1.3.10.2 tls return -1; 390 1.3.10.2 tls } 391 1.3.10.2 tls 392 1.3.10.2 tls void 393 1.3.10.2 tls mg_eisa_memunmap(void *v, bus_space_handle_t bsh, bus_size_t size) 394 1.3.10.2 tls { 395 1.3.10.2 tls /* TODO: eisa memory unmap */ 396 1.3.10.2 tls } 397 1.3.10.2 tls 398 1.3.10.2 tls void 399 1.3.10.2 tls mg_isa_barrier(void *v, bus_space_handle_t h, bus_size_t o, bus_size_t l, int op) 400 1.3.10.2 tls { 401 1.3.10.2 tls sync_caches(); 402 1.3.10.2 tls } 403 1.3.10.2 tls 404 1.3.10.2 tls uint16_t 405 1.3.10.2 tls mg_isa_r2(void *v, bus_space_handle_t h, bus_size_t o) 406 1.3.10.2 tls { 407 1.3.10.2 tls uint16_t r = *((volatile uint16_t *)(h + o)); 408 1.3.10.2 tls 409 1.3.10.2 tls return le16toh(r); 410 1.3.10.2 tls } 411 1.3.10.2 tls 412 1.3.10.2 tls uint32_t 413 1.3.10.2 tls mg_isa_r4(void *v, bus_space_handle_t h, bus_size_t o) 414 1.3.10.2 tls { 415 1.3.10.2 tls uint32_t r = *((volatile uint32_t *)(h + o)); 416 1.3.10.2 tls 417 1.3.10.2 tls return le32toh(r); 418 1.3.10.2 tls } 419 1.3.10.2 tls 420 1.3.10.2 tls void 421 1.3.10.2 tls mg_isa_w2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv) 422 1.3.10.2 tls { 423 1.3.10.2 tls *((volatile uint16_t *)(h + o)) = htole16(vv); 424 1.3.10.2 tls } 425 1.3.10.2 tls 426 1.3.10.2 tls void 427 1.3.10.2 tls mg_isa_w4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv) 428 1.3.10.2 tls { 429 1.3.10.2 tls *((volatile uint32_t *)(h + o)) = htole32(vv); 430 1.3.10.2 tls } 431 1.3.10.2 tls 432 1.3.10.2 tls void 433 1.3.10.2 tls mg_isa_rm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 434 1.3.10.2 tls { 435 1.3.10.2 tls h += o; 436 1.3.10.2 tls while (c--) 437 1.3.10.2 tls *(a++) = le16toh(*(volatile uint16_t *)h); 438 1.3.10.2 tls } 439 1.3.10.2 tls 440 1.3.10.2 tls void 441 1.3.10.2 tls mg_isa_rm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 442 1.3.10.2 tls { 443 1.3.10.2 tls h += o; 444 1.3.10.2 tls while (c--) 445 1.3.10.2 tls *(a++) = le32toh(*(volatile uint32_t *)h); 446 1.3.10.2 tls } 447 1.3.10.2 tls 448 1.3.10.2 tls void 449 1.3.10.2 tls mg_isa_wm_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 450 1.3.10.2 tls { 451 1.3.10.2 tls uint16_t r; 452 1.3.10.2 tls 453 1.3.10.2 tls h += o; 454 1.3.10.2 tls while (c--) { 455 1.3.10.2 tls r = *(a++); 456 1.3.10.2 tls *(volatile uint16_t *)h = htole16(r); 457 1.3.10.2 tls } 458 1.3.10.2 tls } 459 1.3.10.2 tls 460 1.3.10.2 tls void 461 1.3.10.2 tls mg_isa_wm_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 462 1.3.10.2 tls { 463 1.3.10.2 tls uint32_t r; 464 1.3.10.2 tls 465 1.3.10.2 tls h += o; 466 1.3.10.2 tls while (c--) { 467 1.3.10.2 tls r = *(a++); 468 1.3.10.2 tls *(volatile uint32_t *)h = htole32(r); 469 1.3.10.2 tls } 470 1.3.10.2 tls } 471 1.3.10.2 tls 472 1.3.10.2 tls void 473 1.3.10.2 tls mg_isa_sm_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 474 1.3.10.2 tls { 475 1.3.10.2 tls vv = htole16(vv); 476 1.3.10.2 tls h += o; 477 1.3.10.2 tls while (c--) 478 1.3.10.2 tls *(volatile uint16_t *)h = vv; 479 1.3.10.2 tls } 480 1.3.10.2 tls 481 1.3.10.2 tls void 482 1.3.10.2 tls mg_isa_sm_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 483 1.3.10.2 tls { 484 1.3.10.2 tls vv = htole32(vv); 485 1.3.10.2 tls h += o; 486 1.3.10.2 tls while (c--) 487 1.3.10.2 tls *(volatile uint32_t *)h = vv; 488 1.3.10.2 tls } 489 1.3.10.2 tls 490 1.3.10.2 tls void 491 1.3.10.2 tls mg_isa_rr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t *a, bus_size_t c) 492 1.3.10.2 tls { 493 1.3.10.2 tls uint16_t r; 494 1.3.10.2 tls volatile uint16_t *p; 495 1.3.10.2 tls 496 1.3.10.2 tls h += o; 497 1.3.10.2 tls p = (void *)h; 498 1.3.10.2 tls while (c--) { 499 1.3.10.2 tls r = *p++; 500 1.3.10.2 tls *a++ = le16toh(r); 501 1.3.10.2 tls } 502 1.3.10.2 tls } 503 1.3.10.2 tls 504 1.3.10.2 tls void 505 1.3.10.2 tls mg_isa_rr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t *a, bus_size_t c) 506 1.3.10.2 tls { 507 1.3.10.2 tls uint32_t r; 508 1.3.10.2 tls volatile uint32_t *p; 509 1.3.10.2 tls 510 1.3.10.2 tls h += o; 511 1.3.10.2 tls p = (void *)h; 512 1.3.10.2 tls while (c--) { 513 1.3.10.2 tls r = *p++; 514 1.3.10.2 tls *a++ = le32toh(r); 515 1.3.10.2 tls } 516 1.3.10.2 tls } 517 1.3.10.2 tls 518 1.3.10.2 tls void 519 1.3.10.2 tls mg_isa_wr_2(void *v, bus_space_handle_t h, bus_size_t o, const uint16_t *a, bus_size_t c) 520 1.3.10.2 tls { 521 1.3.10.2 tls uint16_t r; 522 1.3.10.2 tls volatile uint16_t *p; 523 1.3.10.2 tls 524 1.3.10.2 tls h += o; 525 1.3.10.2 tls p = (void *)h; 526 1.3.10.2 tls while (c--) { 527 1.3.10.2 tls r = *a++; 528 1.3.10.2 tls *p++ = htole16(r); 529 1.3.10.2 tls } 530 1.3.10.2 tls } 531 1.3.10.2 tls 532 1.3.10.2 tls void 533 1.3.10.2 tls mg_isa_wr_4(void *v, bus_space_handle_t h, bus_size_t o, const uint32_t *a, bus_size_t c) 534 1.3.10.2 tls { 535 1.3.10.2 tls uint32_t r; 536 1.3.10.2 tls volatile uint32_t *p; 537 1.3.10.2 tls 538 1.3.10.2 tls h += o; 539 1.3.10.2 tls p = (void *)h; 540 1.3.10.2 tls while (c--) { 541 1.3.10.2 tls r = *a++; 542 1.3.10.2 tls *p++ = htole32(r); 543 1.3.10.2 tls } 544 1.3.10.2 tls } 545 1.3.10.2 tls 546 1.3.10.2 tls void 547 1.3.10.2 tls mg_isa_sr_2(void *v, bus_space_handle_t h, bus_size_t o, uint16_t vv, bus_size_t c) 548 1.3.10.2 tls { 549 1.3.10.2 tls volatile uint16_t *p; 550 1.3.10.2 tls 551 1.3.10.2 tls vv = htole16(vv); 552 1.3.10.2 tls h += o; 553 1.3.10.2 tls p = (void *)h; 554 1.3.10.2 tls while (c--) 555 1.3.10.2 tls *p++ = vv; 556 1.3.10.2 tls } 557 1.3.10.2 tls 558 1.3.10.2 tls void 559 1.3.10.2 tls mg_isa_sr_4(void *v, bus_space_handle_t h, bus_size_t o, uint32_t vv, bus_size_t c) 560 1.3.10.2 tls { 561 1.3.10.2 tls volatile uint32_t *p; 562 1.3.10.2 tls 563 1.3.10.2 tls vv = htole32(vv); 564 1.3.10.2 tls h += o; 565 1.3.10.2 tls p = (void *)h; 566 1.3.10.2 tls while (c--) 567 1.3.10.2 tls *p++ = vv; 568 1.3.10.2 tls } 569 1.3.10.2 tls 570 1.3.10.2 tls int 571 1.3.10.2 tls mgmatch(device_t parent, cfdata_t cf, void *aux) 572 1.3.10.2 tls { 573 1.3.10.2 tls struct confargs *ca = aux; 574 1.3.10.2 tls bus_space_handle_t ioh; 575 1.3.10.2 tls 576 1.3.10.2 tls if (ca->ca_type.iodc_type != HPPA_TYPE_BHA || 577 1.3.10.2 tls ca->ca_type.iodc_sv_model != HPPA_BHA_EISA) 578 1.3.10.2 tls return 0; 579 1.3.10.2 tls 580 1.3.10.2 tls if (bus_space_map(ca->ca_iot, ca->ca_hpa + MONGOOSE_MONGOOSE, 581 1.3.10.2 tls sizeof(struct mongoose_regs), 0, &ioh)) 582 1.3.10.2 tls return 0; 583 1.3.10.2 tls 584 1.3.10.2 tls /* XXX check EISA signature */ 585 1.3.10.2 tls 586 1.3.10.2 tls bus_space_unmap(ca->ca_iot, ioh, sizeof(struct mongoose_regs)); 587 1.3.10.2 tls 588 1.3.10.2 tls return 1; 589 1.3.10.2 tls } 590 1.3.10.2 tls 591 1.3.10.2 tls void 592 1.3.10.2 tls mgattach(device_t parent, device_t self, void *aux) 593 1.3.10.2 tls { 594 1.3.10.2 tls struct confargs *ca = aux; 595 1.3.10.2 tls struct mongoose_softc *sc = device_private(self); 596 1.3.10.2 tls struct cpu_info *ci = &cpus[0]; 597 1.3.10.2 tls struct hppa_bus_space_tag *bt; 598 1.3.10.2 tls union mongoose_attach_args ea; 599 1.3.10.2 tls char brid[EISA_IDSTRINGLEN]; 600 1.3.10.2 tls bus_space_handle_t ioh; 601 1.3.10.2 tls 602 1.3.10.2 tls sc->sc_dev = self; 603 1.3.10.2 tls sc->sc_bt = ca->ca_iot; 604 1.3.10.2 tls sc->sc_iomap = ca->ca_hpa; 605 1.3.10.2 tls if (bus_space_map(ca->ca_iot, ca->ca_hpa + MONGOOSE_MONGOOSE, 606 1.3.10.2 tls sizeof(struct mongoose_regs), 0, &ioh)) { 607 1.3.10.2 tls aprint_error(": can't map registers\n"); 608 1.3.10.2 tls return; 609 1.3.10.2 tls } 610 1.3.10.2 tls sc->sc_regs = (struct mongoose_regs *)ioh; 611 1.3.10.2 tls 612 1.3.10.2 tls if (bus_space_map(ca->ca_iot, ca->ca_hpa + MONGOOSE_CTRL, 613 1.3.10.2 tls sizeof(struct mongoose_ctrl), 0, &ioh)) { 614 1.3.10.2 tls aprint_error(": can't map control registers\n"); 615 1.3.10.2 tls bus_space_unmap(ca->ca_iot, (bus_space_handle_t)sc->sc_regs, 616 1.3.10.2 tls sizeof(struct mongoose_regs)); 617 1.3.10.2 tls return; 618 1.3.10.2 tls } 619 1.3.10.2 tls 620 1.3.10.2 tls ca->ca_irq = hppa_intr_allocate_bit(&ci->ci_ir, ca->ca_irq); 621 1.3.10.2 tls if (ca->ca_irq == HPPACF_IRQ_UNDEF) { 622 1.3.10.2 tls aprint_error(": can't allocate interrupt\n"); 623 1.3.10.2 tls return; 624 1.3.10.2 tls } 625 1.3.10.2 tls 626 1.3.10.2 tls sc->sc_ctrl = (struct mongoose_ctrl *)ioh; 627 1.3.10.2 tls 628 1.3.10.2 tls viper_eisa_en(); 629 1.3.10.2 tls 630 1.3.10.2 tls /* BUS RESET */ 631 1.3.10.2 tls sc->sc_ctrl->nmi_ext = MONGOOSE_NMI_BUSRESET; 632 1.3.10.2 tls DELAY(1); 633 1.3.10.2 tls sc->sc_ctrl->nmi_ext = 0; 634 1.3.10.2 tls DELAY(100); 635 1.3.10.2 tls 636 1.3.10.2 tls /* determine eisa board id */ 637 1.3.10.2 tls { 638 1.3.10.2 tls uint8_t id[4], *p; 639 1.3.10.2 tls /* XXX this is awful */ 640 1.3.10.2 tls p = (uint8_t *)(ioh + EISA_SLOTOFF_VID); 641 1.3.10.2 tls id[0] = *p++; 642 1.3.10.2 tls id[1] = *p++; 643 1.3.10.2 tls id[2] = *p++; 644 1.3.10.2 tls id[3] = *p++; 645 1.3.10.2 tls 646 1.3.10.2 tls brid[0] = EISA_VENDID_0(id); 647 1.3.10.2 tls brid[1] = EISA_VENDID_1(id); 648 1.3.10.2 tls brid[2] = EISA_VENDID_2(id); 649 1.3.10.2 tls brid[3] = EISA_PRODID_0(id + 2); 650 1.3.10.2 tls brid[4] = EISA_PRODID_1(id + 2); 651 1.3.10.2 tls brid[5] = EISA_PRODID_2(id + 2); 652 1.3.10.2 tls brid[6] = EISA_PRODID_3(id + 2); 653 1.3.10.2 tls brid[7] = '\0'; 654 1.3.10.2 tls } 655 1.3.10.2 tls 656 1.3.10.2 tls aprint_normal(": %s rev %d, %d MHz\n", brid, sc->sc_regs->version, 657 1.3.10.2 tls (sc->sc_regs->clock? 33 : 25)); 658 1.3.10.2 tls sc->sc_regs->liowait = 1; /* disable isa wait states */ 659 1.3.10.2 tls sc->sc_regs->lock = 1; /* bus unlock */ 660 1.3.10.2 tls 661 1.3.10.2 tls /* attach EISA */ 662 1.3.10.2 tls sc->sc_ec.ec_v = sc; 663 1.3.10.2 tls sc->sc_ec.ec_attach_hook = mg_eisa_attach_hook; 664 1.3.10.2 tls sc->sc_ec.ec_intr_establish = mg_intr_establish; 665 1.3.10.2 tls sc->sc_ec.ec_intr_disestablish = mg_intr_disestablish; 666 1.3.10.2 tls sc->sc_ec.ec_intr_string = mg_intr_string; 667 1.3.10.2 tls sc->sc_ec.ec_intr_map = mg_intr_map; 668 1.3.10.2 tls 669 1.3.10.2 tls /* inherit the bus tags for eisa from the mainbus */ 670 1.3.10.2 tls bt = &sc->sc_eiot; 671 1.3.10.2 tls memcpy(bt, ca->ca_iot, sizeof(*bt)); 672 1.3.10.2 tls bt->hbt_cookie = sc; 673 1.3.10.2 tls bt->hbt_map = mg_eisa_iomap; 674 1.3.10.2 tls #define R(n) bt->__CONCAT(hbt_,n) = &__CONCAT(mg_isa_,n) 675 1.3.10.2 tls /* R(barrier); */ 676 1.3.10.2 tls R(r2); R(r4); R(w2); R(w4); 677 1.3.10.2 tls R(rm_2);R(rm_4);R(wm_2);R(wm_4);R(sm_2);R(sm_4); 678 1.3.10.2 tls R(rr_2);R(rr_4);R(wr_2);R(wr_4);R(sr_2);R(sr_4); 679 1.3.10.2 tls 680 1.3.10.2 tls bt = &sc->sc_ememt; 681 1.3.10.2 tls memcpy(bt, ca->ca_iot, sizeof(*bt)); 682 1.3.10.2 tls bt->hbt_cookie = sc; 683 1.3.10.2 tls bt->hbt_map = mg_eisa_memmap; 684 1.3.10.2 tls bt->hbt_unmap = mg_eisa_memunmap; 685 1.3.10.2 tls 686 1.3.10.2 tls /* attachment guts */ 687 1.3.10.2 tls ea.mongoose_eisa.eba_iot = &sc->sc_eiot; 688 1.3.10.2 tls ea.mongoose_eisa.eba_memt = &sc->sc_ememt; 689 1.3.10.2 tls ea.mongoose_eisa.eba_dmat = NULL /* &sc->sc_edmat */; 690 1.3.10.2 tls ea.mongoose_eisa.eba_ec = &sc->sc_ec; 691 1.3.10.2 tls config_found_ia(self, "eisabus", &ea.mongoose_eisa, eisabusprint); 692 1.3.10.2 tls 693 1.3.10.2 tls sc->sc_ic.ic_v = sc; 694 1.3.10.2 tls sc->sc_ic.ic_attach_hook = mg_isa_attach_hook; 695 1.3.10.2 tls sc->sc_ic.ic_detach_hook = mg_isa_detach_hook; 696 1.3.10.2 tls sc->sc_ic.ic_intr_establish = mg_intr_establish; 697 1.3.10.2 tls sc->sc_ic.ic_intr_disestablish = mg_intr_disestablish; 698 1.3.10.2 tls sc->sc_ic.ic_intr_check = mg_intr_check; 699 1.3.10.2 tls 700 1.3.10.2 tls /* inherit the bus tags for isa from the eisa */ 701 1.3.10.2 tls bt = &sc->sc_imemt; 702 1.3.10.2 tls memcpy(bt, &sc->sc_ememt, sizeof(*bt)); 703 1.3.10.2 tls bt = &sc->sc_iiot; 704 1.3.10.2 tls memcpy(bt, &sc->sc_eiot, sizeof(*bt)); 705 1.3.10.2 tls 706 1.3.10.2 tls /* TODO: DMA tags */ 707 1.3.10.2 tls 708 1.3.10.2 tls /* attachment guts */ 709 1.3.10.2 tls ea.mongoose_isa.iba_iot = &sc->sc_iiot; 710 1.3.10.2 tls ea.mongoose_isa.iba_memt = &sc->sc_imemt; 711 1.3.10.2 tls #if NISADMA > 0 712 1.3.10.2 tls ea.mongoose_isa.iba_dmat = &sc->sc_idmat; 713 1.3.10.2 tls #endif 714 1.3.10.2 tls ea.mongoose_isa.iba_ic = &sc->sc_ic; 715 1.3.10.2 tls config_found_ia(self, "isabus", &ea.mongoose_isa, isabusprint); 716 1.3.10.2 tls #undef R 717 1.3.10.2 tls 718 1.3.10.2 tls /* attach interrupt */ 719 1.3.10.2 tls sc->sc_ih = hppa_intr_establish(IPL_NONE, mg_intr, sc, &ci->ci_ir, 720 1.3.10.2 tls ca->ca_irq); 721 1.3.10.2 tls } 722
Indexes created Thu Oct 02 14:10:14 GMT 2025