ssio.c revision 1.1
1 /* $NetBSD: ssio.c,v 1.1 2014/02/24 07:23:43 skrll Exp $ */ 2 3 /* $OpenBSD: ssio.c,v 1.7 2009/03/08 22:19:04 miod Exp $ */ 4 5 /* 6 * Copyright (c) 2007 Mark Kettenis 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* 22 * Driver for the National Semiconductor PC87560 Legacy I/O chip. 23 */ 24 25 #include <sys/param.h> 26 #include <sys/systm.h> 27 #include <sys/device.h> 28 29 #include <sys/bus.h> 30 #include <machine/iomod.h> 31 32 #include <dev/pci/pcireg.h> 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 37 #include <hppa/hppa/machdep.h> 38 #include <hppa/dev/ssiovar.h> 39 40 #include "ukbd.h" 41 #if NUKBD > 0 42 #include <dev/usb/ohcireg.h> 43 #include <dev/usb/ukbdvar.h> 44 #endif 45 46 /* PCI config space. */ 47 #define SSIO_PCI_DMA_RC2 0x64 48 #define SSIO_PCI_INT_TC1 0x67 49 #define SSIO_PCI_INT_TC2 0x68 50 #define SSIO_PCI_INT_RC1 0x69 51 #define SSIO_PCI_INT_RC2 0x6a 52 #define SSIO_PCI_INT_RC3 0x6b 53 #define SSIO_PCI_INT_RC4 0x6c 54 #define SSIO_PCI_INT_RC5 0x6d 55 #define SSIO_PCI_INT_RC6 0x6e 56 #define SSIO_PCI_INT_RC7 0x6f 57 #define SSIO_PCI_INT_RC8 0x70 58 #define SSIO_PCI_INT_RC9 0x71 59 #define SSIO_PCI_SP1BAR 0x94 60 #define SSIO_PCI_SP2BAR 0x98 61 #define SSIO_PCI_PPBAR 0x9c 62 63 #define SSIO_PCI_INT_TC1_MASK 0xff 64 #define SSIO_PCI_INT_TC1_SHIFT 24 65 66 #define SSIO_PCI_INT_TC2_MASK 0xff 67 #define SSIO_PCI_INT_TC2_SHIFT 0 68 69 #define SSIO_PCI_INT_RC1_MASK 0xff 70 #define SSIO_PCI_INT_RC1_SHIFT 8 71 72 #define SSIO_PCI_INT_RC2_MASK 0xff 73 #define SSIO_PCI_INT_RC2_SHIFT 16 74 75 #define SSIO_PCI_INT_RC3_MASK 0xff 76 #define SSIO_PCI_INT_RC3_SHIFT 24 77 78 #define SSIO_PCI_INT_RC4_MASK 0xff 79 #define SSIO_PCI_INT_RC4_SHIFT 0 80 81 #define SSIO_PCI_INT_RC5_MASK 0xff 82 #define SSIO_PCI_INT_RC5_SHIFT 8 83 84 #define SSIO_PCI_INT_RC6_MASK 0xff 85 #define SSIO_PCI_INT_RC6_SHIFT 16 86 87 #define SSIO_PCI_INT_RC7_MASK 0xff 88 #define SSIO_PCI_INT_RC7_SHIFT 24 89 90 #define SSIO_PCI_INT_RC8_MASK 0xff 91 #define SSIO_PCI_INT_RC8_SHIFT 0 92 93 #define SSIO_PCI_INT_RC9_MASK 0xff 94 #define SSIO_PCI_INT_RC9_SHIFT 8 95 96 /* Cascaded i8259-compatible PICs. */ 97 #define SSIO_PIC1 0x20 98 #define SSIO_PIC2 0xa0 99 #define SSIO_NINTS 16 100 101 struct ssio_iv { 102 int (*handler)(void *); 103 void *arg; 104 }; 105 106 struct ssio_iv ssio_intr_table[SSIO_NINTS]; 107 108 struct ssio_softc { 109 bus_space_tag_t sc_iot; 110 bus_space_handle_t sc_ic1h; 111 bus_space_handle_t sc_ic2h; 112 void *sc_ih; 113 }; 114 115 int ssio_match(device_t, cfdata_t, void *); 116 void ssio_attach(device_t, device_t, void *); 117 118 CFATTACH_DECL_NEW(ssio, sizeof(struct ssio_softc), ssio_match, ssio_attach, NULL, 119 NULL); 120 121 extern struct cfdriver ssio_cd; 122 123 int ssio_intr(void *); 124 int ssio_print(void *, const char *); 125 126 int 127 ssio_match(device_t parent, cfdata_t match, void *aux) 128 { 129 struct pci_attach_args *pa = aux; 130 pcireg_t bhlc, id; 131 pcitag_t tag; 132 133 /* 134 * The firmware doesn't always switch the IDE function into native 135 * mode. So we do that ourselves since it makes life much simpler. 136 * Note that we have to do this in the match function since the 137 * Legacy I/O function attaches after the IDE function. 138 */ 139 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_NS && 140 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_PC87415) { 141 bhlc = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_BHLC_REG); 142 if (!PCI_HDRTYPE_MULTIFN(bhlc)) 143 return (0); 144 145 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 1); 146 id = pci_conf_read(pa->pa_pc, tag, PCI_ID_REG); 147 if (PCI_VENDOR(id) != PCI_VENDOR_NS || 148 PCI_PRODUCT(id) != PCI_PRODUCT_NS_PC87560) 149 return (0); 150 151 pa->pa_class |= PCIIDE_INTERFACE_PCI(0) << PCI_INTERFACE_SHIFT; 152 pa->pa_class |= PCIIDE_INTERFACE_PCI(1) << PCI_INTERFACE_SHIFT; 153 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_CLASS_REG, 154 pa->pa_class); 155 return (0); 156 } 157 158 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_NS) 159 return 0; 160 161 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_NS_PC87560) 162 return 1; 163 164 return 0; 165 } 166 167 void 168 ssio_attach(device_t parent, device_t self, void *aux) 169 { 170 struct ssio_softc *sc = device_private(self); 171 struct pci_attach_args *pa = aux; 172 struct ssio_attach_args saa; 173 pci_intr_handle_t ih; 174 char devinfo[256]; 175 const char *intrstr; 176 pcireg_t reg; 177 int revision; 178 #if NUKBD > 0 179 pcitag_t tag; 180 int pagezero_cookie; 181 #endif 182 183 pci_devinfo(pa->pa_id, pa->pa_class, 0, devinfo, sizeof devinfo); 184 revision = PCI_REVISION(pa->pa_class); 185 aprint_normal(": %s (rev. 0x%02x)\n", devinfo, revision); 186 187 sc->sc_iot = pa->pa_iot; 188 if (bus_space_map(sc->sc_iot, SSIO_PIC1, 2, 0, &sc->sc_ic1h)) { 189 aprint_error_dev(self, "unable to map PIC1 registers\n"); 190 return; 191 } 192 if (bus_space_map(sc->sc_iot, SSIO_PIC2, 2, 0, &sc->sc_ic2h)) { 193 aprint_error_dev(self, "unable to map PIC2 registers\n"); 194 goto unmap_ic1; 195 } 196 197 if (pci_intr_map(pa, &ih)) { 198 aprint_error_dev(self, "unable to map interrupt\n"); 199 goto unmap_ic2; 200 } 201 intrstr = pci_intr_string(pa->pa_pc, ih); 202 sc->sc_ih = pci_intr_establish(pa->pa_pc, ih, IPL_TTY, ssio_intr, 203 sc); 204 if (sc->sc_ih == NULL) { 205 aprint_error_dev(self, "could not establish interrupt"); 206 if (intrstr != NULL) 207 aprint_error(" at %s", intrstr); 208 aprint_error("\n"); 209 goto unmap_ic2; 210 } 211 aprint_normal_dev(self, "interrupting at %s\n", intrstr); 212 213 /* 214 * We use the following interrupt mapping: 215 * 216 * USB (INTD#) IRQ 1 217 * IDE Channel 1 IRQ 5 218 * Serial Port 1 IRQ 4 219 * Serial Port 2 IRQ 3 220 * Parallel Port IRQ 7 221 * 222 * USB and IDE are set to level triggered, all others to edge 223 * triggered. 224 * 225 * We disable all other interrupts since we don't need them. 226 */ 227 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2); 228 reg &= ~(SSIO_PCI_INT_TC1_MASK << SSIO_PCI_INT_TC1_SHIFT); 229 reg |= 0x22 << SSIO_PCI_INT_TC1_SHIFT; 230 pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_DMA_RC2, reg); 231 232 reg = 0; 233 reg |= 0x34 << SSIO_PCI_INT_RC1_SHIFT; /* SP1, SP2 */ 234 reg |= 0x07 << SSIO_PCI_INT_RC2_SHIFT; /* PP */ 235 reg |= 0x05 << SSIO_PCI_INT_RC3_SHIFT; /* IDE1 */ 236 pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_TC2, reg); 237 238 reg = 0; 239 reg |= 0x10 << SSIO_PCI_INT_RC5_SHIFT; /* INTD# (USB) */ 240 pci_conf_write(pa->pa_pc, pa->pa_tag, SSIO_PCI_INT_RC4, reg); 241 242 /* Program PIC1. */ 243 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0x11); 244 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 1, 0x00); 245 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 1, 0x04); 246 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 1, 0x01); 247 248 /* Priority (3-7,0-2). */ 249 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0xc2); 250 251 /* Program PIC2. */ 252 bus_space_write_1(sc->sc_iot, sc->sc_ic2h, 0, 0x11); 253 bus_space_write_1(sc->sc_iot, sc->sc_ic2h, 1, 0x00); 254 bus_space_write_1(sc->sc_iot, sc->sc_ic2h, 1, 0x02); 255 bus_space_write_1(sc->sc_iot, sc->sc_ic2h, 1, 0x01); 256 257 /* Unmask all interrupts. */ 258 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 1, 0x00); 259 bus_space_write_1(sc->sc_iot, sc->sc_ic2h, 1, 0x00); 260 261 /* Serial Port 1. */ 262 saa.saa_name = "com"; 263 saa.saa_iot = sc->sc_iot; 264 saa.saa_iobase = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_SP1BAR); 265 saa.saa_iobase &= 0xfffffffe; 266 saa.saa_irq = 4; 267 config_found(self, &saa, ssio_print); 268 269 /* Serial Port 2. */ 270 saa.saa_name = "com"; 271 saa.saa_iot = sc->sc_iot; 272 saa.saa_iobase = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_SP2BAR); 273 saa.saa_iobase &= 0xfffffffe; 274 saa.saa_irq = 3; 275 config_found(self, &saa, ssio_print); 276 277 /* Parallel Port. */ 278 saa.saa_name = "lpt"; 279 saa.saa_iot = sc->sc_iot; 280 saa.saa_iobase = pci_conf_read(pa->pa_pc, pa->pa_tag, SSIO_PCI_PPBAR); 281 saa.saa_iobase &= 0xfffffffe; 282 saa.saa_irq = 7; 283 config_found(self, &saa, ssio_print); 284 285 #if NUKBD > 0 286 /* 287 * If a USB keybard is used for console input, the firmware passes 288 * the mmio address of the USB controller the keyboard is attached 289 * to. Since we know the USB controller is function 2 on the same 290 * device and comes right after us (we're function 1 remember), 291 * this is a convenient spot to mark the USB keyboard as console 292 * if the address matches. 293 */ 294 tag = pci_make_tag(pa->pa_pc, pa->pa_bus, pa->pa_device, 2); 295 reg = pci_conf_read(pa->pa_pc, tag, PCI_CBMEM); 296 297 pagezero_cookie = hppa_pagezero_map(); 298 if (PAGE0->mem_kbd.pz_class == PCL_KEYBD && 299 PAGE0->mem_kbd.pz_hpa == (struct iomod *)reg) 300 ukbd_cnattach(); 301 hppa_pagezero_unmap(pagezero_cookie); 302 #endif 303 304 return; 305 306 unmap_ic2: 307 bus_space_unmap(sc->sc_iot, sc->sc_ic2h, 2); 308 unmap_ic1: 309 bus_space_unmap(sc->sc_iot, sc->sc_ic1h, 2); 310 } 311 312 int 313 ssio_intr(void *v) 314 { 315 struct ssio_softc *sc = v; 316 struct ssio_iv *iv; 317 int claimed = 0; 318 int irq, isr; 319 320 /* Poll for interrupt. */ 321 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0x0c); 322 irq = bus_space_read_1(sc->sc_iot, sc->sc_ic1h, 0); 323 irq &= 0x07; 324 325 if (irq == 7) { 326 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0x0b); 327 isr = bus_space_read_1(sc->sc_iot, sc->sc_ic1h, 0); 328 if ((isr & 0x80) == 0) 329 /* Spurious interrupt. */ 330 return (0); 331 } 332 333 iv = &ssio_intr_table[irq]; 334 if (iv->handler) 335 claimed = iv->handler(iv->arg); 336 337 /* Signal EOI. */ 338 bus_space_write_1(sc->sc_iot, sc->sc_ic1h, 0, 0x60 | (irq & 0x0f)); 339 340 return (claimed); 341 } 342 343 void * 344 ssio_intr_establish(int pri, int irq, int (*handler)(void *), void *arg, 345 const char *name) 346 { 347 struct ssio_iv *iv; 348 349 if (irq < 0 || irq >= SSIO_NINTS || ssio_intr_table[irq].handler) 350 return (NULL); 351 352 iv = &ssio_intr_table[irq]; 353 iv->handler = handler; 354 iv->arg = arg; 355 356 return (iv); 357 } 358 359 int 360 ssio_print(void *aux, const char *pnp) 361 { 362 struct ssio_attach_args *saa = aux; 363 364 if (pnp) 365 printf("%s at %s", saa->saa_name, pnp); 366 if (saa->saa_iobase) { 367 printf(" offset %lx", saa->saa_iobase); 368 if (!pnp && saa->saa_irq >= 0) 369 printf(" irq %d", saa->saa_irq); 370 } 371 372 return (UNCONF); 373 } 374
Indexes created Thu Oct 23 22:10:10 GMT 2025