db_disasm.c revision 1.13
1 /* $NetBSD: db_disasm.c,v 1.13 2012/01/16 09:01:35 skrll Exp $ */ 2 3 /* $OpenBSD: db_disasm.c,v 1.9 2000/04/18 20:02:45 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999,2005 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN 18 * AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT 19 * OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 /* 22 * (c) Copyright 1992 HEWLETT-PACKARD COMPANY 23 * 24 * To anyone who acknowledges that this file is provided "AS IS" 25 * without any express or implied warranty: 26 * permission to use, copy, modify, and distribute this file 27 * for any purpose is hereby granted without fee, provided that 28 * the above copyright notice and this notice appears in all 29 * copies, and that the name of Hewlett-Packard Company not be 30 * used in advertising or publicity pertaining to distribution 31 * of the software without specific, written prior permission. 32 * Hewlett-Packard Company makes no representations about the 33 * suitability of this software for any purpose. 34 */ 35 36 /* 37 * unasm.c -- HP_PA Instruction Printer 38 */ 39 40 #include <sys/cdefs.h> 41 __KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.13 2012/01/16 09:01:35 skrll Exp $"); 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 46 #include <machine/db_machdep.h> 47 #include <ddb/db_access.h> 48 #include <ddb/db_sym.h> 49 #include <ddb/db_output.h> 50 #include <ddb/db_interface.h> 51 52 53 /* IMPORTANT NOTE: 54 * All modules using this header may assume that the datatype "int" is a 55 * 32-bit (or > 32-bit) signed quantity. 56 */ 57 58 59 /* Spectrum Architecturally Defined Datatypes */ 60 struct doubleword { 61 int wd0; 62 int wd1; 63 }; 64 65 struct quadword { 66 struct doubleword d0; 67 struct doubleword d1; 68 }; 69 70 /* datatypes for halfword and byte fields of a word are defined 71 * in ssBits.h */ 72 73 /* Memory addressing datatypes */ 74 typedef unsigned int SID, /* range [0..MAXSID] */ 75 PGID, /* range [0..MAXPGID] */ 76 OFS, /* range [0..MAXINT] */ 77 REALADR; /* range [0..MAXINT] */ 78 79 80 /* data sizes */ 81 enum datasize { Byte, Halfword, Word, Doubleword, Quadword, Variable }; 82 83 /* Miscellaneous datatypes */ 84 typedef unsigned int FLAGS; 85 86 /* struct for entry in unwind table */ 87 struct ute { 88 int word1; 89 int word2; 90 int word3; 91 int word4; 92 }; 93 /* 94 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 95 * 96 * Spectrum Instruction Set Condition Completer Bit Assignments 97 * Dan Magenheimer - 6/14/82 98 * Terrence Miller - 6/21/82 99 * Computer Research Center, Hewlett-Packard Labs 100 * 101 * (c) copyright 1982 102 * (p) protected 1982 103 * The Hewlett-Packard Company 104 * Hewlett-Packard Laboratories 105 * Computer Research Center 106 * Palo Alto, California 107 * 108 * *** HP Company Confidential *** 109 * 110 * Log: unasm.c,v 111 * Revision 1.5 1994/07/21 22:32:05 mike 112 * official HP copyright notice 113 * 114 * Revision 1.4 1992/07/08 12:19:52 dalton 115 * Checkin before split to 1.0.4 release (by LBS). 116 * 117 * Revision 1.3 92/06/06 16:16:45 dalton 118 * *** empty log message *** 119 * 120 * Revision 1.2 92/06/06 15:42:28 dalton 121 * Changed include to be a path relative to hp800. 122 * 123 * Revision 1.1 92/06/06 14:05:33 dalton 124 * Initial revision 125 * 126 * Revision 1.2 91/04/14 20:29:49 osfrcs 127 * Initial version. 128 * [91/03/30 09:20:34 brezak] 129 * 130 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 131 * Initial version. 132 * [91/03/30 09:20:34 brezak] 133 * 134 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 135 * Initial version. 136 * 137 * Revision 1.1 88/07/11 14:05:15 14:05:15 ren (Bob Naas) 138 * Initial revision 139 * 140 * Revision 5.2 87/07/02 14:45:57 14:45:57 kent (Kent McMullen) 141 * added constants to support addDasm and addDCond added to ssDID.c 142 * 143 * Revision 5.1 87/02/27 11:12:08 11:12:08 kent (Kent McMullen) 144 * update all src to 5.1 145 * 146 * Revision 5.0 87/02/18 16:31:15 16:31:15 kent (Kent McMullen) 147 * update all revision numbers to 5.0 for release 148 * 149 * Revision 1.1 86/07/15 08:34:55 08:34:55 kent (Kent McMullen) 150 * Initial revision 151 * 152 * Revision 4.1 83/10/25 17:01:22 17:01:22 djm (Daniel J Magenheimer) 153 * First release for ACD v4 154 * 155 * Revision 3.0 83/06/13 10:22:59 djm (Daniel Magenheimer) 156 * First release for distribution 157 * 158 * 159 */ 160 161 162 /* Arithmetic/Logical Conditions */ 163 #define NEV 0x0 164 #define EQZ 0x2 165 #define LT 0x4 166 #define LE 0x6 167 #define LLT 0x8 168 #define NUV 0x8 169 #define LLE 0xA 170 #define ZNV 0xA 171 #define SV 0xC 172 #define OD 0xE 173 #define TR 0x1 174 #define NEQZ 0x3 175 #define GE 0x5 176 #define GT 0x7 177 #define LGE 0x9 178 #define UV 0x9 179 #define LGT 0xB 180 #define VNZ 0xB 181 #define NSV 0xD 182 #define EV 0xF 183 184 /* unit conditions */ 185 #define SBZ 0x4 186 #define SHZ 0x6 187 #define SDC 0x8 188 #define SBC 0xC 189 #define SHC 0xE 190 #define NBZ 0x5 191 #define NHZ 0x7 192 #define NDC 0x9 193 #define NBC 0xD 194 #define NHC 0xF 195 196 /*field conditions */ 197 #define XEQ 0x1 198 #define XLT 0x2 199 #define XOD 0x3 200 #define XTR 0x4 201 #define XNE 0x5 202 #define XGE 0x6 203 #define XEV 0x7 204 205 206 207 /* 208 * These macros are designed to be portable to all machines that have 209 * a wordsize greater than or equal to 32 bits that support the portable 210 * C compiler and the standard C preprocessor. Wordsize (default 32) 211 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11) 212 * should be predefined using the constants HOSTWDSZ and BITFRL and 213 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20). 214 * Note that the macro arguments assume that the integer being referenced 215 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the 216 * most significant bit. 217 */ 218 219 #ifndef HOSTWDSZ 220 #define HOSTWDSZ 32 221 #endif 222 223 #ifdef vax 224 #ifndef BITFLR 225 #define BITFRL 226 #endif 227 #else 228 #define BITFLR 229 #endif 230 231 /*########################### Macros ######################################*/ 232 233 /*--------------------------------------------------------------------------- 234 * DeclareBitfield$Reference - Declare a structure to be used to reference 235 * a specified bitfield within an integer (using BitfR, see below). 236 * The argument "n" must be an identifier name not used elsewhere in the 237 * program , "s" and "l" must (alas!) be constants. (Suggestion: if 238 * "s" == 2 and "l" == 8, use _b28 for "n".) The name "BITFLR" should 239 * be pre-defined if the compiler assigns bitfields from left-to-right. 240 * The resultant macro expansion defines a structure in which the bit field 241 * starting at position "s" with length "l" may be referenced by accessing 242 * member "n". [Note: The leftmost bits in a 36-bit word may be accessed 243 * by specifying -4 <= s < 0 on the DEC-20.] 244 *---------------------------------------------------------------------------*/ 245 246 #ifdef BITFRL 247 #define DeclBitfR(s,l,n) struct n { int:(HOSTWDSZ-(s)-(l)); unsigned n:l;} n; 248 #else 249 #define DeclBitfR(s,l,n) struct n { int:((s)+(HOSTWDSZ-32)); unsigned n:l;} n; 250 #endif 251 252 /*--------------------------------------------------------------------------- 253 * Bitfield$Reference - Reference a specified bitfield within an integer. 254 * The argument "i" must be an addressable variable (i.e., not a register 255 * variable or an expression... but see BitfX below), "n" must be an 256 * identifier name declared in a DeclBitfR invocation. The resultant 257 * macro expansion references the bit field in "i" described by the 258 * DeclBitfR invocation with the same name ("n"). BitfR may be used as 259 * an lvalue or an rvalue. (i.e., either side of an assignment statement) 260 * The "s" and "l" arguments are historical and are now unused. (They 261 * correspond to the "s" and "l" arguments in DeclBitfR) 262 * Translates to a single instruction on both the VAX and the DEC-20. 263 *---------------------------------------------------------------------------*/ 264 #define BitfR(i,s,l,n) (i.n.n) 265 266 /*--------------------------------------------------------------------------- 267 * Bitfield$eXtract - Extract the specified field from an integer. Arguments 268 * are the same as for BitfR (except no "n"), however both "s" and "l" need 269 * no longer be constants. May only be used as an rvalue. Translates to 270 * two instructions on the VAX, three on the DEC-20. 271 *---------------------------------------------------------------------------*/ 272 273 #define BitfX(i,s,l) (((i.w) >> (32-(s)-(l))) & ((1 << (l)) - 1)) 274 275 276 /*--------------------------------------------------------------------------- 277 * Mask$32bits - Mask the low order 32 bits of passed word. No-op on 32 278 * bit machines. 279 *---------------------------------------------------------------------------*/ 280 281 #if HOSTWDSZ > 32 282 #define Mask32(x) ((x) & 0xffffffff) 283 #else 284 #define Mask32(x) (x) 285 #endif 286 287 288 /*--------------------------------------------------------------------------- 289 * SignExtend$32bits - Force the high-order bits in machines with wordsize 290 * longer than 32 to match bit 0. 291 *---------------------------------------------------------------------------*/ 292 293 #if HOSTWDSZ > 32 294 #define SignEx32(x) (((x) & 0x80000000) ? ((x) | ((unsigned)-1 << 32)) \ 295 : Mask32(x)) 296 #else 297 #define SignEx32(x) (x) 298 #endif 299 300 /**************************/ 301 /* bit field declarations */ 302 /**************************/ 303 304 /* since the compiler complains if a structure name is declared twice, even 305 * if the declarations are identical, all DeclBitfR invocations are 306 * given here in one file. */ 307 308 union insn { 309 int w; 310 DeclBitfR(0,1,_b01) 311 DeclBitfR(0,15,_b015) 312 DeclBitfR(0,16,_b016) 313 DeclBitfR(0,4,_b04) 314 DeclBitfR(0,6,_b06) 315 DeclBitfR(0,8,_b08) 316 DeclBitfR(4,1,_b41) 317 DeclBitfR(4,4,_b44) 318 DeclBitfR(6,1,_b61) 319 DeclBitfR(6,13,_b613) 320 DeclBitfR(6,15,_b615) 321 DeclBitfR(6,17,_b617) 322 DeclBitfR(6,26,_b626) 323 DeclBitfR(6,5,_b65) 324 DeclBitfR(7,1,_b71) 325 DeclBitfR(8,1,_b81) 326 DeclBitfR(8,4,_b84) 327 DeclBitfR(8,8,_b88) 328 DeclBitfR(9,1,_b91) 329 DeclBitfR(10,1,_b101) 330 DeclBitfR(11,1,_b111) 331 DeclBitfR(11,10,_b1110) 332 DeclBitfR(11,4,_b114) 333 DeclBitfR(11,5,_b115) 334 DeclBitfR(12,1,_b121) 335 DeclBitfR(12,4,_b124) 336 DeclBitfR(13,1,_b131) 337 DeclBitfR(14,1,_b141) 338 DeclBitfR(15,1,_b151) 339 DeclBitfR(16,1,_b161) 340 DeclBitfR(16,15,_b1615) 341 DeclBitfR(16,16,_b1616) 342 DeclBitfR(16,2,_b162) 343 DeclBitfR(16,3,_b163) 344 DeclBitfR(16,4,_b164) 345 DeclBitfR(16,5,_b165) 346 DeclBitfR(16,8,_b168) 347 DeclBitfR(17,1,_b171) 348 DeclBitfR(18,1,_b181) 349 DeclBitfR(18,13,_b1813) 350 DeclBitfR(18,2,_b182) 351 DeclBitfR(18,7,_b187) 352 DeclBitfR(19,1,_b191) 353 DeclBitfR(19,8,_b198) 354 DeclBitfR(19,10,_b1910) 355 DeclBitfR(20,11,_b2011) 356 DeclBitfR(20,2,_b202) 357 DeclBitfR(20,4,_b204) 358 DeclBitfR(21,10,_b2110) 359 DeclBitfR(21,2,_b212) 360 DeclBitfR(21,5,_b215) 361 DeclBitfR(22,5,_b225) 362 DeclBitfR(23,3,_b233) 363 DeclBitfR(24,1,_b241) 364 DeclBitfR(24,4,_b244) 365 DeclBitfR(24,8,_b248) 366 DeclBitfR(25,1,_b251) 367 DeclBitfR(26,1,_b261) 368 DeclBitfR(27,1,_b271) 369 DeclBitfR(27,4,_b274) 370 DeclBitfR(27,5,_b275) 371 DeclBitfR(28,1,_b281) 372 DeclBitfR(28,4,_b284) 373 DeclBitfR(29,1,_b291) 374 DeclBitfR(30,1,_b301) 375 DeclBitfR(30,2,_b302) 376 DeclBitfR(31,1,_b311) 377 }; 378 379 /******************/ 380 /* Word subfields */ 381 /******************/ 382 383 #define Sign(i) BitfR(i,0,1,_b01) 384 /* halfwords */ 385 #define Hwd0(i) BitfR(i,0,16,_b016) 386 #define Hwd1sign(i) BitfR(i,16,1,_b161) 387 #define Hwd1(i) BitfR(i,16,16,_b1616) 388 /* bytes */ 389 #define Byte0(i) BitfR(i,0,8,_b08) 390 #define Byte1sign(i) BitfR(i,8,1,_b81) 391 #define Byte1(i) BitfR(i,8,8,_b88) 392 #define Byte2(i) BitfR(i,16,8,_b168) 393 #define Byte3sign(i) BitfR(i,24,1,_b241) 394 #define Byte3(i) BitfR(i,24,8,_b248) 395 /* digits */ 396 #define Digit0(i) BitfR(i,0,4,_b04) 397 #define Digit1(i) BitfR(i,4,4,_b44) 398 #define Digit2(i) BitfR(i,8,4,_b84) 399 #define Digit3(i) BitfR(i,12,4,_b124) 400 #define Digit4(i) BitfR(i,16,4,_b164) 401 #define Digit5(i) BitfR(i,20,4,_b204) 402 #define Digit6(i) BitfR(i,24,4,_b244) 403 #define Digit7(i) BitfR(i,28,4,_b284) 404 405 /* Wordsize definitions */ 406 407 #define BIT_P_DW 64 /* bits/doubleword */ 408 #define BIT_P_WD 32 /* bits/word */ 409 #define BIT_P_HW 16 /* bits/halfword */ 410 #define BIT_P_BYT 8 /* bits/byte */ 411 #define BYT_P_DW 8 /* bytes/doubleword */ 412 #define BYT_P_WD 4 /* bytes/word */ 413 #define BYT_P_HW 2 /* bytes/halfword */ 414 415 /* Masks */ 416 417 #define WDMASK 0xffffffff /* 32-bit mask */ 418 #define OFSMASK 0xffffffff /* 32-bit mask */ 419 #define SIDMASK 0xffffffff /* 32-bit mask */ 420 #define SIGNMASK 0x80000000 /* 32 bit word sign bit */ 421 422 /* Alignments */ 423 424 #define wdalign(ofs) (ofs &= ~3) 425 /* 426 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 427 * 428 * Spectrum Simulator Instruction Opcode Definitions 429 * Dan Magenheimer 430 * Computer Research Center, Hewlett-Packard Labs 431 * 432 * (c) copyright 1982 433 * (p) protected 1982 434 * The Hewlett-Packard Company 435 * Hewlett-Packard Laboratories 436 * Computer Research Center 437 * Palo Alto, California 438 * 439 * *** HP Company Confidential *** 440 * 441 * Log: unasm.c,v 442 * Revision 1.5 1994/07/21 22:32:05 mike 443 * official HP copyright notice 444 * 445 * Revision 1.4 1992/07/08 12:19:52 dalton 446 * Checkin before split to 1.0.4 release (by LBS). 447 * 448 * Revision 1.3 92/06/06 16:16:45 dalton 449 * *** empty log message *** 450 * 451 * Revision 1.2 92/06/06 15:42:28 dalton 452 * Changed include to be a path relative to hp800. 453 * 454 * Revision 1.1 92/06/06 14:05:33 dalton 455 * Initial revision 456 * 457 * Revision 1.2 91/04/14 20:29:49 osfrcs 458 * Initial version. 459 * [91/03/30 09:20:34 brezak] 460 * 461 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 462 * Initial version. 463 * [91/03/30 09:20:34 brezak] 464 * 465 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 466 * Initial version. 467 * 468 * Revision 6.1 89/09/06 10:39:58 burroughs 469 * Added shadow registers for gr0-gr7. 470 * gr0-7 are copied into sh0-7 whenever a trap occurs 471 * the instruction RFIR restores gr0-7 from sh0-7 and returns from 472 * interrupt. 473 * the "sh" command displays the shadow registers 474 * = sh7 0x789 works, too. 475 * 476 * Revision 6.0 89/09/01 15:46:37 15:46:37 burroughs (Greg Burroughs) 477 * baseline for pcx simple offsite 478 * 479 * Revision 5.2 87/09/02 14:30:23 14:30:23 kent 480 * separated stat gathering for indexed vs short. 481 * this will NOT work if cache hints ever get used 482 * since this field was assumed always zero 483 * 484 * Revision 5.1 87/02/27 11:12:16 11:12:16 kent (Kent McMullen) 485 * update all src to 5.1 486 * 487 * Revision 5.0 87/02/18 16:31:35 16:31:35 kent (Kent McMullen) 488 * update all revision numbers to 5.0 for release 489 * 490 * Revision 1.1 86/07/15 08:34:57 08:34:57 kent (Kent McMullen) 491 * Initial revision 492 * 493 * Revision 4.1 83/10/25 17:02:34 17:02:34 djm (Daniel J Magenheimer) 494 * First release for ACD v4 495 * 496 * Revision 3.0 83/06/13 10:24:45 djm (Daniel Magenheimer) 497 * First release for distribution 498 * 499 * 500 */ 501 502 /* 503 * Changes: 504 * 01/30/90 ejf Simplify SPOPn support, now only gives assist emulation trap. 505 * 01/19/90 ejf Replace linpak instructions with just FSTQ[SX]. 506 * 12/19/89 ejf Add PA89 new floating point opcode 0E. 507 * 12/18/89 ejf Change 5 ops to PA89 format. 508 * 12/01/89 ejf Move additional instructions fmas, fmaa, fld2, fst2 to ssILst 509 * 09/22/89 ejf Fix unbalanced comments. 510 */ 511 512 513 /* ..and modified by hand to remove the load/store short references */ 514 /* ..and modified by hand to make memory management ops conform to the 515 * requirement that all subops of a major opcode begin in the same 516 * place and have the same length */ 517 518 #define LDW 0x12, 0x00, 0, 0 /* LOAD WORD */ 519 #define LDWM 0x13, 0x00, 0, 0 /* LOAD WORD and MODIFY */ 520 #define LDH 0x11, 0x00, 0, 0 /* LOAD HALFWORD */ 521 #define LDB 0x10, 0x00, 0, 0 /* LOAD BYTE */ 522 #define LDO 0x0d, 0x00, 0, 0 /* LOAD OFFSET */ 523 #define STW 0x1a, 0x00, 0, 0 /* STORE WORD */ 524 #define STWM 0x1b, 0x00, 0, 0 /* STORE WORD and MODIFY */ 525 #define STH 0x19, 0x00, 0, 0 /* STORE HALFWORD */ 526 #define STB 0x18, 0x00, 0, 0 /* STORE BYTE */ 527 #define LDWX 0x03, 0x02, 19, 7 /* LOAD WORD INDEXED */ 528 #define LDHX 0x03, 0x01, 19, 7 /* LOAD HALFWORD INDEXED */ 529 #define LDBX 0x03, 0x00, 19, 7 /* LOAD BYTE INDEXED */ 530 #define LDWAX 0x03, 0x06, 19, 7 /* LOAD WORD ABSOLUTE INDEXED */ 531 #define LDCWX 0x03, 0x07, 19, 7 /* LOAD and CLEAR WORD INDEXED */ 532 #define LDWS 0x03, 0x42, 19, 7 /* LOAD WORD SHORT DISP */ 533 #define LDHS 0x03, 0x41, 19, 7 /* LOAD HALFWORD SHORT DISP */ 534 #define LDBS 0x03, 0x40, 19, 7 /* LOAD BYTE SHORT DISP */ 535 #define LDWAS 0x03, 0x46, 19, 7 /* LOAD WORD ABSOLUTE SHORT DISP */ 536 #define LDCWS 0x03, 0x47, 19, 7 /* LOAD and CLEAR WORD SHORT DISP */ 537 #define STWS 0x03, 0x4a, 19, 7 /* STORE WORD SHORT DISP */ 538 #define STHS 0x03, 0x49, 19, 7 /* STORE HALFWORD SHORT DISP */ 539 #define STBS 0x03, 0x48, 19, 7 /* STORE BYTE SHORT DISP */ 540 #define STWAS 0x03, 0x4e, 19, 7 /* STORE WORD ABSOLUTE SHORT DISP */ 541 #define STBYS 0x03, 0x4c, 19, 7 /* STORE BYTES SHORT DISP */ 542 #define LDIL 0x08, 0x00, 0, 0 /* LOAD IMMED LEFT */ 543 #define ADDIL 0x0a, 0x00, 0, 0 /* ADD IMMED LEFT */ 544 #define BL 0x3a, 0x00, 16, 3 /* BRANCH [and LINK] */ 545 #define GATE 0x3a, 0x01, 16, 3 /* GATEWAY */ 546 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ 547 #define BV 0x3a, 0x06, 16, 3 /* BRANCH VECTORED */ 548 #define BE 0x38, 0x00, 0, 0 /* BRANCH EXTERNAL */ 549 #define BLE 0x39, 0x00, 0, 0 /* BRANCH and LINK EXTERNAL */ 550 #define MOVB 0x32, 0x00, 0, 0 /* MOVE and BRANCH */ 551 #define MOVIB 0x33, 0x00, 0, 0 /* MOVE IMMED and BRANCH */ 552 #define COMBT 0x20, 0x00, 0, 0 /* COMPARE and BRANCH if TRUE */ 553 #define COMBF 0x22, 0x00, 0, 0 /* COMPARE and BRANCH if FALSE */ 554 #define COMIBT 0x21, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if TRUE */ 555 #define COMIBF 0x23, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if FALSE */ 556 #define ADDBT 0x28, 0x00, 0, 0 /* ADD and BRANCH if TRUE */ 557 #define ADDBF 0x2a, 0x00, 0, 0 /* ADD and BRANCH if FALSE */ 558 #define ADDIBT 0x29, 0x00, 0, 0 /* ADD IMMED and BRANCH if TRUE */ 559 #define ADDIBF 0x2b, 0x00, 0, 0 /* ADD IMMED and BRANCH if FALSE */ 560 #define BVB 0x30, 0x00, 0, 0 /* BRANCH on VARIABLE BIT */ 561 #define BB 0x31, 0x00, 0, 0 /* BRANCH on BIT */ 562 #define ADD 0x02, 0x30, 20, 7 /* ADD */ 563 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ 564 #define ADDO 0x02, 0x70, 20, 7 /* ADD and TRAP on OVFLO */ 565 #define SH1ADD 0x02, 0x32, 20, 7 /* SHIFT 1, ADD */ 566 #define SH1ADDL 0x02, 0x52, 20, 7 /* SHIFT 1, ADD LOGICAL */ 567 #define SH1ADDO 0x02, 0x72, 20, 7 /* SHIFT 1, ADD and TRAP on OVFLO */ 568 #define SH2ADD 0x02, 0x34, 20, 7 /* SHIFT 2, ADD */ 569 #define SH2ADDL 0x02, 0x54, 20, 7 /* SHIFT 2, ADD LOGICAL */ 570 #define SH2ADDO 0x02, 0x74, 20, 7 /* SHIFT 2, ADD and TRAP on OVFLO */ 571 #define SH3ADD 0x02, 0x36, 20, 7 /* SHIFT 3, ADD */ 572 #define SH3ADDL 0x02, 0x56, 20, 7 /* SHIFT 3, ADD LOGICAL */ 573 #define SH3ADDO 0x02, 0x76, 20, 7 /* SHIFT 3, ADD and TRAP on OVFLO */ 574 #define ADDC 0x02, 0x38, 20, 7 /* ADD with CARRY */ 575 #define ADDCO 0x02, 0x78, 20, 7 /* ADD with CARRY and TRAP on OVFLO */ 576 #define SUB 0x02, 0x20, 20, 7 /* SUBTRACT */ 577 #define SUBO 0x02, 0x60, 20, 7 /* SUBTRACT and TRAP on OVFLO */ 578 #define SUBB 0x02, 0x28, 20, 7 /* SUBTRACT with BORROW */ 579 #define SUBBO 0x02, 0x68, 20, 7 /* SUBTRACT with BORROW and TRAP on OVFLO */ 580 #define SUBT 0x02, 0x26, 20, 7 /* SUBTRACT and TRAP on COND */ 581 #define SUBTO 0x02, 0x66, 20, 7 /* SUBTRACT and TRAP on COND or OVFLO */ 582 #define DS 0x02, 0x22, 20, 7 /* DIVIDE STEP */ 583 #define COMCLR 0x02, 0x44, 20, 7 /* COMPARE and CLEAR */ 584 #define OR 0x02, 0x12, 20, 7 /* INCLUSIVE OR */ 585 #define XOR 0x02, 0x14, 20, 7 /* EXCLUSIVE OR */ 586 #define AND 0x02, 0x10, 20, 7 /* AND */ 587 #define ANDCM 0x02, 0x00, 20, 7 /* AND COMPLEMENT */ 588 #define UXOR 0x02, 0x1c, 20, 7 /* UNIT XOR */ 589 #define UADDCM 0x02, 0x4c, 20, 7 /* UNIT ADD COMPLEMENT */ 590 #define UADDCMT 0x02, 0x4e, 20, 7 /* UNIT ADD COMPLEMENT and TRAP on COND */ 591 #define DCOR 0x02, 0x5c, 20, 7 /* DECIMAL CORRECT */ 592 #define IDCOR 0x02, 0x5e, 20, 7 /* INTERMEDIATE DECIMAL CORRECT */ 593 #define ADDI 0x2d, 0x00, 20, 1 /* ADD to IMMED */ 594 #define ADDIO 0x2d, 0x01, 20, 1 /* ADD to IMMED and TRAP on OVFLO */ 595 #define ADDIT 0x2c, 0x00, 20, 1 /* ADD to IMMED and TRAP on COND */ 596 #define ADDITO 0x2c, 0x01, 20, 1 /* ADD to IMMED and TRAP on COND or OVFLO */ 597 #define SUBI 0x25, 0x00, 20, 1 /* SUBTRACT from IMMED */ 598 #define SUBIO 0x25, 0x01, 20, 1 /* SUBTRACT from IMMED and TRAP on OVFLO */ 599 #define COMICLR 0x24, 0x00, 0, 0 /* COMPARE IMMED and CLEAR */ 600 #define VSHD 0x34, 0x00, 19, 3 /* VARIABLE SHIFT DOUBLE */ 601 #define SHD 0x34, 0x02, 19, 3 /* SHIFT DOUBLE */ 602 #define VEXTRU 0x34, 0x04, 19, 3 /* VARIABLE EXTRACT RIGHT UNSIGNED */ 603 #define VEXTRS 0x34, 0x05, 19, 3 /* VARIABLE EXTRACT RIGHT SIGNED */ 604 #define EXTRU 0x34, 0x06, 19, 3 /* EXTRACT RIGHT UNSIGNED */ 605 #define EXTRS 0x34, 0x07, 19, 3 /* EXTRACT RIGHT SIGNED */ 606 #define VDEP 0x35, 0x01, 19, 3 /* VARIABLE DEPOSIT */ 607 #define DEP 0x35, 0x03, 19, 3 /* DEPOSIT */ 608 #define VDEPI 0x35, 0x05, 19, 3 /* VARIABLE DEPOSIT IMMED */ 609 #define DEPI 0x35, 0x07, 19, 3 /* DEPOSIT IMMED */ 610 #define ZVDEP 0x35, 0x00, 19, 3 /* ZERO and VARIABLE DEPOSIT */ 611 #define ZDEP 0x35, 0x02, 19, 3 /* ZERO and DEPOSIT */ 612 #define ZVDEPI 0x35, 0x04, 19, 3 /* ZERO and VARIABLE DEPOSIT IMMED */ 613 #define ZDEPI 0x35, 0x06, 19, 3 /* ZERO and DEPOSIT IMMED */ 614 #define BREAK 0x00, 0x00, 19, 8 /* BREAK */ 615 #define RFI 0x00, 0x60, 19, 8 /* RETURN FROM INTERRUPTION */ 616 #define RFIR 0x00, 0x65, 19, 8 /* RFI & RESTORE SHADOW REGISTERS */ 617 #define SSM 0x00, 0x6b, 19, 8 /* SET SYSTEM MASK */ 618 #define RSM 0x00, 0x73, 19, 8 /* RESET SYSTEM MASK */ 619 #define MTSM 0x00, 0xc3, 19, 8 /* MOVE TO SYSTEM MASK */ 620 #define LDSID 0x00, 0x85, 19, 8 /* LOAD SPACE IDENTIFIER */ 621 #define MTSP 0x00, 0xc1, 19, 8 /* MOVE TO SPACE REGISTER */ 622 #define MTCTL 0x00, 0xc2, 19, 8 /* MOVE TO SYSTEM CONTROL REGISTER */ 623 #define MFSP 0x00, 0x25, 19, 8 /* MOVE FROM SPACE REGISTER */ 624 #define MFCTL 0x00, 0x45, 19, 8 /* MOVE FROM SYSTEM CONTROL REGISTER */ 625 #define SYNC 0x00, 0x20, 19, 8 /* SYNCHRONIZE DATA CACHE */ 626 #define DIAG 0x05, 0x00, 0, 0 /* DIAGNOSE */ 627 #define SPOP 0x04, 0x00, 0, 0 /* SPECIAL FUNCTION UNIT */ 628 #define COPR 0x0c, 0x00, 0, 0 /* COPROCESSOR */ 629 #define CLDWX 0x09, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 630 #define CLDDX 0x0b, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 631 #define CSTWX 0x09, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 632 #define CSTDX 0x0b, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 633 #define CLDWS 0x09, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 634 #define CLDDS 0x0b, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 635 #define CSTWS 0x09, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 636 #define CSTDS 0x0b, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 637 #define FLOAT0 0x0e, 0x00, 21, 2 /* FLOATING POINT CLASS 0 */ 638 #define FLOAT1 0x0e, 0x01, 21, 2 /* FLOATING POINT CLASS 1 */ 639 #define FLOAT2 0x0e, 0x02, 21, 2 /* FLOATING POINT CLASS 2 */ 640 #define FLOAT3 0x0e, 0x03, 21, 2 /* FLOATING POINT CLASS 3 */ 641 #define FMPYSUB 0x26, 0x00, 0, 0 /* FP MULTIPLY AND SUBTRACT */ 642 #define FMPYADD 0x06, 0x00, 0, 0 /* FP MULTIPLY AND ADD/TRUNCATE */ 643 #define FSTQX 0x0f, 0x01, 19, 4 /* FLOATING POINT STORE QUAD INDEXED */ 644 #define FSTQS 0x0f, 0x09, 19, 4 /* FLOATING POINT STORE QUAD SHORT */ 645 /* all of the following have been pushed around to conform */ 646 #define PROBER 0x01, 0x46, 19, 7 /* PROBE READ ACCESS */ 647 #ifdef notdef 648 #define PROBERI 0x01, 0xc6, 19, 7 /* PROBE READ ACCESS IMMEDIATE */ 649 #endif 650 #define PROBEW 0x01, 0x47, 19, 7 /* PROBE WRITE ACCESS */ 651 #ifdef notdef 652 #define PROBEWI 0x01, 0xc7, 19, 7 /* PROBE WRITE ACCESS IMMEDIATE */ 653 #endif 654 #define LPA 0x01, 0x4d, 19, 7 /* LOAD PHYSICAL ADDRESS */ 655 #define LHA 0x01, 0x4c, 19, 7 /* LOAD HASH ADDRESS */ 656 #define PDTLB 0x01, 0x48, 19, 7 /* PURGE DATA TRANS LOOKASIDE BUFFER */ 657 #define PITLB 0x01, 0x08, 19, 7 /* PURGE INST TRANS LOOKASIDE BUFFER */ 658 #define PDTLBE 0x01, 0x49, 19, 7 /* PURGE DATA TLB ENTRY */ 659 #define PITLBE 0x01, 0x09, 19, 7 /* PURGE INST TLB ENTRY */ 660 #define IDTLBA 0x01, 0x41, 19, 7 /* INSERT DATA TLB ADDRESS */ 661 #define IITLBA 0x01, 0x01, 19, 7 /* INSERT INSTRUCTION TLB ADDRESS */ 662 #define IDTLBP 0x01, 0x40, 19, 7 /* INSERT DATA TLB PROTECTION */ 663 #define IITLBP 0x01, 0x00, 19, 7 /* INSERT INSTRUCTION TLB PROTECTION */ 664 #define PDC 0x01, 0x4e, 19, 7 /* PURGE DATA CACHE */ 665 #define FDC 0x01, 0x4a, 19, 7 /* FLUSH DATA CACHE */ 666 #define FIC 0x01, 0x0a, 19, 7 /* FLUSH INSTRUCTION CACHE */ 667 #define FDCE 0x01, 0x4b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 668 #define FICE 0x01, 0x0b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 669 670 /* 671 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 672 * 673 * Spectrum Simulator Instruction Set Constants and Datatypes 674 * Dan Magenheimer - 4/28/82 675 * Computer Research Center, Hewlett-Packard Labs 676 * 677 * (c) copyright 1982 678 * (p) protected 1982 679 * The Hewlett-Packard Company 680 * Hewlett-Packard Laboratories 681 * Computer Research Center 682 * Palo Alto, California 683 * 684 * *** HP Company Confidential *** 685 * 686 * Log: unasm.c,v 687 * Revision 1.5 1994/07/21 22:32:05 mike 688 * official HP copyright notice 689 * 690 * Revision 1.4 1992/07/08 12:19:52 dalton 691 * Checkin before split to 1.0.4 release (by LBS). 692 * 693 * Revision 1.3 92/06/06 16:16:45 dalton 694 * *** empty log message *** 695 * 696 * Revision 1.2 92/06/06 15:42:28 dalton 697 * Changed include to be a path relative to hp800. 698 * 699 * Revision 1.1 92/06/06 14:05:33 dalton 700 * Initial revision 701 * 702 * Revision 1.2 91/04/14 20:29:49 osfrcs 703 * Initial version. 704 * [91/03/30 09:20:34 brezak] 705 * 706 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 707 * Initial version. 708 * [91/03/30 09:20:34 brezak] 709 * 710 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 711 * Initial version. 712 * 713 ;Revision 1.1 88/07/11 14:05:21 14:05:21 ren (Bob Naas) 714 ;Initial revision 715 ; 716 * Revision 5.1 87/02/27 11:12:23 11:12:23 kent (Kent McMullen) 717 * update all src to 5.1 718 * 719 * Revision 5.0 87/02/18 16:31:52 16:31:52 kent (Kent McMullen) 720 * update all revision numbers to 5.0 for release 721 * 722 * Revision 1.1 86/07/15 08:35:00 08:35:00 kent (Kent McMullen) 723 * Initial revision 724 * 725 * Revision 4.3 85/11/12 09:28:44 09:28:44 viggy (Viggy Mokkarala) 726 * first mpsim version, partially stable 727 * 728 * Revision 4.2 84/07/16 17:20:57 17:20:57 djm () 729 * Define field macros for COPR and SFU insts 730 * 731 * Revision 4.1 83/10/25 17:10:14 djm (Daniel Magenheimer) 732 * First release for ACD v4 733 * 734 * Revision 3.1 83/08/03 14:09:59 djm (Daniel Magenheimer) 735 * Sys calls, args, -S, bug fixes, etc. 736 * 737 * Revision 3.0 83/06/13 10:25:13 djm (Daniel Magenheimer) 738 * First release for distribution 739 * 740 * 741 */ 742 /* 743 * Changes: 744 * 12/01/89 ejf Add Rsd(), Rse(), Rtd(), Rte() for 5 ops. 745 * 11/30/89 ejf Make instruction use counters shared, not per CPU. 746 * 11/28/89 ejf Change majoropcode for quicker extension extract. 747 */ 748 749 750 751 /* 752 * Dependencies: std.h, ssDefs.h, bits.h 753 */ 754 755 756 /* Lookup/Execute structure for instructions */ 757 struct inst { 758 u_char majopc; /* major opcode of instruction, 0..MAXOPC */ 759 u_char opcext; /* opcode extension, 0 if not applic. */ 760 u_char extbs; /* starting bit pos of extension field */ 761 u_char extbl; /* bit length of extension field */ 762 u_int count; /* frequency counter for analysis */ 763 char mnem[8]; /* ascii mnemonic */ 764 /* disassembly function */ 765 int (*dasmfcn)(const struct inst *, OFS, union insn); 766 }; 767 768 769 #define NMAJOPCS 64 770 771 struct majoropcode { 772 const struct inst **subops; /* pointer to table of subops indexed by 773 * opcode extension */ 774 u_int maxsubop; /* largest opcode extension value or 0 */ 775 u_int extshft; /* right shift amount for extension field */ 776 u_int extmask; /* post shift mask for extension field */ 777 }; 778 779 #define OpExt(i,m) ((i >> m->extshft) & m->extmask) /* extract opcode extension */ 780 781 782 /*****************************/ 783 /* Miscellaneous definitions */ 784 /*****************************/ 785 786 /* Load/Store Indexed Opcode Extension Cache Control */ 787 #define NOACTION 0 788 #define STACKREF 1 789 #define SEQPASS 2 790 #define PREFETCH 3 791 792 /******************************/ 793 /* Fields within instructions */ 794 /******************************/ 795 796 /* opcode */ 797 #define Opcode(i) BitfR(i,0,6,_b06) 798 /* opcode true/false bit */ 799 #define OpcTF(i) BitfR(i,4,1,_b41) 800 /* register sources */ 801 #define Rsa(i) BitfR(i,11,5,_b115) 802 #define Rsb(i) BitfR(i,6,5,_b65) 803 #define Rsc(i) BitfR(i,27,5,_b275) 804 #define Rsd(i) BitfR(i,21,5,_b215) 805 #define Rse(i) BitfR(i,16,5,_b165) 806 /* register targets */ 807 #define Rta(i) BitfR(i,11,5,_b115) 808 #define Rtb(i) BitfR(i,6,5,_b65) 809 #define Rtc(i) BitfR(i,27,5,_b275) 810 #define Rtd(i) BitfR(i,21,5,_b215) 811 #define Rte(i) BitfR(i,16,5,_b165) 812 /* 5-bit immediates (Magnitude, Sign) */ 813 #define Imb5(i) BitfR(i,6,5,_b65) 814 #define Ima5M(i) BitfR(i,11,4,_b114) 815 #define Ima5S(i) BitfR(i,15,1,_b151) 816 #define Ima5A(i) BitfR(i,11,5,_b115) 817 #define Imd5(i) BitfR(i,22,5,_b225) 818 #define Imc5M(i) BitfR(i,27,4,_b274) 819 #define Imc5S(i) BitfR(i,31,1,_b311) 820 #define Imc5A(i) BitfR(i,27,5,_b275) 821 /* Other immediates */ 822 #define Im21L(i) BitfR(i,18,2,_b182) 823 #define Im21H(i) BitfR(i,20,11,_b2011) 824 #define Im21M1(i) BitfR(i,16,2,_b162) 825 #define Im21M2(i) BitfR(i,11,5,_b115) 826 #define Im21S(i) BitfR(i,31,1,_b311) 827 #define Im11M(i) BitfR(i,21,10,_b2110) 828 #define Im11S(i) BitfR(i,31,1,_b311) 829 /* displacements/offsets */ 830 #define DispM(i) BitfR(i,18,13,_b1813) 831 #define DispS(i) BitfR(i,31,1,_b311) 832 #define Off5(i) BitfR(i,11,5,_b115) 833 #define Off11H(i) BitfR(i,19,10,_b1910) 834 #define Off11L(i) BitfR(i,29,1,_b291) 835 #define OffS(i) BitfR(i,31,1,_b311) 836 /* miscellaneous */ 837 #define Dss(i) BitfR(i,16,2,_b162) 838 #define Cond(i) BitfR(i,16,3,_b163) 839 #define Cneg(i) BitfR(i,19,1,_b191) 840 #define Cond4(i) BitfR(i,16,4,_b164) /* Cond AND Cneg */ 841 #define Nu(i) BitfR(i,30,1,_b301) 842 #define SrL(i) BitfR(i,16,2,_b162) 843 #define SrH(i) BitfR(i,18,1,_b181) 844 #define ShortDisp(i) BitfR(i,19,1,_b191) 845 #define IndxShft(i) BitfR(i,18,1,_b181) 846 #define ModBefore(i) BitfR(i,18,1,_b181) 847 #define CacheCtrl(i) BitfR(i,20,2,_b202) 848 #define Modify(i) BitfR(i,26,1,_b261) 849 #define ProbeI(i) BitfR(i,18,1,_b181) 850 #define Uid(i) BitfR(i,23,3,_b233) 851 #define Sfu(i) BitfR(i,23,3,_b233) 852 #define CopExt17(i) BitfR(i,6,17,_b617) 853 #define CopExt5(i) BitfR(i,27,5,_b275) 854 #define SpopType(i) BitfR(i,21,2,_b212) 855 #define SpopExt15(i) BitfR(i,6,15,_b615) 856 #define SpopExt10(i) BitfR(i,11,10,_b1110) 857 #define SpopExt5L(i) BitfR(i,16,5,_b165) 858 #define SpopExt5(i) BitfR(i,27,5,_b275) 859 #define NoMajOpc(i) BitfR(i,6,26,_b626) 860 #define Bi1(i) BitfR(i,27,5,_b275) /* fields in BREAK */ 861 #define Bi2(i) BitfR(i,6,13,_b613) 862 863 /* fragmented field collating macros */ 864 #define Ima5(i) (Ima5S(i) ? Ima5M(i) | (-1<<4) : Ima5M(i)) 865 866 #define Imc5(i) (Imc5S(i) ? Imc5M(i) | (-1<<4) : Imc5M(i)) 867 868 #define Disp(i) (DispS(i) ? DispM(i) | (-1<<13) : DispM(i)) 869 870 #define Im21(i) (Im21S(i) << 31 | Im21H(i) << 20 | Im21M1(i) << 18 | \ 871 Im21M2(i) << 13 | Im21L(i) << 11) 872 873 #define Im11(i) (Im11S(i) ? Im11M(i) | (-1<<10) : Im11M(i)) 874 875 #define Bdisp(i) ((OffS(i) ? (Off5(i)<<11 | Off11L(i)<<10|Off11H(i)) \ 876 /* branch displacement (bytes) */ | (-1 << 16) \ 877 : (Off5(i)<<11|Off11L(i)<<10|Off11H(i))) << 2) 878 879 #define Cbdisp(i) ((OffS(i) ? (Off11L(i) << 10 | Off11H(i)) \ 880 /* compare/branch disp (bytes) */ | (-1 << 11) \ 881 : Off11L(i) << 10 | Off11H(i)) << 2) 882 883 #define Sr(i) (SrH(i)<<2 | SrL(i)) 884 885 /* sfu/copr */ 886 #define CoprExt1(i) (CopExt17(i)) 887 #define CoprExt2(i) (CopExt5(i)) 888 #define CoprExt(i) ((CopExt17(i)<<5) | CopExt5(i)) 889 #define Spop0Ext(i) ((SpopExt15(i)<<5) | SpopExt5(i)) 890 #define Spop1Ext(i) (SpopExt15(i)) 891 #define Spop2Ext(i) ((SpopExt10(i)<<5) | SpopExt5(i)) 892 #define Spop3Ext(i) ((SpopExt5L(i)<<5) | SpopExt5(i)) 893 894 895 /*##################### Globals - Imports ##################################*/ 896 897 /* Disassembly functions */ 898 int fcoprDasm(union insn, u_int, u_int); 899 const char *edDCond(u_int); 900 const char *unitDCond(u_int); 901 const char *addDCond(u_int); 902 const char *subDCond(u_int); 903 int blDasm(const struct inst *, OFS, union insn); 904 int ldDasm(const struct inst *, OFS, union insn); 905 int stDasm(const struct inst *, OFS, union insn); 906 int addDasm(const struct inst *, OFS, union insn); 907 int unitDasm(const struct inst *, OFS, union insn); 908 int iaDasm(const struct inst *, OFS, union insn); 909 int shdDasm(const struct inst *, OFS, union insn); 910 int extrDasm(const struct inst *, OFS, union insn); 911 int vextrDasm(const struct inst *, OFS, union insn); 912 int depDasm(const struct inst *, OFS, union insn); 913 int vdepDasm(const struct inst *, OFS, union insn); 914 int depiDasm(const struct inst *, OFS, union insn); 915 int vdepiDasm(const struct inst *, OFS, union insn); 916 int limmDasm(const struct inst *, OFS, union insn); 917 int brkDasm(const struct inst *, OFS, union insn); 918 int lpkDasm(const struct inst *, OFS, union insn); 919 int fmpyaddDasm(const struct inst *, OFS, union insn); 920 int fmpysubDasm(const struct inst *, OFS, union insn); 921 int floatDasm(const struct inst *, OFS, union insn); 922 int coprDasm(const struct inst *, OFS, union insn); 923 int diagDasm(const struct inst *, OFS, union insn); 924 int scDasm(const struct inst *, OFS, union insn); 925 int mmgtDasm(const struct inst *, OFS, union insn); 926 int ldxDasm(const struct inst *, OFS, union insn); 927 int stsDasm(const struct inst *, OFS, union insn); 928 int stbysDasm(const struct inst *, OFS, union insn); 929 int brDasm(const struct inst *, OFS, union insn); 930 int bvDasm(const struct inst *, OFS, union insn); 931 int beDasm(const struct inst *, OFS, union insn); 932 int cbDasm(const struct inst *, OFS, union insn); 933 int cbiDasm(const struct inst *, OFS, union insn); 934 int bbDasm(const struct inst *, OFS, union insn); 935 int ariDasm(const struct inst *, OFS, union insn); 936 937 /*##################### Globals - Exports ##################################*/ 938 /*##################### Local Variables ####################################*/ 939 940 static const char fcoprUndef[] = "copr\t(rsvd or undef.)"; 941 static const char fmtStrTbl[][5] = { "sgl", "dbl", "sgl", "quad" }; 942 static const char condStrTbl[][7] = { 943 "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", 944 "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", 945 "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", 946 "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" 947 }; 948 static const char fsreg[][5] = { 949 "r0L", "r0R", "r1L", "r1R", "r2L", "r2R", "r3L", "r3R", 950 "r4L", "r4R", "r5L", "r5R", "r6L", "r6R", "r7L", "r7R", 951 "r8L", "r8R", "r9L", "r9R", "r10L", "r10R", "r11L", "r11R", 952 "r12L", "r12R", "r13L", "r13R", "r14L", "r14R", "r15L", "r15R", 953 "r16L", "r16R", "r17L", "r17R", "r18L", "r18R", "r19L", "r19R", 954 "r20L", "r20R", "r21L", "r21R", "r22L", "r22R", "r23L", "r23R", 955 "r24L", "r24R", "r25L", "r25R", "r26L", "r26R", "r27L", "r27R", 956 "r28L", "r28R", "r29L", "r29R", "r30L", "r30R", "r31L", "r31R" 957 }; 958 static const char fdreg[][4] = { 959 "r0", "r0", "r1", "r1", "r2", "r2", "r3", "r3", 960 "r4", "r4", "r5", "r5", "r6", "r6", "r7", "r7", 961 "r8", "r8", "r9", "r9", "r10", "r10", "r11", "r11", 962 "r12", "r12", "r13", "r13", "r14", "r14", "r15", "r15", 963 "r16", "r16", "r17", "r17", "r18", "r18", "r19", "r19", 964 "r20", "r20", "r21", "r21", "r22", "r22", "r23", "r23", 965 "r24", "r24", "r25", "r25", "r26", "r26", "r27", "r27", 966 "r28", "r28", "r29", "r29", "r30", "r30", "r31", "r31" 967 }; 968 969 /*##################### Macros #############################################*/ 970 971 #define Match(s) (strncmp(s,i->mnem,sizeof(s)-1) == 0) 972 973 /* bits for assist ops */ 974 #define AstNu(w) Modify(w) 975 #define Fpi(w) (Uid(w)>3) 976 977 /* bits for 5 ops */ 978 #define SinglePrec(i) Modify(i) 979 #define Ms1(i) ((Rsb(i)<<1)+(SinglePrec(i)?((Rsb(i)>15)?1:32):0)) 980 #define Ms2(i) ((Rsa(i)<<1)+(SinglePrec(i)?((Rsa(i)>15)?1:32):0)) 981 #define Mt(i) ((Rtc(i)<<1)+(SinglePrec(i)?((Rtc(i)>15)?1:32):0)) 982 #define As(i) ((Rsd(i)<<1)+(SinglePrec(i)?((Rsd(i)>15)?1:32):0)) 983 #define Ad(i) ((Rte(i)<<1)+(SinglePrec(i)?((Rte(i)>15)?1:32):0)) 984 985 /*##################### Globals - Exports ##################################*/ 986 987 /* To replace instr function, do the following: */ 988 /* a) locate the desired entry in instrs[] below */ 989 /* b) change the 3rd field if an alternate mneumonic is */ 990 /* desired for window disassembly */ 991 /* c) change the 4th field to the name of the function being */ 992 /* used for replacement (i.e. ldwRepl instead of ldw) */ 993 /* d) change the 5th field if an alternate disassembly routine */ 994 /* is desired (i.e. ldDasmRepl) */ 995 996 static const struct inst instrs[] = { 997 { LDW, 0, "ldw", ldDasm }, 998 { LDH, 0, "ldh", ldDasm }, 999 { LDB, 0, "ldb", ldDasm }, 1000 { LDWM, 0, "ldwm", ldDasm }, 1001 { LDO, 0, "ldo", ldDasm }, 1002 { STW, 0, "stw", stDasm }, 1003 { STH, 0, "sth", stDasm }, 1004 { STB, 0, "stb", stDasm }, 1005 { STWM, 0, "stwm", stDasm }, 1006 { LDWX, 0, "ldw", ldxDasm }, 1007 { LDHX, 0, "ldh", ldxDasm }, 1008 { LDBX, 0, "ldb", ldxDasm }, 1009 { LDCWX, 0, "ldcw", ldxDasm }, 1010 { LDWAX, 0, "ldwa", ldxDasm }, 1011 { LDWS, 0, "ldw", ldxDasm }, 1012 { LDHS, 0, "ldh", ldxDasm }, 1013 { LDBS, 0, "ldb", ldxDasm }, 1014 { LDCWS, 0, "ldcw", ldxDasm }, 1015 { LDWAS, 0, "ldwa", ldxDasm }, 1016 { STWS, 0, "stws", stsDasm }, 1017 { STHS, 0, "sths", stsDasm }, 1018 { STBS, 0, "stbs", stsDasm }, 1019 { STWAS, 0, "stwas", stsDasm }, 1020 { STBYS, 0, "stbys", stbysDasm }, 1021 { LDIL, 0, "ldil", limmDasm }, 1022 { ADDIL, 0, "addil", limmDasm }, 1023 { GATE, 0, "gate", blDasm }, 1024 { BL, 0, "b", blDasm }, 1025 { BLR, 0, "blr", brDasm }, 1026 { BV, 0, "bv", bvDasm }, 1027 { BE, 0, "be", beDasm }, 1028 { BLE, 0, "ble", beDasm }, 1029 { COMBT, 0, "combt", cbDasm }, 1030 { COMBF, 0, "combf", cbDasm }, 1031 { COMIBT, 0, "comibt", cbiDasm }, 1032 { COMIBF, 0, "comibf", cbiDasm }, 1033 { ADDBT, 0, "addbt", cbDasm }, 1034 { ADDBF, 0, "addbf", cbDasm }, 1035 { ADDIBT, 0, "addibt", cbiDasm }, 1036 { ADDIBF, 0, "addibf", cbiDasm }, 1037 { MOVB, 0, "movb", cbDasm }, 1038 { MOVIB, 0, "movib", cbiDasm }, 1039 { BB, 0, "bb", bbDasm }, 1040 { BVB, 0, "bvb", bbDasm }, 1041 { SUBO, 0, "subo", ariDasm }, 1042 { ADD, 0, "add", addDasm }, 1043 { ADDL, 0, "addl", addDasm }, 1044 { ADDO, 0, "addo", ariDasm }, 1045 { SH1ADD, 0, "sh1add", ariDasm }, 1046 { SH1ADDL,0, "sh1addl", ariDasm }, 1047 { SH1ADDO,0, "sh1addo", ariDasm }, 1048 { SH2ADD, 0, "sh2add", ariDasm }, 1049 { SH2ADDL,0, "sh2addl", ariDasm }, 1050 { SH2ADDO,0, "sh2addo", ariDasm }, 1051 { SH3ADD, 0, "sh3add", ariDasm }, 1052 { SH3ADDL,0, "sh3addl", ariDasm }, 1053 { SH3ADDO,0, "sh3addo", ariDasm }, 1054 { SUB, 0, "sub", ariDasm }, 1055 { ADDCO, 0, "addco", ariDasm }, 1056 { SUBBO, 0, "subbo", ariDasm }, 1057 { ADDC, 0, "addc", ariDasm }, 1058 { SUBB, 0, "subb", ariDasm }, 1059 { COMCLR, 0, "comclr", ariDasm }, 1060 { OR, 0, "or", ariDasm }, 1061 { AND, 0, "and", ariDasm }, 1062 { XOR, 0, "xor", ariDasm }, 1063 { ANDCM, 0, "andcm", ariDasm }, 1064 { DS, 0, "ds", ariDasm }, 1065 { UXOR, 0, "uxor", unitDasm }, 1066 { UADDCM, 0, "uaddcm", unitDasm }, 1067 { UADDCMT,0, "uaddcmt", unitDasm }, 1068 { SUBTO, 0, "subto", ariDasm }, 1069 { SUBT, 0, "subt", ariDasm }, 1070 { DCOR, 0, "dcor", unitDasm }, 1071 { IDCOR, 0, "idcor", unitDasm }, 1072 { ADDIO, 0, "addio", iaDasm }, 1073 { SUBIO, 0, "subio", iaDasm }, 1074 { ADDI, 0, "addi", iaDasm }, 1075 { SUBI, 0, "subi", iaDasm }, 1076 { COMICLR,0, "comiclr", iaDasm }, 1077 { ADDITO, 0, "addito", iaDasm }, 1078 { ADDIT, 0, "addit", iaDasm }, 1079 { SHD, 0, "shd", shdDasm }, 1080 { VSHD, 0, "vshd", shdDasm }, 1081 { EXTRU, 0, "extru", extrDasm }, 1082 { EXTRS, 0, "extrs", extrDasm }, 1083 { VEXTRU, 0, "vextru", vextrDasm }, 1084 { VEXTRS, 0, "vextrs", vextrDasm }, 1085 { DEP, 0, "dep", depDasm }, 1086 { VDEP, 0, "vdep", vdepDasm }, 1087 { DEPI, 0, "depi", depiDasm }, 1088 { VDEPI, 0, "vdepi", vdepiDasm }, 1089 { ZDEP, 0, "zdep", depDasm }, 1090 { ZVDEP, 0, "zvdep", vdepDasm }, 1091 { ZDEPI, 0, "zdepi", depiDasm }, 1092 { ZVDEPI, 0, "zvdepi", vdepiDasm }, 1093 { BREAK, 0, "break", brkDasm }, 1094 { RFI, 0, "rfi", 0 }, 1095 { RFIR, 0, "rfir", 0 }, 1096 { SSM, 0, "ssm", scDasm }, 1097 { RSM, 0, "rsm", scDasm }, 1098 { MTSM, 0, "mtsm", scDasm }, 1099 { PROBER, 0, "prober", mmgtDasm }, 1100 { PROBEW, 0, "probew", mmgtDasm }, 1101 { LPA, 0, "lpa", mmgtDasm }, 1102 { LHA, 0, "lha", mmgtDasm }, 1103 { LDSID, 0, "ldsid", scDasm }, 1104 { PDTLB, 0, "pdtlb", mmgtDasm }, 1105 { PDTLBE, 0, "pdtlbe", mmgtDasm }, 1106 { PITLB, 0, "pitlb", mmgtDasm }, 1107 { PITLBE, 0, "pitlbe", mmgtDasm }, 1108 { IDTLBA, 0, "idtlba", mmgtDasm }, 1109 { IITLBA, 0, "iitlba", mmgtDasm }, 1110 { IDTLBP, 0, "idtlbp", mmgtDasm }, 1111 { IITLBP, 0, "iitlbp", mmgtDasm }, 1112 { FIC, 0, "fic", mmgtDasm }, 1113 { FICE, 0, "fice", mmgtDasm }, 1114 { PDC, 0, "pdc", mmgtDasm }, 1115 { FDC, 0, "fdc", mmgtDasm }, 1116 { FDCE, 0, "fdce", mmgtDasm }, 1117 { SYNC, 0, "sync", 0 }, 1118 { MTSP, 0, "mtsp", scDasm }, 1119 { MTCTL, 0, "mtctl", scDasm }, 1120 { MFSP, 0, "mfsp", scDasm }, 1121 { MFCTL, 0, "mfctl", scDasm }, 1122 { DIAG, 0, "diag", diagDasm }, 1123 { SPOP, 0, "???", 0 }, 1124 { COPR, 0, "copr", coprDasm }, 1125 { CLDWX, 0, "cldw", coprDasm }, 1126 { CLDDX, 0, "cldd", coprDasm }, 1127 { CSTWX, 0, "cstw", coprDasm }, 1128 { CSTDX, 0, "cstd", coprDasm }, 1129 { CLDWS, 0, "cldw", coprDasm }, 1130 { CLDDS, 0, "cldd", coprDasm }, 1131 { CSTWS, 0, "cstw", coprDasm }, 1132 { CSTDS, 0, "cstd", coprDasm }, 1133 { FLOAT0, 0, "f", floatDasm }, 1134 { FLOAT1, 0, "fcnv", floatDasm }, 1135 { FLOAT2, 0, "f", floatDasm }, 1136 { FLOAT3, 0, "f", floatDasm }, 1137 { FMPYSUB,0, "fmpy", fmpysubDasm }, 1138 { FMPYADD,0, "fmpy", fmpyaddDasm }, 1139 { FSTQX, 0, "fstqx", lpkDasm }, 1140 { FSTQS, 0, "fstqs", lpkDasm }, 1141 {0} 1142 }; 1143 1144 1145 static const struct inst *so_sysop[0xd0]; 1146 static const struct inst *so_mmuop[0x50]; 1147 static const struct inst *so_arith[0x80]; 1148 static const struct inst *so_loads[0x50]; 1149 static const struct inst *so_cldw [0x0A]; 1150 static const struct inst *so_cldd [0x0A]; 1151 static const struct inst *so_float[0x04]; 1152 static const struct inst *so_fstq [0x0A]; 1153 static const struct inst *so_ebran[0x08]; 1154 static const struct inst *so_addit[0x02]; 1155 static const struct inst *so_addi [0x02]; 1156 static const struct inst *so_subi [0x02]; 1157 static const struct inst *so_shext[0x08]; 1158 static const struct inst *so_deps [0x08]; 1159 1160 #define ILLEG NULL 1161 #define NENTS(a) (sizeof(a)/sizeof(a[0])-1) 1162 static struct majoropcode majopcs[NMAJOPCS] = { 1163 { so_sysop, NENTS(so_sysop) }, /* 00 */ 1164 { so_mmuop, NENTS(so_mmuop) }, /* 01 */ 1165 { so_arith, NENTS(so_arith) }, /* 02 */ 1166 { so_loads, NENTS(so_loads) }, /* 03 */ 1167 { ILLEG, 1 }, /* 04 */ 1168 { ILLEG, 1 }, /* 05 */ 1169 { ILLEG, 1 }, /* 06 */ 1170 { ILLEG, 1 }, /* 07 */ 1171 { ILLEG, 1 }, /* 08 */ 1172 { so_cldw , NENTS(so_cldw ) }, /* 09 */ 1173 { ILLEG, 1 }, /* 0A */ 1174 { so_cldd , NENTS(so_cldd ) }, /* 0B */ 1175 { ILLEG, 1 }, /* 0C */ 1176 { ILLEG, 1 }, /* 0D */ 1177 { so_float, NENTS(so_float) }, /* 0E */ 1178 { so_fstq , NENTS(so_fstq ) }, /* 0F */ 1179 { ILLEG, 1 }, /* 10 */ 1180 { ILLEG, 1 }, /* 11 */ 1181 { ILLEG, 1 }, /* 12 */ 1182 { ILLEG, 1 }, /* 13 */ 1183 { ILLEG, 1 }, /* 14 */ 1184 { ILLEG, 1 }, /* 15 */ 1185 { ILLEG, 1 }, /* 16 */ 1186 { ILLEG, 1 }, /* 17 */ 1187 { ILLEG, 1 }, /* 18 */ 1188 { ILLEG, 1 }, /* 19 */ 1189 { ILLEG, 1 }, /* 1A */ 1190 { ILLEG, 1 }, /* 1B */ 1191 { ILLEG, 1 }, /* 1C */ 1192 { ILLEG, 1 }, /* 1D */ 1193 { ILLEG, 1 }, /* 1E */ 1194 { ILLEG, 1 }, /* 1F */ 1195 { ILLEG, 1 }, /* 20 */ 1196 { ILLEG, 1 }, /* 21 */ 1197 { ILLEG, 1 }, /* 22 */ 1198 { ILLEG, 1 }, /* 23 */ 1199 { ILLEG, 1 }, /* 24 */ 1200 { so_subi , NENTS(so_subi ) }, /* 25 */ 1201 { ILLEG, 1 }, /* 26 */ 1202 { ILLEG, 1 }, /* 27 */ 1203 { ILLEG, 1 }, /* 28 */ 1204 { ILLEG, 1 }, /* 29 */ 1205 { ILLEG, 1 }, /* 2A */ 1206 { ILLEG, 1 }, /* 2B */ 1207 { so_addit, NENTS(so_addit) }, /* 2C */ 1208 { so_addi , NENTS(so_addi ) }, /* 2D */ 1209 { ILLEG, 1 }, /* 2E */ 1210 { ILLEG, 1 }, /* 2F */ 1211 { ILLEG, 1 }, /* 30 */ 1212 { ILLEG, 1 }, /* 31 */ 1213 { ILLEG, 1 }, /* 32 */ 1214 { ILLEG, 1 }, /* 33 */ 1215 { so_shext, NENTS(so_shext) }, /* 34 */ 1216 { so_deps , NENTS(so_deps ) }, /* 35 */ 1217 { ILLEG, 1 }, /* 36 */ 1218 { ILLEG, 1 }, /* 37 */ 1219 { ILLEG, 1 }, /* 38 */ 1220 { ILLEG, 1 }, /* 39 */ 1221 { so_ebran, NENTS(so_ebran) }, /* 3A */ 1222 { ILLEG, 1 }, /* 3B */ 1223 { ILLEG, 1 }, /* 3C */ 1224 { ILLEG, 1 }, /* 3D */ 1225 { ILLEG, 1 }, /* 3E */ 1226 { ILLEG, 1 }, /* 3F */ 1227 }; 1228 #undef NENTS 1229 #undef ILLEG 1230 1231 /*-------------------------------------------------------------------------- 1232 * instruction$ExecutionInitialize - Initialize the instruction execution 1233 * data structures. 1234 *---------------------------------------------------------------------------*/ 1235 static int iExInit(void); 1236 static int 1237 iExInit(void) 1238 { 1239 static int unasm_initted = 0; 1240 const struct inst *i; 1241 struct majoropcode *m; 1242 u_int shft, mask; 1243 1244 if (unasm_initted) 1245 return 0; 1246 1247 /* 1248 * Determine maxsubop for each major opcode. 1249 * Also, check all instructions of a given major opcode 1250 * for consistent opcode extension field definition, and 1251 * save a converted form of this definition in the majopcs 1252 * entry for this major opcode. 1253 */ 1254 for (i = &instrs[0]; *i->mnem; i++) { 1255 m = &majopcs[i->majopc]; 1256 if (m->maxsubop < i->opcext) 1257 panic("iExInit not enough space for opcode %d", 1258 i->majopc); 1259 shft = 32 - i->extbs - i->extbl; 1260 mask = (1 << i->extbl) - 1; 1261 if (m->extshft || m->extmask) { 1262 if (m->extshft != shft || m->extmask != mask) { 1263 db_printf("%s - Bad instruction initialization!\n", i->mnem); 1264 return (0); 1265 } 1266 } else { 1267 m->extshft = shft; 1268 m->extmask = mask; 1269 } 1270 } 1271 1272 /* 1273 * Lastly, fill in all legal subops with the appropriate info. 1274 */ 1275 for (i = &instrs[0]; *i->mnem; i++) { 1276 m = &majopcs[i->majopc]; 1277 if (m->maxsubop == 1) 1278 m->subops = __UNCONST(i); 1279 else 1280 m->subops[i->opcext] = i; 1281 } 1282 1283 unasm_initted++; 1284 return (1); 1285 } 1286 1287 1288 1289 /*##################### Functions and Subroutines ##########################*/ 1290 1291 /**************************************/ 1292 /* Miscellaneous Disassembly Routines */ 1293 /**************************************/ 1294 1295 /* Add instructions */ 1296 int 1297 addDasm(const struct inst *i, OFS ofs, union insn w) 1298 { 1299 db_printf("%s\t%%r%d,%%r%d,%%r%d",addDCond(Cond4(w)), 1300 Rsa(w),Rsb(w),Rtc(w)); 1301 return (1); 1302 } 1303 1304 /* Unit instructions */ 1305 int 1306 unitDasm(const struct inst *i, OFS ofs, union insn w) 1307 { 1308 db_printf(unitDCond(Cond4(w))); 1309 if (Match("dcor") || Match("idcor")) 1310 db_printf("\t%%r%d,%%r%d",Rsb(w),Rtc(w)); 1311 else 1312 db_printf("\t%%r%d,%%r%d,%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1313 return (1); 1314 } 1315 1316 /* Immediate Arithmetic instructions */ 1317 int 1318 iaDasm(const struct inst *i, OFS ofs, union insn w) 1319 { 1320 if (Match("addi")) 1321 db_printf("%s\t%d,%%r%d,%%r%d", 1322 addDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1323 else 1324 db_printf("%s\t%d,%%r%d,%%r%d", 1325 subDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1326 return (1); 1327 } 1328 1329 /* Shift double instructions */ 1330 int 1331 shdDasm(const struct inst *i, OFS ofs, union insn w) 1332 { 1333 if (Match("vshd")) 1334 db_printf("%s\t%%r%d,%%r%d,%%r%d", 1335 edDCond(Cond(w)), Rsa(w),Rsb(w),Rtc(w)); 1336 else 1337 db_printf("%s\t%%r%d,%%r%d,%d,%%r%d", 1338 edDCond(Cond(w)),Rsa(w),Rsb(w),31-Imd5(w),Rtc(w)); 1339 return (1); 1340 } 1341 1342 /* Extract instructions */ 1343 int 1344 extrDasm(const struct inst *i, OFS ofs, union insn w) 1345 { 1346 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1347 edDCond(Cond(w)),Rsb(w),Imd5(w),32 - Rsc(w),Rta(w)); 1348 return (1); 1349 } 1350 1351 1352 /* Variable extract instructions */ 1353 int 1354 vextrDasm(const struct inst *i, OFS ofs, union insn w) 1355 { 1356 db_printf("%s\t%%r%d,%d,%%r%d", 1357 edDCond(Cond(w)),Rsb(w),32 - Rsc(w),Rta(w)); 1358 return (1); 1359 } 1360 1361 1362 /* Deposit instructions */ 1363 int 1364 depDasm(const struct inst *i, OFS ofs, union insn w) 1365 { 1366 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1367 edDCond(Cond(w)),Rsa(w),31 - Imd5(w),32 - Rsc(w),Rtb(w)); 1368 return (1); 1369 } 1370 1371 1372 /* Variable deposit instructions */ 1373 int 1374 vdepDasm(const struct inst *i, OFS ofs, union insn w) 1375 { 1376 db_printf("%s\t%%r%d,%d,%%r%d", 1377 edDCond(Cond(w)),Rsa(w),32 - Rsc(w),Rtb(w)); 1378 return (1); 1379 } 1380 1381 1382 /* Deposit Immediate instructions */ 1383 int 1384 depiDasm(const struct inst *i, OFS ofs, union insn w) 1385 { 1386 db_printf("%s\t%d,%d,%d,%%r%d", 1387 edDCond(Cond(w)),Ima5(w),31 - Imd5(w),32 - Imc5A(w),Rtb(w)); 1388 return (1); 1389 } 1390 1391 /* Variable Deposit Immediate instructions */ 1392 int 1393 vdepiDasm(const struct inst *i, OFS ofs, union insn w) 1394 { 1395 db_printf("%s\t%d,%d,%%r%d",edDCond(Cond(w)),Ima5(w),32-Imc5A(w),Rtb(w)); 1396 return (1); 1397 } 1398 1399 /*--------------------------------------------------------------------------- 1400 * conditionType$DisassembleCondition - Return a string which contains the 1401 * ascii description of the passed numeric condition. 1402 *---------------------------------------------------------------------------*/ 1403 1404 const char * 1405 subDCond(u_int cond) 1406 { 1407 switch(cond) { 1408 case EQZ: return(",="); 1409 case LT: return(",<"); 1410 case LE: return(",<="); 1411 case LLT: return(",<<"); 1412 case LLE: return(",<<="); 1413 case SV: return(",sv"); 1414 case OD: return(",od"); 1415 case NEQZ: return(",<>"); 1416 case GE: return(",>="); 1417 case GT: return(",>"); 1418 case LGE: return(",>>="); 1419 case LGT: return(",>>"); 1420 case NSV: return(",nsv"); 1421 case EV: return(",ev"); 1422 case TR: return(",tr"); 1423 case NEV: return(""); 1424 default: 1425 panic("subDCond: unknown condition"); 1426 } 1427 } 1428 1429 1430 /*--------------------------------------------------------------------------- 1431 * conditionType$DisassembleCondition - Return a string which contains the 1432 * ascii description of the passed numeric condition. 1433 *---------------------------------------------------------------------------*/ 1434 1435 const char * 1436 addDCond(u_int cond) 1437 { 1438 switch(cond) { 1439 case EQZ: return(",="); 1440 case LT: return(",<"); 1441 case LE: return(",<="); 1442 case NUV: return(",nuv"); 1443 case ZNV: return(",znv"); 1444 case SV: return(",sv"); 1445 case OD: return(",od"); 1446 case NEQZ: return(",<>"); 1447 case GE: return(",>="); 1448 case GT: return(",>"); 1449 case UV: return(",uv"); 1450 case VNZ: return(",vnz"); 1451 case NSV: return(",nsv"); 1452 case EV: return(",ev"); 1453 case TR: return(",tr"); 1454 case NEV: return(""); 1455 default: 1456 panic("addDCond: unknown condition"); 1457 } 1458 } 1459 1460 const char * 1461 unitDCond(u_int cond) 1462 { 1463 switch(cond) { 1464 case SHC: return(",shc"); 1465 case SHZ: return(",shz"); 1466 case SBC: return(",sbc"); 1467 case SBZ: return(",sbz"); 1468 case SDC: return(",sdc"); 1469 case NHC: return(",nhc"); 1470 case NHZ: return(",nhz"); 1471 case NBC: return(",nbc"); 1472 case NBZ: return(",nbz"); 1473 case NDC: return(",ndc"); 1474 case TR: return(",tr"); 1475 case NEV: return(""); 1476 default: 1477 panic("unitDCond: unknown condition"); 1478 } 1479 } 1480 1481 const char * 1482 edDCond(u_int cond) 1483 { 1484 switch(cond) { 1485 case XOD: return(",od"); 1486 case XTR: return(",tr"); 1487 case XNE: return(",<>"); 1488 case XLT: return(",<"); 1489 case XEQ: return(",="); 1490 case XGE: return(",>="); 1491 case XEV: return(",ev"); 1492 case NEV: return(""); 1493 default: 1494 panic("edDCond: unknown condition"); 1495 } 1496 } 1497 1498 1499 1500 /****************************************/ 1501 /* Format Specific Disassembly Routines */ 1502 /****************************************/ 1503 1504 1505 /* Load [modify] instructions */ 1506 int 1507 ldDasm(const struct inst *i, OFS ofs, union insn w) 1508 { 1509 int d = Disp(w); 1510 char s[2]; 1511 1512 s[1] = '\0'; 1513 if (d < 0) { 1514 d = -d; 1515 s[0] = '-'; 1516 } else 1517 s[0] = '\0'; 1518 1519 if (Rsb(w) == 0 && Match("ldo")) { 1520 db_printf("ldi\t%s%X,%%r%d",s,d,Rta(w)); 1521 return (1); 1522 } 1523 db_printf("%s\t%s%s%X",i->mnem,(d < 2048? "R'":""), s, d); 1524 if (Dss(w)) 1525 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rta(w)); 1526 else 1527 db_printf("(%%r%d),%%r%d",Rsb(w),Rta(w)); 1528 return (1); 1529 } 1530 1531 /* Store [modify] instructions */ 1532 int 1533 stDasm(const struct inst *i, OFS ofs, union insn w) 1534 { 1535 int d = Disp(w); 1536 char s[2]; 1537 1538 db_printf("\t%%r%d,",Rta(w)); 1539 1540 s[1] = '\0'; 1541 if (d < 0) { 1542 d = -d; 1543 s[0] = '-'; 1544 } else 1545 s[0] = '\0'; 1546 1547 db_printf("%s%s%X", (d < 2048? "R'":""), s, d); 1548 1549 if (Dss(w)) 1550 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 1551 else 1552 db_printf("(%%r%d)",Rsb(w)); 1553 return (1); 1554 } 1555 1556 /* Load indexed instructions */ 1557 int 1558 ldxDasm(const struct inst *i, OFS ofs, union insn w) 1559 { 1560 const char *p; 1561 1562 if (ShortDisp(w)) { 1563 db_printf("s"); 1564 if (Modify(w)) 1565 db_printf(",m%s", ModBefore(w)? "b": "a"); 1566 } else { 1567 db_printf("x"); 1568 if (Modify(w)) 1569 db_printf(",%sm", IndxShft(w)? "s":""); 1570 } 1571 switch (CacheCtrl(w)) { 1572 default: 1573 case NOACTION: p = ""; break; 1574 case STACKREF: p = ",c"; break; 1575 case SEQPASS: p = ",q"; break; 1576 case PREFETCH: p = ",p"; break; 1577 } 1578 if (ShortDisp(w)) 1579 db_printf("%s\t%d", p, Ima5(w)); 1580 else 1581 db_printf("%s\t%%r%d", p, Rsa(w)); 1582 1583 if (Dss(w)) 1584 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1585 else 1586 db_printf("(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1587 return (1); 1588 } 1589 1590 /* Store short displacement instructions */ 1591 int 1592 stsDasm(const struct inst *i, OFS ofs, union insn w) 1593 { 1594 const char *p; 1595 1596 if (Modify(w)) 1597 db_printf(",m%s", ModBefore(w)? "b":"a"); 1598 1599 switch (CacheCtrl(w)) { 1600 default: 1601 case NOACTION: p = ""; break; 1602 case STACKREF: p = ",c"; break; 1603 case SEQPASS: p = ",q"; break; 1604 case PREFETCH: p = ",p"; break; 1605 } 1606 db_printf("%s\t%%r%d,", p, Rta(w)); 1607 if (Dss(w)) 1608 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1609 else 1610 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1611 return (1); 1612 } 1613 1614 /* Store Bytes Instruction */ 1615 int 1616 stbysDasm(const struct inst *i, OFS ofs, union insn w) 1617 { 1618 const char *p; 1619 1620 db_printf(ModBefore(w)? ",e":",b"); 1621 if (Modify(w)) 1622 db_printf(",m"); 1623 switch (CacheCtrl(w)) { 1624 default: 1625 case NOACTION: p = ""; break; 1626 case STACKREF: p = ",f"; break; 1627 case SEQPASS: p = ",r"; break; 1628 case PREFETCH: p = ",z"; break; 1629 } 1630 db_printf("%s\t%%r%d,", p, Rta(w)); 1631 if (Dss(w)) 1632 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1633 else 1634 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1635 return (1); 1636 } 1637 1638 /* Long Immediate instructions */ 1639 int 1640 limmDasm(const struct inst *i, OFS ofs, union insn w) 1641 { 1642 db_printf("\tL'%X,%%r%d", Im21(w), Rtb(w)); 1643 return (1); 1644 } 1645 1646 1647 /* Branch and Link instruction(s) (Branch, too!!) */ 1648 int 1649 blDasm(const struct inst *i, OFS ofs, union insn w) 1650 { 1651 OFS tgtofs = ofs + 8 + Bdisp(w); 1652 u_int link = Rtb(w); 1653 1654 if (link && !Match("gate")) 1655 db_printf("l"); 1656 if (Nu(w)) 1657 db_printf(",n"); 1658 db_printf("\t"); 1659 1660 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1661 1662 if (link || Match("gate")) 1663 db_printf(",%%r%d",link); 1664 1665 return (1); 1666 } 1667 1668 /* Branch Register instruction */ 1669 int 1670 brDasm(const struct inst *i, OFS ofs, union insn w) 1671 { 1672 db_printf("%s\t%%r%d,%%r%d", Nu(w)?",n":"", Rsa(w), Rtb(w)); 1673 return (1); 1674 } 1675 1676 /* Dispatch instructions */ 1677 int 1678 bvDasm(const struct inst *i, OFS ofs, union insn w) 1679 { 1680 db_printf("%s\t%%r%d(%%r%d)", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1681 return (1); 1682 } 1683 1684 /* Branch External instructions */ 1685 int 1686 beDasm(const struct inst *i, OFS ofs, union insn w) 1687 { 1688 int d = Bdisp(w); 1689 const char *p; 1690 char s[2]; 1691 1692 s[1] = '\0'; 1693 if (d < 0) { 1694 d = -d; 1695 s[0] = '-'; 1696 } else 1697 s[0] = '\0'; 1698 1699 p = Nu(w)? ",n":""; 1700 db_printf("%s\tR'%s%X(%%sr%d,%%r%d)", p, 1701 s, d, Sr(w), Rsb(w)); 1702 return (1); 1703 } 1704 1705 1706 /* Compare/Add and Branch instructions */ 1707 int 1708 cbDasm(const struct inst *i, OFS ofs, union insn w) 1709 { 1710 OFS tgtofs = ofs + 8 + Cbdisp(w); 1711 1712 if (Match("movb")) 1713 db_printf(edDCond(Cond(w))); 1714 else if (Match("addb")) 1715 db_printf(addDCond(Cond(w) << 1)); 1716 else 1717 db_printf(subDCond(Cond(w) << 1)); 1718 db_printf("%s\t%%r%d,%%r%d,", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1719 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1720 return (1); 1721 } 1722 1723 /* Compare/Add and Branch Immediate instructions */ 1724 int 1725 cbiDasm(const struct inst *i, OFS ofs, union insn w) 1726 { 1727 OFS tgtofs = ofs + 8 + Cbdisp(w); 1728 1729 if (Match("movib")) 1730 db_printf(edDCond(Cond(w))); 1731 else if (Match("addib")) 1732 db_printf(addDCond(Cond(w) << 1)); 1733 else 1734 db_printf(subDCond(Cond(w) << 1)); 1735 db_printf("%s\t%d,%%r%d,", Nu(w)? ",n":"", Ima5(w), Rsb(w)); 1736 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1737 return (1); 1738 } 1739 1740 /* Branch on Bit instructions */ 1741 int 1742 bbDasm(const struct inst *i, OFS ofs, union insn w) 1743 { 1744 OFS tgtofs = ofs + 8 + Cbdisp(w); 1745 const char *p; 1746 1747 db_printf(edDCond(Cond(w))); 1748 p = Nu(w)? ",n":""; 1749 if (Match("bvb")) 1750 db_printf("%s\t%%r%d,", p, Rta(w)); 1751 else 1752 db_printf("%s\t%%r%d,%d,", p, Rsa(w), Imb5(w)); 1753 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1754 return (1); 1755 } 1756 1757 /* Arithmetic instructions */ 1758 int 1759 ariDasm(const struct inst *i, OFS ofs, union insn w) 1760 { 1761 if (Match("or") && Rsb(w) == 0 && Cond4(w) == NEV) { 1762 if (Rsa(w) == 0 && Rtc(w) == 0) 1763 db_printf("nop"); 1764 else 1765 db_printf("copy\t%%r%d,%%r%d",Rsa(w),Rtc(w)); 1766 } else 1767 db_printf("%s%s\t%%r%d,%%r%d,%%r%d", i->mnem, 1768 subDCond(Cond4(w)), Rsa(w),Rsb(w),Rtc(w)); 1769 return(1); 1770 } 1771 1772 /* System control operations */ 1773 int 1774 scDasm(const struct inst *i, OFS ofs, union insn w) 1775 { 1776 if (Match("mtctl")) { 1777 if (Rtb(w) == 11) 1778 db_printf("mtsar\t%%r%d",Rsa(w)); 1779 else 1780 db_printf("mtctl\t%%r%d,%%cr%d",Rsa(w),Rtb(w)); 1781 return (1); 1782 } 1783 db_printf(i->mnem); 1784 if (Match("ssm") || Match("rsm")) 1785 db_printf("\t%d,%%r%d",Ima5A(w),Rtc(w)); 1786 else if (Match("mtsm")) db_printf("\t%%r%d",Rsa(w)); 1787 else if (Match("ldprid")) db_printf("\t%%r%d",Rtc(w)); 1788 else if (Match("mtsp")) db_printf("\t%%r%d,%%sr%d",Rsa(w),Sr(w)); 1789 else if (Match("mfsp")) db_printf("\t%%sr%d,%%r%d",Sr(w),Rtc(w)); 1790 else if (Match("mfctl")) db_printf("\t%%cr%d,%%r%d",Rsb(w),Rtc(w)); 1791 else if (Match("ldsid")) { 1792 if (Dss(w)) 1793 db_printf("\t(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1794 else 1795 db_printf("\t(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1796 } else { 1797 db_printf("?????"); 1798 return (0); 1799 } 1800 return (1); 1801 } 1802 1803 /* Instruction cache/tlb control instructions */ 1804 int 1805 mmgtDasm(const struct inst *i, OFS ofs, union insn w) 1806 { 1807 if (Match("probe")) { 1808 if (ProbeI(w)) { 1809 if (Dss(w)) 1810 db_printf("i\t(%%sr%d,%%r%d),%d,%%r%d", 1811 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1812 else 1813 db_printf("i\t(%%r%d),%d,%%r%d", 1814 Rsb(w),Rsa(w),Rtc(w)); 1815 } else { 1816 if (Dss(w)) 1817 db_printf("\t(%%sr%d,%%r%d),%%r%d,%%r%d", 1818 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1819 else 1820 db_printf("\t(%%r%d),%%r%d,%%r%d", 1821 Rsb(w),Rsa(w),Rtc(w)); 1822 } 1823 } 1824 else if (Match("lha") || Match("lpa")) { 1825 if (Modify(w)) 1826 db_printf(",m"); 1827 if (Dss(w)) 1828 db_printf("\t%%r%d(%%sr%d,%%r%d),%%r%d", 1829 Rsa(w),Dss(w),Rsb(w),Rtc(w)); 1830 else 1831 db_printf("\t%%r%d(%%r%d),%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1832 } 1833 else if (Match("pdtlb") || Match("pdc") || Match("fdc")) { 1834 if (Modify(w)) db_printf(",m"); 1835 if (Dss(w)) 1836 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1837 else 1838 db_printf("\t%%r%d(%%r%d)",Rsa(w),Rsb(w)); 1839 } 1840 else if (Match("pitlb") || Match("fic")) { 1841 if (Modify(w)) 1842 db_printf(",m"); 1843 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1844 } 1845 else if (Match("idtlb")) { 1846 if (Dss(w)) 1847 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1848 else 1849 db_printf("\t%%r%d,(%%r%d)",Rsa(w),Rsb(w)); 1850 } 1851 else if (Match("iitlb")) 1852 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1853 else { 1854 db_printf("?????"); 1855 return (0); 1856 } 1857 return(1); 1858 } 1859 1860 /* break instruction */ 1861 int 1862 brkDasm(const struct inst *i, OFS ofs, union insn w) 1863 { 1864 db_printf("\t%d,%d",Bi1(w),Bi2(w)); 1865 return (1); 1866 } 1867 1868 int 1869 floatDasm(const struct inst *i, OFS ofs, union insn w) 1870 { 1871 u_int op1, r1, fmt, t; 1872 u_int op2, r2, dfmt; 1873 const char *p; 1874 1875 op1 = CoprExt1(w); 1876 op2 = CoprExt2(w); 1877 fmt = (op1 >> 2) & 3; /* get precision of source */ 1878 1879 #define ST(r) ((fmt & 1)? fdreg[(r)]:fsreg[(r)]) 1880 /* 1881 * get first (or only) source register 1882 * (independent of class) 1883 */ 1884 r1 = (op1 >> 11) & 0x3e; 1885 if ((fmt & 1) == 0 && (Uid(w) & 2)) 1886 r1++; 1887 1888 if (op1 & 2) { /* class 2 or 3 */ 1889 /* 1890 * get second source register 1891 */ 1892 r2 = (op1 >> 6) & 0x3e; 1893 if (fmt == 2) 1894 r2++; 1895 1896 if ((op1 & 1) == 0) { /* class 2 */ 1897 /* Opclass 2: 2 sources, no destination */ 1898 switch((op1 >> 4) & 7) { 1899 case 0: 1900 p = "cmp"; 1901 break; 1902 default: 1903 db_printf(fcoprUndef); 1904 return(0); 1905 } 1906 db_printf("%s,%s",p,fmtStrTbl[fmt]); 1907 db_printf(",%s\t%%f%s,%%f%s", 1908 condStrTbl[op2], ST(r1), ST(r2)); 1909 return (1); 1910 } 1911 /* 1912 * get target register (class 3) 1913 */ 1914 t = (op2 << 1); 1915 if ((fmt & 1) == 0 && (Uid(w) & 1)) 1916 t++; 1917 /* Opclass 3: 2 sources, 1 destination */ 1918 switch((op1 >> 4) & 7) { 1919 case 0: p = "add"; break; 1920 case 1: p = "sub"; break; 1921 case 2: p = (Fpi(w)) ? "mpyi" : "mpy"; break; 1922 case 3: p = "div"; break; 1923 case 4: p = "rem"; break; 1924 default: db_printf(fcoprUndef); return (0); 1925 } 1926 db_printf("%s,%s", p, fmtStrTbl[fmt]); 1927 db_printf("\t%%f%s,%%f%s,%%f%s",ST(r1),ST(r2),ST(t)); 1928 } else if (op1 & 1) { /* class 1 */ 1929 dfmt = (op1 >> 4) & 3; 1930 #define DT(r) ((dfmt & 1)? fdreg[(r)]:fsreg[(r)]) 1931 1932 /* 1933 * get target register 1934 */ 1935 t = (op2 << 1); 1936 if ((dfmt & 1) == 0 && (Uid(w) & 1)) 1937 t++; 1938 /* Opclass 1: 1 source, 1 destination conversions */ 1939 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 1940 #if 0 1941 switch((op1 >> 6) & 3) { 1942 default: 1943 case 0: p = "ff"; break; 1944 case 1: p = "xf"; break; 1945 case 2: p = "fx"; break; 1946 case 3: p = "fxt"; break; 1947 } 1948 #endif 1949 db_printf("%s,%s", p, fmtStrTbl[fmt]); 1950 db_printf(",%s\t%%f%s,%%f%s",fmtStrTbl[dfmt],ST(r1),DT(t)); 1951 } else { /* class 0 */ 1952 /* 1953 * get target register 1954 */ 1955 t = (op2 << 1); 1956 if ((fmt & 1) == 0 && (Uid(w) & 1)) 1957 t++; 1958 /* Opclass 0: 1 source, 1 destination */ 1959 switch((op1 >> 4) & 7) { 1960 case 1: p = "rsqrt"; break; 1961 case 2: p = "cpy"; break; 1962 case 3: p = "abs"; break; 1963 case 4: p = "sqrt"; break; 1964 case 5: p = "rnd"; break; 1965 default: db_printf(fcoprUndef); return (0); 1966 } 1967 db_printf("%s,%s",p,fmtStrTbl[fmt]); 1968 db_printf("\t%%f%s,%%f%s",ST(r1),ST(t)); 1969 } 1970 return (1); 1971 } 1972 1973 int 1974 fcoprDasm(union insn w, u_int op1, u_int op2) 1975 { 1976 u_int r1, r2, t, fmt, dfmt; 1977 const char *p; 1978 1979 if (AstNu(w) && op1 == ((1<<4) | 2)) { 1980 if (op2 == 0 || op2 == 1 || op2 == 2) { 1981 db_printf("ftest"); 1982 if (op2 == 1) 1983 db_printf(",acc"); 1984 else if (op2 == 2) 1985 db_printf(",rej"); 1986 return (1); 1987 } 1988 return (0); 1989 } else if (0 == op1 && 0 == op2) { 1990 db_printf("fcopr identify"); 1991 return (1); 1992 } 1993 switch(op1 & 3) { 1994 case 0: 1995 /* Opclass 0: 1 source, 1 destination */ 1996 r1 = (op1 >> 12) & 0x1f; t = op2; fmt = (op1 >> 2) & 3; 1997 switch((op1 >> 4) & 7) { 1998 case 1: p = "rsqrt"; break; 1999 case 2: p = "cpy"; break; 2000 case 3: p = "abs"; break; 2001 case 4: p = "sqrt"; break; 2002 case 5: p = "rnd"; break; 2003 default: db_printf(fcoprUndef); return(0); 2004 } 2005 db_printf("f%s,%s\t%%fr%d,%%fr%d", p, fmtStrTbl[fmt], r1, t); 2006 break; 2007 case 1: 2008 /* Opclass 1: 1 source, 1 destination conversions */ 2009 r1 = (op1 >> 12) & 0x1f; t = op2; 2010 fmt = (op1 >> 2) & 3; dfmt = (op1 >> 4) & 3; 2011 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 2012 #if 0 2013 switch((op1 >> 6) & 3) { 2014 case 0: p = "ff"; break; 2015 case 1: p = "xf"; break; 2016 case 2: p = "fx"; break; 2017 case 3: p = "fxt"; break; 2018 } 2019 #endif 2020 db_printf("fcnv%s,%s,%s\t%%fr%d,%%fr%d", 2021 p, fmtStrTbl[fmt], fmtStrTbl[dfmt], r1, t); 2022 break; 2023 case 2: 2024 /* Opclass 2: 2 sources, no destination */ 2025 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; 2026 fmt = (op1 >> 2) & 3; 2027 switch((op1 >> 4) & 7) { 2028 case 0: p = "fcmp"; break; 2029 default: db_printf(fcoprUndef); return (0); 2030 } 2031 db_printf("%s,%s,%s\t%%fr%d,%%fr%d", 2032 p,fmtStrTbl[fmt],condStrTbl[op2],r1,r2); 2033 break; 2034 case 3: 2035 /* Opclass 3: 2 sources, 1 destination */ 2036 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; t = op2; 2037 fmt = (op1 >> 2) & 3; 2038 switch((op1 >> 4) & 7) { 2039 case 0: p = "add"; break; 2040 case 1: p = "sub"; break; 2041 case 2: p = "mpy"; break; 2042 case 3: p = "div"; break; 2043 case 4: p = "rem"; break; 2044 default: db_printf(fcoprUndef); return (0); 2045 } 2046 db_printf("f%s,%s\t%%fr%d,%%fr%d,%%fr%d", 2047 p, fmtStrTbl[fmt], r1, r2, t); 2048 break; 2049 default: 2050 db_printf(fcoprUndef); 2051 return(0); 2052 } 2053 return (1); 2054 } 2055 2056 int 2057 coprDasm(const struct inst *i, OFS ofs, union insn w) 2058 { 2059 u_int uid = Uid(w); 2060 int load = 0; 2061 const char *pfx = uid > 1 ? "c" : "f"; 2062 int dreg = 0; 2063 2064 if (Match("copr")) { 2065 if (uid) { 2066 db_printf("copr,%d,0x%x",uid,CoprExt(w)); 2067 if (AstNu(w)) 2068 db_printf(",n"); 2069 return (1); 2070 } 2071 return fcoprDasm(w, CoprExt1(w),CoprExt2(w)); 2072 } 2073 if (Match("cldd")) { 2074 dreg = 1; 2075 load = 1; 2076 db_printf("%sldd",pfx); 2077 } else if (Match("cldw")) { 2078 load = 1; 2079 db_printf("%sldw",pfx); 2080 } else if (Match("cstd")) { 2081 dreg = 1; 2082 db_printf("%sstd",pfx); 2083 } else if (Match("cstw")) 2084 db_printf("%sstw",pfx); 2085 else { 2086 db_printf("copr???"); 2087 return (0); 2088 } 2089 if (ShortDisp(w)) { 2090 db_printf("s"); 2091 if (AstNu(w)) 2092 db_printf(",m%s", ModBefore(w)?"b":"a"); 2093 } 2094 else { 2095 db_printf("x"); 2096 if (AstNu(w)) 2097 db_printf(",%sm", IndxShft(w)?"s":""); 2098 else if (IndxShft(w)) 2099 db_printf(",s"); 2100 } 2101 switch (CacheCtrl(w)) { 2102 case NOACTION: break; 2103 case STACKREF: db_printf(",c"); break; 2104 case SEQPASS: db_printf(",q"); break; 2105 case PREFETCH: db_printf(",p"); break; 2106 } 2107 if (load) { 2108 const char *p; 2109 2110 if (dreg) 2111 p = fdreg[(Rtc(w)<<1)+(uid&1)]; 2112 else 2113 p = fsreg[(Rtc(w)<<1)+(uid&1)]; 2114 2115 if (ShortDisp(w)) 2116 db_printf("\t%d",Ima5(w)); 2117 else 2118 db_printf("\t%%r%d",Rsa(w)); 2119 if (Dss(w)) 2120 db_printf("(%%sr%d,%%r%d),%%f%s", Dss(w),Rsb(w), p); 2121 else 2122 db_printf("(%%r%d),%%f%s",Rsb(w), p); 2123 } else { 2124 const char *p; 2125 2126 if (dreg) 2127 p = fdreg[(Rsc(w)<<1)+(uid&1)]; 2128 else 2129 p = fsreg[(Rsc(w)<<1)+(uid&1)]; 2130 2131 if (ShortDisp(w)) 2132 db_printf("\t%%f%s,%d", p, Ima5(w)); 2133 else 2134 db_printf("\t%%f%s,%%r%d", p, Rta(w)); 2135 if (Dss(w)) 2136 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2137 else 2138 db_printf("(%%r%d)",Rsb(w)); 2139 } 2140 return (1); 2141 } 2142 2143 int 2144 lpkDasm(const struct inst *i, OFS ofs, union insn w) 2145 { 2146 /* 2147 * Floating point STore Quad 2148 * Short or Indexed 2149 */ 2150 if (ShortDisp(w)) { 2151 if (Modify(w)) 2152 db_printf(",m%s", ModBefore(w)?"b":"a"); 2153 } else { 2154 if (Modify(w)) 2155 db_printf(",%sm", IndxShft(w)? "s":""); 2156 else if (IndxShft(w)) 2157 db_printf(",s"); 2158 } 2159 switch (CacheCtrl(w)) { 2160 case NOACTION: break; 2161 case STACKREF: db_printf(",c"); break; 2162 case SEQPASS: db_printf(",q"); break; 2163 case PREFETCH: db_printf(",p"); break; 2164 } 2165 if (ShortDisp(w)) 2166 db_printf("\t%%fr%d,%d",Rsc(w),Ima5(w)); 2167 else 2168 db_printf("\t%%fr%d,%%r%d",Rsc(w),Rta(w)); 2169 if (Dss(w)) 2170 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2171 else 2172 db_printf("(%%r%d)",Rsb(w)); 2173 return (1); 2174 } 2175 2176 int 2177 diagDasm(const struct inst *i, OFS ofs, union insn w) 2178 { 2179 if (0x0b0 == BitfR(w,19,8,_b198)) /* mtcpu */ 2180 db_printf("mtcpu\t%%r%d,%%dr%d", Rsa(w), Rtb(w)); 2181 else if (0x0d0 == BitfR(w,19,8,_b198)) /* mfcpu */ 2182 db_printf("mfcpu\t%%dr%d,%%r%d", Rsb(w), Rta(w)); 2183 else { 2184 db_printf(i->mnem); 2185 if (Match("diag")) 2186 db_printf("\t0x%X",w.w & 0x03ffffff); 2187 else { 2188 db_printf("?????"); 2189 return (0); 2190 } 2191 } 2192 return (1); 2193 } 2194 2195 int 2196 fmpysubDasm(const struct inst *i, OFS ofs, union insn w) 2197 { 2198 if (SinglePrec(w)) 2199 db_printf("SUB,SGL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2200 fsreg[Ms1(w)], fsreg[Ms2(w)], fsreg[Mt(w)], 2201 fsreg[As(w)], fsreg[Ad(w)]); 2202 else 2203 db_printf("SUB,DBL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2204 fdreg[Ms1(w)], fdreg[Ms2(w)], fdreg[Mt(w)], 2205 fdreg[As(w)], fdreg[Ad(w)]); 2206 return (1); 2207 } 2208 2209 int 2210 fmpyaddDasm(const struct inst *i, OFS ofs, union insn w) 2211 { 2212 const char 2213 *ms1 = SinglePrec(w) ? fsreg[Ms1(w)] : fdreg[Ms1(w)], 2214 *ms2 = SinglePrec(w) ? fsreg[Ms2(w)] : fdreg[Ms2(w)], 2215 *mt = SinglePrec(w) ? fsreg[Mt(w)] : fdreg[Mt(w)], 2216 *as = SinglePrec(w) ? fsreg[As(w)] : fdreg[As(w)], 2217 *ad = SinglePrec(w) ? fsreg[Ad(w)] : fdreg[Ad(w)]; 2218 2219 if (Rsd(w) == 0) 2220 db_printf("\t%%fcfxt,%s,%%f%s,%%f%s,%%f%s", 2221 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt); 2222 else 2223 db_printf("add%s\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2224 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt, as, ad); 2225 2226 return (1); 2227 } 2228 2229 vaddr_t 2230 db_disasm(vaddr_t loc, bool flag) 2231 { 2232 const struct inst *i; 2233 const struct majoropcode *m; 2234 u_int ext; 2235 union insn instruct; 2236 OFS ofs = 0; 2237 2238 iExInit(); 2239 2240 if (USERMODE(loc)) { 2241 if (copyin((void *)(loc &~ HPPA_PC_PRIV_MASK), 2242 &instruct, sizeof(instruct))) 2243 instruct.w = 0; 2244 } else 2245 instruct.w = *(int *)loc; 2246 2247 m = &majopcs[Opcode(instruct)]; 2248 ext = OpExt(instruct.w, m); 2249 if (ext <= m->maxsubop) { 2250 /* special hack for majopcs table layout */ 2251 if (m->maxsubop == 1) 2252 i = (const struct inst *)m->subops; 2253 else 2254 i = m->subops[ext]; 2255 2256 if (i) { 2257 if (i->dasmfcn != coprDasm && i->dasmfcn != diagDasm && 2258 i->dasmfcn != ariDasm && i->dasmfcn != scDasm && 2259 i->dasmfcn != ldDasm) 2260 db_printf("%s", i->mnem); 2261 if (i->dasmfcn) 2262 (*i->dasmfcn)(i, ofs, instruct); 2263 } else { 2264 db_printf("undefined subop"); 2265 } 2266 } else 2267 db_printf("undefined"); 2268 2269 db_printf("\n"); 2270 return (loc + sizeof(instruct)); 2271 } 2272
Indexes created Fri Sep 26 20:09:58 GMT 2025