db_disasm.c revision 1.3
1 /* $NetBSD: db_disasm.c,v 1.3 2003/08/31 01:26:34 chs Exp $ */ 2 3 /* $OpenBSD: db_disasm.c,v 1.9 2000/04/18 20:02:45 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Michael Shalayeff. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * (c) Copyright 1992 HEWLETT-PACKARD COMPANY 36 * 37 * To anyone who acknowledges that this file is provided "AS IS" 38 * without any express or implied warranty: 39 * permission to use, copy, modify, and distribute this file 40 * for any purpose is hereby granted without fee, provided that 41 * the above copyright notice and this notice appears in all 42 * copies, and that the name of Hewlett-Packard Company not be 43 * used in advertising or publicity pertaining to distribution 44 * of the software without specific, written prior permission. 45 * Hewlett-Packard Company makes no representations about the 46 * suitability of this software for any purpose. 47 */ 48 49 /* 50 * unasm.c -- HP_PA Instruction Printer 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.3 2003/08/31 01:26:34 chs Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 59 #include <machine/db_machdep.h> 60 #include <ddb/db_access.h> 61 #include <ddb/db_sym.h> 62 #include <ddb/db_output.h> 63 #include <ddb/db_interface.h> 64 65 66 /* IMPORTANT NOTE: 67 * All modules using this header may assume that the datatype "int" is a 68 * 32-bit (or > 32-bit) signed quantity. 69 */ 70 71 72 /* Spectrum Architecturally Defined Datatypes */ 73 struct doubleword { 74 int wd0; 75 int wd1; 76 }; 77 78 struct quadword { 79 struct doubleword d0; 80 struct doubleword d1; 81 }; 82 83 /* datatypes for halfword and byte fields of a word are defined 84 * in ssBits.h */ 85 86 /* Memory addressing datatypes */ 87 typedef unsigned int SID, /* range [0..MAXSID] */ 88 PGID, /* range [0..MAXPGID] */ 89 OFS, /* range [0..MAXINT] */ 90 REALADR; /* range [0..MAXINT] */ 91 92 93 /* data sizes */ 94 enum datasize { Byte, Halfword, Word, Doubleword, Quadword, Variable }; 95 96 /* Miscellaneous datatypes */ 97 typedef unsigned int FLAGS; 98 99 /* struct for entry in unwind table */ 100 struct ute { 101 int word1; 102 int word2; 103 int word3; 104 int word4; 105 }; 106 /* 107 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 108 * 109 * Spectrum Instruction Set Condition Completer Bit Assignments 110 * Dan Magenheimer - 6/14/82 111 * Terrence Miller - 6/21/82 112 * Computer Research Center, Hewlett-Packard Labs 113 * 114 * (c) copyright 1982 115 * (p) protected 1982 116 * The Hewlett-Packard Company 117 * Hewlett-Packard Laboratories 118 * Computer Research Center 119 * Palo Alto, California 120 * 121 * *** HP Company Confidential *** 122 * 123 * Log: unasm.c,v 124 * Revision 1.5 1994/07/21 22:32:05 mike 125 * official HP copyright notice 126 * 127 * Revision 1.4 1992/07/08 12:19:52 dalton 128 * Checkin before split to 1.0.4 release (by LBS). 129 * 130 * Revision 1.3 92/06/06 16:16:45 dalton 131 * *** empty log message *** 132 * 133 * Revision 1.2 92/06/06 15:42:28 dalton 134 * Changed include to be a path relative to hp800. 135 * 136 * Revision 1.1 92/06/06 14:05:33 dalton 137 * Initial revision 138 * 139 * Revision 1.2 91/04/14 20:29:49 osfrcs 140 * Initial version. 141 * [91/03/30 09:20:34 brezak] 142 * 143 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 144 * Initial version. 145 * [91/03/30 09:20:34 brezak] 146 * 147 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 148 * Initial version. 149 * 150 * Revision 1.1 88/07/11 14:05:15 14:05:15 ren (Bob Naas) 151 * Initial revision 152 * 153 * Revision 5.2 87/07/02 14:45:57 14:45:57 kent (Kent McMullen) 154 * added constants to support addDasm and addDCond added to ssDID.c 155 * 156 * Revision 5.1 87/02/27 11:12:08 11:12:08 kent (Kent McMullen) 157 * update all src to 5.1 158 * 159 * Revision 5.0 87/02/18 16:31:15 16:31:15 kent (Kent McMullen) 160 * update all revision numbers to 5.0 for release 161 * 162 * Revision 1.1 86/07/15 08:34:55 08:34:55 kent (Kent McMullen) 163 * Initial revision 164 * 165 * Revision 4.1 83/10/25 17:01:22 17:01:22 djm (Daniel J Magenheimer) 166 * First release for ACD v4 167 * 168 * Revision 3.0 83/06/13 10:22:59 djm (Daniel Magenheimer) 169 * First release for distribution 170 * 171 * 172 */ 173 174 175 /* Arithmetic/Logical Conditions */ 176 #define NEV 0x0 177 #define EQZ 0x2 178 #define LT 0x4 179 #define LE 0x6 180 #define LLT 0x8 181 #define NUV 0x8 182 #define LLE 0xA 183 #define ZNV 0xA 184 #define SV 0xC 185 #define OD 0xE 186 #define TR 0x1 187 #define NEQZ 0x3 188 #define GE 0x5 189 #define GT 0x7 190 #define LGE 0x9 191 #define UV 0x9 192 #define LGT 0xB 193 #define VNZ 0xB 194 #define NSV 0xD 195 #define EV 0xF 196 197 /* unit conditions */ 198 #define SBZ 0x4 199 #define SHZ 0x6 200 #define SDC 0x8 201 #define SBC 0xC 202 #define SHC 0xE 203 #define NBZ 0x5 204 #define NHZ 0x7 205 #define NDC 0x9 206 #define NBC 0xD 207 #define NHC 0xF 208 209 /*field conditions */ 210 #define XEQ 0x1 211 #define XLT 0x2 212 #define XOD 0x3 213 #define XTR 0x4 214 #define XNE 0x5 215 #define XGE 0x6 216 #define XEV 0x7 217 218 219 220 /* 221 * These macros are designed to be portable to all machines that have 222 * a wordsize greater than or equal to 32 bits that support the portable 223 * C compiler and the standard C preprocessor. Wordsize (default 32) 224 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11) 225 * should be predefined using the constants HOSTWDSZ and BITFRL and 226 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20). 227 * Note that the macro arguments assume that the integer being referenced 228 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the 229 * most significant bit. 230 */ 231 232 #ifndef HOSTWDSZ 233 #define HOSTWDSZ 32 234 #endif 235 236 #ifdef vax 237 #ifndef BITFLR 238 #define BITFRL 239 #endif 240 #else 241 #define BITFLR 242 #endif 243 244 /*########################### Macros ######################################*/ 245 246 /*--------------------------------------------------------------------------- 247 * DeclareBitfield$Reference - Declare a structure to be used to reference 248 * a specified bitfield within an integer (using BitfR, see below). 249 * The argument "n" must be an identifier name not used elsewhere in the 250 * program , "s" and "l" must (alas!) be constants. (Suggestion: if 251 * "s" == 2 and "l" == 8, use _b28 for "n".) The name "BITFLR" should 252 * be pre-defined if the compiler assigns bitfields from left-to-right. 253 * The resultant macro expansion defines a stucture in which the bit field 254 * starting at position "s" with length "l" may be referenced by accessing 255 * member "n". [Note: The leftmost bits in a 36-bit word may be accessed 256 * by specifying -4 <= s < 0 on the DEC-20.] 257 *---------------------------------------------------------------------------*/ 258 259 #ifdef BITFRL 260 #define DeclBitfR(s,l,n) struct n { int:(HOSTWDSZ-(s)-(l)); unsigned n:l;}; 261 #else 262 #define DeclBitfR(s,l,n) struct n { int:((s)+(HOSTWDSZ-32)); unsigned n:l;}; 263 #endif 264 265 /*--------------------------------------------------------------------------- 266 * Bitfield$Reference - Reference a specified bitfield within an integer. 267 * The argument "i" must be an addressable variable (i.e., not a register 268 * variable or an expression... but see BitfX below), "n" must be an 269 * identifier name declared in a DeclBitfR invocation. The resultant 270 * macro expansion references the bit field in "i" described by the 271 * DeclBitfR invocation with the same name ("n"). BitfR may be used as 272 * an lvalue or an rvalue. (i.e., either side of an assignment statement) 273 * The "s" and "l" arguments are historical and are now unused. (They 274 * correspond to the "s" and "l" arguments in DeclBitfR) 275 * Translates to a single instruction on both the VAX and the DEC-20. 276 *---------------------------------------------------------------------------*/ 277 #define BitfR(i,s,l,n) (((struct n *)&i)->n) 278 279 /*--------------------------------------------------------------------------- 280 * Bitfield$eXtract - Extract the specified field from an integer. Arguments 281 * are the same as for BitfR (except no "n"), however both "s" and "l" need 282 * no longer be constants. May only be used as an rvalue. Translates to 283 * two instructions on the VAX, three on the DEC-20. 284 *---------------------------------------------------------------------------*/ 285 286 #define BitfX(i,s,l) (((i) >> (32-(s)-(l))) & ((1 << (l)) - 1)) 287 288 289 /*--------------------------------------------------------------------------- 290 * Mask$32bits - Mask the low order 32 bits of passed word. No-op on 32 291 * bit machines. 292 *---------------------------------------------------------------------------*/ 293 294 #if HOSTWDSZ > 32 295 #define Mask32(x) ((x) & 0xffffffff) 296 #else 297 #define Mask32(x) (x) 298 #endif 299 300 301 /*--------------------------------------------------------------------------- 302 * SignExtend$32bits - Force the high-order bits in machines with wordsize 303 * longer than 32 to match bit 0. 304 *---------------------------------------------------------------------------*/ 305 306 #if HOSTWDSZ > 32 307 #define SignEx32(x) (((x) & 0x80000000) ? ((x) | ((unsigned)-1 << 32)) \ 308 : Mask32(x)) 309 #else 310 #define SignEx32(x) (x) 311 #endif 312 313 /**************************/ 314 /* bit field declarations */ 315 /**************************/ 316 317 /* since the compiler complains if a structure name is declared twice, even 318 * if the declarations are identical, all DeclBitfR invocations are 319 * given here in one file. */ 320 321 DeclBitfR(0,1,_b01) 322 DeclBitfR(0,15,_b015) 323 DeclBitfR(0,16,_b016) 324 DeclBitfR(0,4,_b04) 325 DeclBitfR(0,6,_b06) 326 DeclBitfR(0,8,_b08) 327 DeclBitfR(4,1,_b41) 328 DeclBitfR(4,4,_b44) 329 DeclBitfR(6,1,_b61) 330 DeclBitfR(6,13,_b613) 331 DeclBitfR(6,15,_b615) 332 DeclBitfR(6,17,_b617) 333 DeclBitfR(6,26,_b626) 334 DeclBitfR(6,5,_b65) 335 DeclBitfR(7,1,_b71) 336 DeclBitfR(8,1,_b81) 337 DeclBitfR(8,4,_b84) 338 DeclBitfR(8,8,_b88) 339 DeclBitfR(9,1,_b91) 340 DeclBitfR(10,1,_b101) 341 DeclBitfR(11,1,_b111) 342 DeclBitfR(11,10,_b1110) 343 DeclBitfR(11,4,_b114) 344 DeclBitfR(11,5,_b115) 345 DeclBitfR(12,1,_b121) 346 DeclBitfR(12,4,_b124) 347 DeclBitfR(13,1,_b131) 348 DeclBitfR(14,1,_b141) 349 DeclBitfR(15,1,_b151) 350 DeclBitfR(16,1,_b161) 351 DeclBitfR(16,15,_b1615) 352 DeclBitfR(16,16,_b1616) 353 DeclBitfR(16,2,_b162) 354 DeclBitfR(16,3,_b163) 355 DeclBitfR(16,4,_b164) 356 DeclBitfR(16,5,_b165) 357 DeclBitfR(16,8,_b168) 358 DeclBitfR(17,1,_b171) 359 DeclBitfR(18,1,_b181) 360 DeclBitfR(18,13,_b1813) 361 DeclBitfR(18,2,_b182) 362 DeclBitfR(18,7,_b187) 363 DeclBitfR(19,1,_b191) 364 DeclBitfR(19,8,_b198) 365 DeclBitfR(19,10,_b1910) 366 DeclBitfR(20,11,_b2011) 367 DeclBitfR(20,2,_b202) 368 DeclBitfR(20,4,_b204) 369 DeclBitfR(21,10,_b2110) 370 DeclBitfR(21,2,_b212) 371 DeclBitfR(21,5,_b215) 372 DeclBitfR(22,5,_b225) 373 DeclBitfR(23,3,_b233) 374 DeclBitfR(24,1,_b241) 375 DeclBitfR(24,4,_b244) 376 DeclBitfR(24,8,_b248) 377 DeclBitfR(25,1,_b251) 378 DeclBitfR(26,1,_b261) 379 DeclBitfR(27,1,_b271) 380 DeclBitfR(27,4,_b274) 381 DeclBitfR(27,5,_b275) 382 DeclBitfR(28,1,_b281) 383 DeclBitfR(28,4,_b284) 384 DeclBitfR(29,1,_b291) 385 DeclBitfR(30,1,_b301) 386 DeclBitfR(30,2,_b302) 387 DeclBitfR(31,1,_b311) 388 389 /******************/ 390 /* Word subfields */ 391 /******************/ 392 393 #define Sign(i) BitfR(i,0,1,_b01) 394 /* halfwords */ 395 #define Hwd0(i) BitfR(i,0,16,_b016) 396 #define Hwd1sign(i) BitfR(i,16,1,_b161) 397 #define Hwd1(i) BitfR(i,16,16,_b1616) 398 /* bytes */ 399 #define Byte0(i) BitfR(i,0,8,_b08) 400 #define Byte1sign(i) BitfR(i,8,1,_b81) 401 #define Byte1(i) BitfR(i,8,8,_b88) 402 #define Byte2(i) BitfR(i,16,8,_b168) 403 #define Byte3sign(i) BitfR(i,24,1,_b241) 404 #define Byte3(i) BitfR(i,24,8,_b248) 405 /* digits */ 406 #define Digit0(i) BitfR(i,0,4,_b04) 407 #define Digit1(i) BitfR(i,4,4,_b44) 408 #define Digit2(i) BitfR(i,8,4,_b84) 409 #define Digit3(i) BitfR(i,12,4,_b124) 410 #define Digit4(i) BitfR(i,16,4,_b164) 411 #define Digit5(i) BitfR(i,20,4,_b204) 412 #define Digit6(i) BitfR(i,24,4,_b244) 413 #define Digit7(i) BitfR(i,28,4,_b284) 414 415 /* Wordsize definitions */ 416 417 #define BIT_P_DW 64 /* bits/doubleword */ 418 #define BIT_P_WD 32 /* bits/word */ 419 #define BIT_P_HW 16 /* bits/halfword */ 420 #define BIT_P_BYT 8 /* bits/byte */ 421 #define BYT_P_DW 8 /* bytes/doubleword */ 422 #define BYT_P_WD 4 /* bytes/word */ 423 #define BYT_P_HW 2 /* bytes/halfword */ 424 425 /* Masks */ 426 427 #define WDMASK 0xffffffff /* 32-bit mask */ 428 #define OFSMASK 0xffffffff /* 32-bit mask */ 429 #define SIDMASK 0xffffffff /* 32-bit mask */ 430 #define SIGNMASK 0x80000000 /* 32 bit word sign bit */ 431 432 /* Alignments */ 433 434 #define wdalign(ofs) (ofs &= ~3) 435 /* 436 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 437 * 438 * Spectrum Simulator Instruction Opcode Definitions 439 * Dan Magenheimer 440 * Computer Research Center, Hewlett-Packard Labs 441 * 442 * (c) copyright 1982 443 * (p) protected 1982 444 * The Hewlett-Packard Company 445 * Hewlett-Packard Laboratories 446 * Computer Research Center 447 * Palo Alto, California 448 * 449 * *** HP Company Confidential *** 450 * 451 * Log: unasm.c,v 452 * Revision 1.5 1994/07/21 22:32:05 mike 453 * official HP copyright notice 454 * 455 * Revision 1.4 1992/07/08 12:19:52 dalton 456 * Checkin before split to 1.0.4 release (by LBS). 457 * 458 * Revision 1.3 92/06/06 16:16:45 dalton 459 * *** empty log message *** 460 * 461 * Revision 1.2 92/06/06 15:42:28 dalton 462 * Changed include to be a path relative to hp800. 463 * 464 * Revision 1.1 92/06/06 14:05:33 dalton 465 * Initial revision 466 * 467 * Revision 1.2 91/04/14 20:29:49 osfrcs 468 * Initial version. 469 * [91/03/30 09:20:34 brezak] 470 * 471 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 472 * Initial version. 473 * [91/03/30 09:20:34 brezak] 474 * 475 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 476 * Initial version. 477 * 478 * Revision 6.1 89/09/06 10:39:58 burroughs 479 * Added shadow registers for gr0-gr7. 480 * gr0-7 are copied into sh0-7 whenever a trap occurs 481 * the instruction RFIR restores gr0-7 from sh0-7 and returns from 482 * interrupt. 483 * the "sh" command displays the shadow registers 484 * = sh7 0x789 works, too. 485 * 486 * Revision 6.0 89/09/01 15:46:37 15:46:37 burroughs (Greg Burroughs) 487 * baseline for pcx simple offsite 488 * 489 * Revision 5.2 87/09/02 14:30:23 14:30:23 kent 490 * separated stat gathering for indexed vs short. 491 * this will NOT work if cache hints ever get used 492 * since this field was assumed always zero 493 * 494 * Revision 5.1 87/02/27 11:12:16 11:12:16 kent (Kent McMullen) 495 * update all src to 5.1 496 * 497 * Revision 5.0 87/02/18 16:31:35 16:31:35 kent (Kent McMullen) 498 * update all revision numbers to 5.0 for release 499 * 500 * Revision 1.1 86/07/15 08:34:57 08:34:57 kent (Kent McMullen) 501 * Initial revision 502 * 503 * Revision 4.1 83/10/25 17:02:34 17:02:34 djm (Daniel J Magenheimer) 504 * First release for ACD v4 505 * 506 * Revision 3.0 83/06/13 10:24:45 djm (Daniel Magenheimer) 507 * First release for distribution 508 * 509 * 510 */ 511 512 /* 513 * Changes: 514 * 01/30/90 ejf Simplify SPOPn support, now only gives assist emulation trap. 515 * 01/19/90 ejf Replace linpak instructions with just FSTQ[SX]. 516 * 12/19/89 ejf Add PA89 new floating point opcode 0E. 517 * 12/18/89 ejf Change 5 ops to PA89 format. 518 * 12/01/89 ejf Move additional instructions fmas, fmaa, fld2, fst2 to ssILst 519 * 09/22/89 ejf Fix unbalanced comments. 520 */ 521 522 523 /* ..and modified by hand to remove the load/store short references */ 524 /* ..and modified by hand to make memory management ops conform to the 525 * requirement that all subops of a major opcode begin in the same 526 * place and have the same length */ 527 528 #define LDW 0x12, 0x00, 0, 0 /* LOAD WORD */ 529 #define LDWM 0x13, 0x00, 0, 0 /* LOAD WORD and MODIFY */ 530 #define LDH 0x11, 0x00, 0, 0 /* LOAD HALFWORD */ 531 #define LDB 0x10, 0x00, 0, 0 /* LOAD BYTE */ 532 #define LDO 0x0d, 0x00, 0, 0 /* LOAD OFFSET */ 533 #define STW 0x1a, 0x00, 0, 0 /* STORE WORD */ 534 #define STWM 0x1b, 0x00, 0, 0 /* STORE WORD and MODIFY */ 535 #define STH 0x19, 0x00, 0, 0 /* STORE HALFWORD */ 536 #define STB 0x18, 0x00, 0, 0 /* STORE BYTE */ 537 #define LDWX 0x03, 0x02, 19, 7 /* LOAD WORD INDEXED */ 538 #define LDHX 0x03, 0x01, 19, 7 /* LOAD HALFWORD INDEXED */ 539 #define LDBX 0x03, 0x00, 19, 7 /* LOAD BYTE INDEXED */ 540 #define LDWAX 0x03, 0x06, 19, 7 /* LOAD WORD ABSOLUTE INDEXED */ 541 #define LDCWX 0x03, 0x07, 19, 7 /* LOAD and CLEAR WORD INDEXED */ 542 #define LDWS 0x03, 0x42, 19, 7 /* LOAD WORD SHORT DISP */ 543 #define LDHS 0x03, 0x41, 19, 7 /* LOAD HALFWORD SHORT DISP */ 544 #define LDBS 0x03, 0x40, 19, 7 /* LOAD BYTE SHORT DISP */ 545 #define LDWAS 0x03, 0x46, 19, 7 /* LOAD WORD ABSOLUTE SHORT DISP */ 546 #define LDCWS 0x03, 0x47, 19, 7 /* LOAD and CLEAR WORD SHORT DISP */ 547 #define STWS 0x03, 0x4a, 19, 7 /* STORE WORD SHORT DISP */ 548 #define STHS 0x03, 0x49, 19, 7 /* STORE HALFWORD SHORT DISP */ 549 #define STBS 0x03, 0x48, 19, 7 /* STORE BYTE SHORT DISP */ 550 #define STWAS 0x03, 0x4e, 19, 7 /* STORE WORD ABSOLUTE SHORT DISP */ 551 #define STBYS 0x03, 0x4c, 19, 7 /* STORE BYTES SHORT DISP */ 552 #define LDIL 0x08, 0x00, 0, 0 /* LOAD IMMED LEFT */ 553 #define ADDIL 0x0a, 0x00, 0, 0 /* ADD IMMED LEFT */ 554 #define BL 0x3a, 0x00, 16, 3 /* BRANCH [and LINK] */ 555 #define GATE 0x3a, 0x01, 16, 3 /* GATEWAY */ 556 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ 557 #define BV 0x3a, 0x06, 16, 3 /* BRANCH VECTORED */ 558 #define BE 0x38, 0x00, 0, 0 /* BRANCH EXTERNAL */ 559 #define BLE 0x39, 0x00, 0, 0 /* BRANCH and LINK EXTERNAL */ 560 #define MOVB 0x32, 0x00, 0, 0 /* MOVE and BRANCH */ 561 #define MOVIB 0x33, 0x00, 0, 0 /* MOVE IMMED and BRANCH */ 562 #define COMBT 0x20, 0x00, 0, 0 /* COMPARE and BRANCH if TRUE */ 563 #define COMBF 0x22, 0x00, 0, 0 /* COMPARE and BRANCH if FALSE */ 564 #define COMIBT 0x21, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if TRUE */ 565 #define COMIBF 0x23, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if FALSE */ 566 #define ADDBT 0x28, 0x00, 0, 0 /* ADD and BRANCH if TRUE */ 567 #define ADDBF 0x2a, 0x00, 0, 0 /* ADD and BRANCH if FALSE */ 568 #define ADDIBT 0x29, 0x00, 0, 0 /* ADD IMMED and BRANCH if TRUE */ 569 #define ADDIBF 0x2b, 0x00, 0, 0 /* ADD IMMED and BRANCH if FALSE */ 570 #define BVB 0x30, 0x00, 0, 0 /* BRANCH on VARIABLE BIT */ 571 #define BB 0x31, 0x00, 0, 0 /* BRANCH on BIT */ 572 #define ADD 0x02, 0x30, 20, 7 /* ADD */ 573 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ 574 #define ADDO 0x02, 0x70, 20, 7 /* ADD and TRAP on OVFLO */ 575 #define SH1ADD 0x02, 0x32, 20, 7 /* SHIFT 1, ADD */ 576 #define SH1ADDL 0x02, 0x52, 20, 7 /* SHIFT 1, ADD LOGICAL */ 577 #define SH1ADDO 0x02, 0x72, 20, 7 /* SHIFT 1, ADD and TRAP on OVFLO */ 578 #define SH2ADD 0x02, 0x34, 20, 7 /* SHIFT 2, ADD */ 579 #define SH2ADDL 0x02, 0x54, 20, 7 /* SHIFT 2, ADD LOGICAL */ 580 #define SH2ADDO 0x02, 0x74, 20, 7 /* SHIFT 2, ADD and TRAP on OVFLO */ 581 #define SH3ADD 0x02, 0x36, 20, 7 /* SHIFT 3, ADD */ 582 #define SH3ADDL 0x02, 0x56, 20, 7 /* SHIFT 3, ADD LOGICAL */ 583 #define SH3ADDO 0x02, 0x76, 20, 7 /* SHIFT 3, ADD and TRAP on OVFLO */ 584 #define ADDC 0x02, 0x38, 20, 7 /* ADD with CARRY */ 585 #define ADDCO 0x02, 0x78, 20, 7 /* ADD with CARRY and TRAP on OVFLO */ 586 #define SUB 0x02, 0x20, 20, 7 /* SUBTRACT */ 587 #define SUBO 0x02, 0x60, 20, 7 /* SUBTRACT and TRAP on OVFLO */ 588 #define SUBB 0x02, 0x28, 20, 7 /* SUBTRACT with BORROW */ 589 #define SUBBO 0x02, 0x68, 20, 7 /* SUBTRACT with BORROW and TRAP on OVFLO */ 590 #define SUBT 0x02, 0x26, 20, 7 /* SUBTRACT and TRAP on COND */ 591 #define SUBTO 0x02, 0x66, 20, 7 /* SUBTRACT and TRAP on COND or OVFLO */ 592 #define DS 0x02, 0x22, 20, 7 /* DIVIDE STEP */ 593 #define COMCLR 0x02, 0x44, 20, 7 /* COMPARE and CLEAR */ 594 #define OR 0x02, 0x12, 20, 7 /* INCLUSIVE OR */ 595 #define XOR 0x02, 0x14, 20, 7 /* EXCLUSIVE OR */ 596 #define AND 0x02, 0x10, 20, 7 /* AND */ 597 #define ANDCM 0x02, 0x00, 20, 7 /* AND COMPLEMENT */ 598 #define UXOR 0x02, 0x1c, 20, 7 /* UNIT XOR */ 599 #define UADDCM 0x02, 0x4c, 20, 7 /* UNIT ADD COMPLEMENT */ 600 #define UADDCMT 0x02, 0x4e, 20, 7 /* UNIT ADD COMPLEMENT and TRAP on COND */ 601 #define DCOR 0x02, 0x5c, 20, 7 /* DECIMAL CORRECT */ 602 #define IDCOR 0x02, 0x5e, 20, 7 /* INTERMEDIATE DECIMAL CORRECT */ 603 #define ADDI 0x2d, 0x00, 20, 1 /* ADD to IMMED */ 604 #define ADDIO 0x2d, 0x01, 20, 1 /* ADD to IMMED and TRAP on OVFLO */ 605 #define ADDIT 0x2c, 0x00, 20, 1 /* ADD to IMMED and TRAP on COND */ 606 #define ADDITO 0x2c, 0x01, 20, 1 /* ADD to IMMED and TRAP on COND or OVFLO */ 607 #define SUBI 0x25, 0x00, 20, 1 /* SUBTRACT from IMMED */ 608 #define SUBIO 0x25, 0x01, 20, 1 /* SUBTRACT from IMMED and TRAP on OVFLO */ 609 #define COMICLR 0x24, 0x00, 0, 0 /* COMPARE IMMED and CLEAR */ 610 #define VSHD 0x34, 0x00, 19, 3 /* VARIABLE SHIFT DOUBLE */ 611 #define SHD 0x34, 0x02, 19, 3 /* SHIFT DOUBLE */ 612 #define VEXTRU 0x34, 0x04, 19, 3 /* VARIABLE EXTRACT RIGHT UNSIGNED */ 613 #define VEXTRS 0x34, 0x05, 19, 3 /* VARIABLE EXTRACT RIGHT SIGNED */ 614 #define EXTRU 0x34, 0x06, 19, 3 /* EXTRACT RIGHT UNSIGNED */ 615 #define EXTRS 0x34, 0x07, 19, 3 /* EXTRACT RIGHT SIGNED */ 616 #define VDEP 0x35, 0x01, 19, 3 /* VARIABLE DEPOSIT */ 617 #define DEP 0x35, 0x03, 19, 3 /* DEPOSIT */ 618 #define VDEPI 0x35, 0x05, 19, 3 /* VARIABLE DEPOSIT IMMED */ 619 #define DEPI 0x35, 0x07, 19, 3 /* DEPOSIT IMMED */ 620 #define ZVDEP 0x35, 0x00, 19, 3 /* ZERO and VARIABLE DEPOSIT */ 621 #define ZDEP 0x35, 0x02, 19, 3 /* ZERO and DEPOSIT */ 622 #define ZVDEPI 0x35, 0x04, 19, 3 /* ZERO and VARIABLE DEPOSIT IMMED */ 623 #define ZDEPI 0x35, 0x06, 19, 3 /* ZERO and DEPOSIT IMMED */ 624 #define BREAK 0x00, 0x00, 19, 8 /* BREAK */ 625 #define RFI 0x00, 0x60, 19, 8 /* RETURN FROM INTERRUPTION */ 626 #define RFIR 0x00, 0x65, 19, 8 /* RFI & RESTORE SHADOW REGISTERS */ 627 #define SSM 0x00, 0x6b, 19, 8 /* SET SYSTEM MASK */ 628 #define RSM 0x00, 0x73, 19, 8 /* RESET SYSTEM MASK */ 629 #define MTSM 0x00, 0xc3, 19, 8 /* MOVE TO SYSTEM MASK */ 630 #define LDSID 0x00, 0x85, 19, 8 /* LOAD SPACE IDENTIFIER */ 631 #define MTSP 0x00, 0xc1, 19, 8 /* MOVE TO SPACE REGISTER */ 632 #define MTCTL 0x00, 0xc2, 19, 8 /* MOVE TO SYSTEM CONTROL REGISTER */ 633 #define MFSP 0x00, 0x25, 19, 8 /* MOVE FROM SPACE REGISTER */ 634 #define MFCTL 0x00, 0x45, 19, 8 /* MOVE FROM SYSTEM CONTROL REGISTER */ 635 #define SYNC 0x00, 0x20, 19, 8 /* SYNCHRONIZE DATA CACHE */ 636 #define DIAG 0x05, 0x00, 0, 0 /* DIAGNOSE */ 637 #define SPOP 0x04, 0x00, 0, 0 /* SPECIAL FUNCTION UNIT */ 638 #define COPR 0x0c, 0x00, 0, 0 /* COPROCESSOR */ 639 #define CLDWX 0x09, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 640 #define CLDDX 0x0b, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 641 #define CSTWX 0x09, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 642 #define CSTDX 0x0b, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 643 #define CLDWS 0x09, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 644 #define CLDDS 0x0b, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 645 #define CSTWS 0x09, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 646 #define CSTDS 0x0b, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 647 #define FLOAT0 0x0e, 0x00, 21, 2 /* FLOATING POINT CLASS 0 */ 648 #define FLOAT1 0x0e, 0x01, 21, 2 /* FLOATING POINT CLASS 1 */ 649 #define FLOAT2 0x0e, 0x02, 21, 2 /* FLOATING POINT CLASS 2 */ 650 #define FLOAT3 0x0e, 0x03, 21, 2 /* FLOATING POINT CLASS 3 */ 651 #define FMPYSUB 0x26, 0x00, 0, 0 /* FP MULTIPLY AND SUBTRACT */ 652 #define FMPYADD 0x06, 0x00, 0, 0 /* FP MULTIPLY AND ADD/TRUNCATE */ 653 #define FSTQX 0x0f, 0x01, 19, 4 /* FLOATING POINT STORE QUAD INDEXED */ 654 #define FSTQS 0x0f, 0x09, 19, 4 /* FLOATING POINT STORE QUAD SHORT */ 655 /* all of the following have been pushed around to conform */ 656 #define PROBER 0x01, 0x46, 19, 7 /* PROBE READ ACCESS */ 657 #ifdef notdef 658 #define PROBERI 0x01, 0xc6, 19, 7 /* PROBE READ ACCESS IMMEDIATE */ 659 #endif 660 #define PROBEW 0x01, 0x47, 19, 7 /* PROBE WRITE ACCESS */ 661 #ifdef notdef 662 #define PROBEWI 0x01, 0xc7, 19, 7 /* PROBE WRITE ACCESS IMMEDIATE */ 663 #endif 664 #define LPA 0x01, 0x4d, 19, 7 /* LOAD PHYSICAL ADDRESS */ 665 #define LHA 0x01, 0x4c, 19, 7 /* LOAD HASH ADDRESS */ 666 #define PDTLB 0x01, 0x48, 19, 7 /* PURGE DATA TRANS LOOKASIDE BUFFER */ 667 #define PITLB 0x01, 0x08, 19, 7 /* PURGE INST TRANS LOOKASIDE BUFFER */ 668 #define PDTLBE 0x01, 0x49, 19, 7 /* PURGE DATA TLB ENTRY */ 669 #define PITLBE 0x01, 0x09, 19, 7 /* PURGE INST TLB ENTRY */ 670 #define IDTLBA 0x01, 0x41, 19, 7 /* INSERT DATA TLB ADDRESS */ 671 #define IITLBA 0x01, 0x01, 19, 7 /* INSERT INSTRUCTION TLB ADDRESS */ 672 #define IDTLBP 0x01, 0x40, 19, 7 /* INSERT DATA TLB PROTECTION */ 673 #define IITLBP 0x01, 0x00, 19, 7 /* INSERT INSTRUCTION TLB PROTECTION */ 674 #define PDC 0x01, 0x4e, 19, 7 /* PURGE DATA CACHE */ 675 #define FDC 0x01, 0x4a, 19, 7 /* FLUSH DATA CACHE */ 676 #define FIC 0x01, 0x0a, 19, 7 /* FLUSH INSTRUCTION CACHE */ 677 #define FDCE 0x01, 0x4b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 678 #define FICE 0x01, 0x0b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 679 680 /* 681 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 682 * 683 * Spectrum Simulator Instruction Set Constants and Datatypes 684 * Dan Magenheimer - 4/28/82 685 * Computer Research Center, Hewlett-Packard Labs 686 * 687 * (c) copyright 1982 688 * (p) protected 1982 689 * The Hewlett-Packard Company 690 * Hewlett-Packard Laboratories 691 * Computer Research Center 692 * Palo Alto, California 693 * 694 * *** HP Company Confidential *** 695 * 696 * Log: unasm.c,v 697 * Revision 1.5 1994/07/21 22:32:05 mike 698 * official HP copyright notice 699 * 700 * Revision 1.4 1992/07/08 12:19:52 dalton 701 * Checkin before split to 1.0.4 release (by LBS). 702 * 703 * Revision 1.3 92/06/06 16:16:45 dalton 704 * *** empty log message *** 705 * 706 * Revision 1.2 92/06/06 15:42:28 dalton 707 * Changed include to be a path relative to hp800. 708 * 709 * Revision 1.1 92/06/06 14:05:33 dalton 710 * Initial revision 711 * 712 * Revision 1.2 91/04/14 20:29:49 osfrcs 713 * Initial version. 714 * [91/03/30 09:20:34 brezak] 715 * 716 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 717 * Initial version. 718 * [91/03/30 09:20:34 brezak] 719 * 720 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 721 * Initial version. 722 * 723 ;Revision 1.1 88/07/11 14:05:21 14:05:21 ren (Bob Naas) 724 ;Initial revision 725 ; 726 * Revision 5.1 87/02/27 11:12:23 11:12:23 kent (Kent McMullen) 727 * update all src to 5.1 728 * 729 * Revision 5.0 87/02/18 16:31:52 16:31:52 kent (Kent McMullen) 730 * update all revision numbers to 5.0 for release 731 * 732 * Revision 1.1 86/07/15 08:35:00 08:35:00 kent (Kent McMullen) 733 * Initial revision 734 * 735 * Revision 4.3 85/11/12 09:28:44 09:28:44 viggy (Viggy Mokkarala) 736 * first mpsim version, partially stable 737 * 738 * Revision 4.2 84/07/16 17:20:57 17:20:57 djm () 739 * Define field macros for COPR and SFU insts 740 * 741 * Revision 4.1 83/10/25 17:10:14 djm (Daniel Magenheimer) 742 * First release for ACD v4 743 * 744 * Revision 3.1 83/08/03 14:09:59 djm (Daniel Magenheimer) 745 * Sys calls, args, -S, bug fixes, etc. 746 * 747 * Revision 3.0 83/06/13 10:25:13 djm (Daniel Magenheimer) 748 * First release for distribution 749 * 750 * 751 */ 752 /* 753 * Changes: 754 * 12/01/89 ejf Add Rsd(), Rse(), Rtd(), Rte() for 5 ops. 755 * 11/30/89 ejf Make instruction use counters shared, not per cpu. 756 * 11/28/89 ejf Change majoropcode for quicker extension extract. 757 */ 758 759 760 761 /* 762 * Dependencies: std.h, ssDefs.h, bits.h 763 */ 764 765 766 /* Lookup/Execute structure for instructions */ 767 struct inst { 768 u_char majopc; /* major opcode of instruction, 0..MAXOPC */ 769 u_char opcext; /* opcode extension, 0 if not applic. */ 770 u_char extbs; /* starting bit pos of extension field */ 771 u_char extbl; /* bit length of extension field */ 772 u_int count; /* frequency counter for analysis */ 773 char mnem[8]; /* ascii mnemonic */ 774 /* disassembly function */ 775 int (*dasmfcn)(const struct inst *, OFS, int); 776 }; 777 778 779 #define NMAJOPCS 64 780 781 struct majoropcode { 782 const struct inst **subops; /* pointer to table of subops indexed by 783 * opcode extension */ 784 u_int maxsubop; /* largest opcode extension value or 0 */ 785 u_int extshft; /* right shift amount for extension field */ 786 u_int extmask; /* post shift mask for extension field */ 787 }; 788 789 #define OpExt(i,m) ((i >> m->extshft) & m->extmask) /* extract opcode extension */ 790 791 792 /*****************************/ 793 /* Miscellaneous definitions */ 794 /*****************************/ 795 796 /* Load/Store Indexed Opcode Extension Cache Control */ 797 #define NOACTION 0 798 #define STACKREF 1 799 #define SEQPASS 2 800 #define PREFETCH 3 801 802 /******************************/ 803 /* Fields within instructions */ 804 /******************************/ 805 806 /* opcode */ 807 #define Opcode(i) BitfR(i,0,6,_b06) 808 /* opcode true/false bit */ 809 #define OpcTF(i) BitfR(i,4,1,_b41) 810 /* register sources */ 811 #define Rsa(i) BitfR(i,11,5,_b115) 812 #define Rsb(i) BitfR(i,6,5,_b65) 813 #define Rsc(i) BitfR(i,27,5,_b275) 814 #define Rsd(i) BitfR(i,21,5,_b215) 815 #define Rse(i) BitfR(i,16,5,_b165) 816 /* register targets */ 817 #define Rta(i) BitfR(i,11,5,_b115) 818 #define Rtb(i) BitfR(i,6,5,_b65) 819 #define Rtc(i) BitfR(i,27,5,_b275) 820 #define Rtd(i) BitfR(i,21,5,_b215) 821 #define Rte(i) BitfR(i,16,5,_b165) 822 /* 5-bit immediates (Magnitude, Sign) */ 823 #define Imb5(i) BitfR(i,6,5,_b65) 824 #define Ima5M(i) BitfR(i,11,4,_b114) 825 #define Ima5S(i) BitfR(i,15,1,_b151) 826 #define Ima5A(i) BitfR(i,11,5,_b115) 827 #define Imd5(i) BitfR(i,22,5,_b225) 828 #define Imc5M(i) BitfR(i,27,4,_b274) 829 #define Imc5S(i) BitfR(i,31,1,_b311) 830 #define Imc5A(i) BitfR(i,27,5,_b275) 831 /* Other immediates */ 832 #define Im21L(i) BitfR(i,18,2,_b182) 833 #define Im21H(i) BitfR(i,20,11,_b2011) 834 #define Im21M1(i) BitfR(i,16,2,_b162) 835 #define Im21M2(i) BitfR(i,11,5,_b115) 836 #define Im21S(i) BitfR(i,31,1,_b311) 837 #define Im11M(i) BitfR(i,21,10,_b2110) 838 #define Im11S(i) BitfR(i,31,1,_b311) 839 /* displacements/offsets */ 840 #define DispM(i) BitfR(i,18,13,_b1813) 841 #define DispS(i) BitfR(i,31,1,_b311) 842 #define Off5(i) BitfR(i,11,5,_b115) 843 #define Off11H(i) BitfR(i,19,10,_b1910) 844 #define Off11L(i) BitfR(i,29,1,_b291) 845 #define OffS(i) BitfR(i,31,1,_b311) 846 /* miscellaneous */ 847 #define Dss(i) BitfR(i,16,2,_b162) 848 #define Cond(i) BitfR(i,16,3,_b163) 849 #define Cneg(i) BitfR(i,19,1,_b191) 850 #define Cond4(i) BitfR(i,16,4,_b164) /* Cond AND Cneg */ 851 #define Nu(i) BitfR(i,30,1,_b301) 852 #define SrL(i) BitfR(i,16,2,_b162) 853 #define SrH(i) BitfR(i,18,1,_b181) 854 #define ShortDisp(i) BitfR(i,19,1,_b191) 855 #define IndxShft(i) BitfR(i,18,1,_b181) 856 #define ModBefore(i) BitfR(i,18,1,_b181) 857 #define CacheCtrl(i) BitfR(i,20,2,_b202) 858 #define Modify(i) BitfR(i,26,1,_b261) 859 #define ProbeI(i) BitfR(i,18,1,_b181) 860 #define Uid(i) BitfR(i,23,3,_b233) 861 #define Sfu(i) BitfR(i,23,3,_b233) 862 #define CopExt17(i) BitfR(i,6,17,_b617) 863 #define CopExt5(i) BitfR(i,27,5,_b275) 864 #define SpopType(i) BitfR(i,21,2,_b212) 865 #define SpopExt15(i) BitfR(i,6,15,_b615) 866 #define SpopExt10(i) BitfR(i,11,10,_b1110) 867 #define SpopExt5L(i) BitfR(i,16,5,_b165) 868 #define SpopExt5(i) BitfR(i,27,5,_b275) 869 #define NoMajOpc(i) BitfR(i,6,26,_b626) 870 #define Bi1(i) BitfR(i,27,5,_b275) /* fields in BREAK */ 871 #define Bi2(i) BitfR(i,6,13,_b613) 872 873 /* fragmented field collating macros */ 874 #define Ima5(i) (Ima5S(i) ? Ima5M(i) | (-1<<4) : Ima5M(i)) 875 876 #define Imc5(i) (Imc5S(i) ? Imc5M(i) | (-1<<4) : Imc5M(i)) 877 878 #define Disp(i) (DispS(i) ? DispM(i) | (-1<<13) : DispM(i)) 879 880 #define Im21(i) (Im21S(i) << 31 | Im21H(i) << 20 | Im21M1(i) << 18 | \ 881 Im21M2(i) << 13 | Im21L(i) << 11) 882 883 #define Im11(i) (Im11S(i) ? Im11M(i) | (-1<<10) : Im11M(i)) 884 885 #define Bdisp(i) ((OffS(i) ? (Off5(i)<<11 | Off11L(i)<<10|Off11H(i)) \ 886 /* branch displacement (bytes) */ | (-1 << 16) \ 887 : (Off5(i)<<11|Off11L(i)<<10|Off11H(i))) << 2) 888 889 #define Cbdisp(i) ((OffS(i) ? (Off11L(i) << 10 | Off11H(i)) \ 890 /* compare/branch disp (bytes) */ | (-1 << 11) \ 891 : Off11L(i) << 10 | Off11H(i)) << 2) 892 893 #define Sr(i) (SrH(i)<<2 | SrL(i)) 894 895 /* sfu/copr */ 896 #define CoprExt1(i) (CopExt17(i)) 897 #define CoprExt2(i) (CopExt5(i)) 898 #define CoprExt(i) ((CopExt17(i)<<5) | CopExt5(i)) 899 #define Spop0Ext(i) ((SpopExt15(i)<<5) | SpopExt5(i)) 900 #define Spop1Ext(i) (SpopExt15(i)) 901 #define Spop2Ext(i) ((SpopExt10(i)<<5) | SpopExt5(i)) 902 #define Spop3Ext(i) ((SpopExt5L(i)<<5) | SpopExt5(i)) 903 904 905 /*##################### Globals - Imports ##################################*/ 906 907 /* Disassembly functions */ 908 int fcoprDasm __P((int w, u_int op1, u_int)); 909 char *edDCond __P((u_int cond)); 910 char *unitDCond __P((u_int cond)); 911 char *addDCond __P((u_int cond)); 912 char *subDCond __P((u_int cond)); 913 int blDasm __P((const struct inst *i, OFS ofs, int w)); 914 int ldDasm __P((const struct inst *, OFS, int)); 915 int stDasm __P((const struct inst *i, OFS, int)); 916 int addDasm __P((const struct inst *i, OFS, int)); 917 int unitDasm __P((const struct inst *i, OFS, int)); 918 int iaDasm __P((const struct inst *i, OFS, int)); 919 int shdDasm __P((const struct inst *i, OFS, int)); 920 int extrDasm __P((const struct inst *i, OFS, int)); 921 int vextrDasm __P((const struct inst *i, OFS, int)); 922 int depDasm __P((const struct inst *i, OFS, int)); 923 int vdepDasm __P((const struct inst *i, OFS, int)); 924 int depiDasm __P((const struct inst *i, OFS, int)); 925 int vdepiDasm __P((const struct inst *i, OFS, int)); 926 int limmDasm __P((const struct inst *i, OFS, int)); 927 int brkDasm __P((const struct inst *i, OFS, int)); 928 int lpkDasm __P((const struct inst *i, OFS, int)); 929 int fmpyaddDasm __P((const struct inst *i, OFS, int)); 930 int fmpysubDasm __P((const struct inst *i, OFS, int)); 931 int floatDasm __P((const struct inst *i, OFS, int)); 932 int coprDasm __P((const struct inst *i, OFS, int)); 933 int diagDasm __P((const struct inst *i, OFS, int)); 934 int scDasm __P((const struct inst *i, OFS, int)); 935 int mmgtDasm __P((const struct inst *i, OFS, int)); 936 int ldxDasm __P((const struct inst *i, OFS, int)); 937 int stsDasm __P((const struct inst *i, OFS, int)); 938 int stbysDasm __P((const struct inst *i, OFS, int)); 939 int brDasm __P((const struct inst *i, OFS, int)); 940 int bvDasm __P((const struct inst *i, OFS, int)); 941 int beDasm __P((const struct inst *i, OFS, int)); 942 int cbDasm __P((const struct inst *i,OFS ofs, int)); 943 int cbiDasm __P((const struct inst *i,OFS ofs, int)); 944 int bbDasm __P((const struct inst *i,OFS ofs, int)); 945 int ariDasm __P((const struct inst *i, OFS, int)); 946 947 /*##################### Globals - Exports ##################################*/ 948 /*##################### Local Variables ####################################*/ 949 950 static const char fcoprUndef[] = "copr\t(rsvd or undef.)"; 951 static const char fmtStrTbl[][5] = { "sgl", "dbl", "sgl", "quad" }; 952 static const char condStrTbl[][7] = { 953 "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", 954 "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", 955 "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", 956 "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" 957 }; 958 static const char fsreg[][5] = { 959 "r0L", "r0R", "r1L", "r1R", "r2L", "r2R", "r3L", "r3R", 960 "r4L", "r4R", "r5L", "r5R", "r6L", "r6R", "r7L", "r7R", 961 "r8L", "r8R", "r9L", "r9R", "r10L", "r10R", "r11L", "r11R", 962 "r12L", "r12R", "r13L", "r13R", "r14L", "r14R", "r15L", "r15R", 963 "r16L", "r16R", "r17L", "r17R", "r18L", "r18R", "r19L", "r19R", 964 "r20L", "r20R", "r21L", "r21R", "r22L", "r22R", "r23L", "r23R", 965 "r24L", "r24R", "r25L", "r25R", "r26L", "r26R", "r27L", "r27R", 966 "r28L", "r28R", "r29L", "r29R", "r30L", "r30R", "r31L", "r31R" 967 }; 968 static const char fdreg[][4] = { 969 "r0", "r0", "r1", "r1", "r2", "r2", "r3", "r3", 970 "r4", "r4", "r5", "r5", "r6", "r6", "r7", "r7", 971 "r8", "r8", "r9", "r9", "r10", "r10", "r11", "r11", 972 "r12", "r12", "r13", "r13", "r14", "r14", "r15", "r15", 973 "r16", "r16", "r17", "r17", "r18", "r18", "r19", "r19", 974 "r20", "r20", "r21", "r21", "r22", "r22", "r23", "r23", 975 "r24", "r24", "r25", "r25", "r26", "r26", "r27", "r27", 976 "r28", "r28", "r29", "r29", "r30", "r30", "r31", "r31" 977 }; 978 979 /*##################### Macros #############################################*/ 980 981 #define Match(s) (strncmp(s,i->mnem,sizeof(s)-1) == 0) 982 983 /* bits for assist ops */ 984 #define AstNu(w) Modify(w) 985 #define Fpi(w) (Uid(w)>3) 986 987 /* bits for 5 ops */ 988 #define SinglePrec(i) Modify(i) 989 #define Ms1(i) ((Rsb(i)<<1)+(SinglePrec(i)?((Rsb(i)>15)?1:32):0)) 990 #define Ms2(i) ((Rsa(i)<<1)+(SinglePrec(i)?((Rsa(i)>15)?1:32):0)) 991 #define Mt(i) ((Rtc(i)<<1)+(SinglePrec(i)?((Rtc(i)>15)?1:32):0)) 992 #define As(i) ((Rsd(i)<<1)+(SinglePrec(i)?((Rsd(i)>15)?1:32):0)) 993 #define Ad(i) ((Rte(i)<<1)+(SinglePrec(i)?((Rte(i)>15)?1:32):0)) 994 995 /*##################### Globals - Exports ##################################*/ 996 997 /* To replace instr function, do the following: */ 998 /* a) locate the desired entry in instrs[] below */ 999 /* b) change the 3rd field if an alternate mneumonic is */ 1000 /* desired for window disassembly */ 1001 /* c) change the 4th field to the name of the function being */ 1002 /* used for replacement (i.e. ldwRepl instead of ldw) */ 1003 /* d) change the 5th field if an alternate disassembly routine */ 1004 /* is desired (i.e. ldDasmRepl) */ 1005 1006 static const struct inst instrs[] = { 1007 { LDW, 0, "ldw", ldDasm }, 1008 { LDH, 0, "ldh", ldDasm }, 1009 { LDB, 0, "ldb", ldDasm }, 1010 { LDWM, 0, "ldwm", ldDasm }, 1011 { LDO, 0, "ldo", ldDasm }, 1012 { STW, 0, "stw", stDasm }, 1013 { STH, 0, "sth", stDasm }, 1014 { STB, 0, "stb", stDasm }, 1015 { STWM, 0, "stwm", stDasm }, 1016 { LDWX, 0, "ldw", ldxDasm }, 1017 { LDHX, 0, "ldh", ldxDasm }, 1018 { LDBX, 0, "ldb", ldxDasm }, 1019 { LDCWX, 0, "ldcw", ldxDasm }, 1020 { LDWAX, 0, "ldwa", ldxDasm }, 1021 { LDWS, 0, "ldw", ldxDasm }, 1022 { LDHS, 0, "ldh", ldxDasm }, 1023 { LDBS, 0, "ldb", ldxDasm }, 1024 { LDCWS, 0, "ldcw", ldxDasm }, 1025 { LDWAS, 0, "ldwa", ldxDasm }, 1026 { STWS, 0, "stws", stsDasm }, 1027 { STHS, 0, "sths", stsDasm }, 1028 { STBS, 0, "stbs", stsDasm }, 1029 { STWAS, 0, "stwas", stsDasm }, 1030 { STBYS, 0, "stbys", stbysDasm }, 1031 { LDIL, 0, "ldil", limmDasm }, 1032 { ADDIL, 0, "addil", limmDasm }, 1033 { GATE, 0, "gate", blDasm }, 1034 { BL, 0, "b", blDasm }, 1035 { BLR, 0, "blr", brDasm }, 1036 { BV, 0, "bv", bvDasm }, 1037 { BE, 0, "be", beDasm }, 1038 { BLE, 0, "ble", beDasm }, 1039 { COMBT, 0, "combt", cbDasm }, 1040 { COMBF, 0, "combf", cbDasm }, 1041 { COMIBT, 0, "comibt", cbiDasm }, 1042 { COMIBF, 0, "comibf", cbiDasm }, 1043 { ADDBT, 0, "addbt", cbDasm }, 1044 { ADDBF, 0, "addbf", cbDasm }, 1045 { ADDIBT, 0, "addibt", cbiDasm }, 1046 { ADDIBF, 0, "addibf", cbiDasm }, 1047 { MOVB, 0, "movb", cbDasm }, 1048 { MOVIB, 0, "movib", cbiDasm }, 1049 { BB, 0, "bb", bbDasm }, 1050 { BVB, 0, "bvb", bbDasm }, 1051 { SUBO, 0, "subo", ariDasm }, 1052 { ADD, 0, "add", addDasm }, 1053 { ADDL, 0, "addl", addDasm }, 1054 { ADDO, 0, "addo", ariDasm }, 1055 { SH1ADD, 0, "sh1add", ariDasm }, 1056 { SH1ADDL,0, "sh1addl", ariDasm }, 1057 { SH1ADDO,0, "sh1addo", ariDasm }, 1058 { SH2ADD, 0, "sh2add", ariDasm }, 1059 { SH2ADDL,0, "sh2addl", ariDasm }, 1060 { SH2ADDO,0, "sh2addo", ariDasm }, 1061 { SH3ADD, 0, "sh3add", ariDasm }, 1062 { SH3ADDL,0, "sh3addl", ariDasm }, 1063 { SH3ADDO,0, "sh3addo", ariDasm }, 1064 { SUB, 0, "sub", ariDasm }, 1065 { ADDCO, 0, "addco", ariDasm }, 1066 { SUBBO, 0, "subbo", ariDasm }, 1067 { ADDC, 0, "addc", ariDasm }, 1068 { SUBB, 0, "subb", ariDasm }, 1069 { COMCLR, 0, "comclr", ariDasm }, 1070 { OR, 0, "or", ariDasm }, 1071 { AND, 0, "and", ariDasm }, 1072 { XOR, 0, "xor", ariDasm }, 1073 { ANDCM, 0, "andcm", ariDasm }, 1074 { DS, 0, "ds", ariDasm }, 1075 { UXOR, 0, "uxor", unitDasm }, 1076 { UADDCM, 0, "uaddcm", unitDasm }, 1077 { UADDCMT,0, "uaddcmt", unitDasm }, 1078 { SUBTO, 0, "subto", ariDasm }, 1079 { SUBT, 0, "subt", ariDasm }, 1080 { DCOR, 0, "dcor", unitDasm }, 1081 { IDCOR, 0, "idcor", unitDasm }, 1082 { ADDIO, 0, "addio", iaDasm }, 1083 { SUBIO, 0, "subio", iaDasm }, 1084 { ADDI, 0, "addi", iaDasm }, 1085 { SUBI, 0, "subi", iaDasm }, 1086 { COMICLR,0, "comiclr", iaDasm }, 1087 { ADDITO, 0, "addito", iaDasm }, 1088 { ADDIT, 0, "addit", iaDasm }, 1089 { SHD, 0, "shd", shdDasm }, 1090 { VSHD, 0, "vshd", shdDasm }, 1091 { EXTRU, 0, "extru", extrDasm }, 1092 { EXTRS, 0, "extrs", extrDasm }, 1093 { VEXTRU, 0, "vextru", vextrDasm }, 1094 { VEXTRS, 0, "vextrs", vextrDasm }, 1095 { DEP, 0, "dep", depDasm }, 1096 { VDEP, 0, "vdep", vdepDasm }, 1097 { DEPI, 0, "depi", depiDasm }, 1098 { VDEPI, 0, "vdepi", vdepiDasm }, 1099 { ZDEP, 0, "zdep", depDasm }, 1100 { ZVDEP, 0, "zvdep", vdepDasm }, 1101 { ZDEPI, 0, "zdepi", depiDasm }, 1102 { ZVDEPI, 0, "zvdepi", vdepiDasm }, 1103 { BREAK, 0, "break", brkDasm }, 1104 { RFI, 0, "rfi", 0 }, 1105 { RFIR, 0, "rfir", 0 }, 1106 { SSM, 0, "ssm", scDasm }, 1107 { RSM, 0, "rsm", scDasm }, 1108 { MTSM, 0, "mtsm", scDasm }, 1109 { PROBER, 0, "prober", mmgtDasm }, 1110 { PROBEW, 0, "probew", mmgtDasm }, 1111 { LPA, 0, "lpa", mmgtDasm }, 1112 { LHA, 0, "lha", mmgtDasm }, 1113 { LDSID, 0, "ldsid", scDasm }, 1114 { PDTLB, 0, "pdtlb", mmgtDasm }, 1115 { PDTLBE, 0, "pdtlbe", mmgtDasm }, 1116 { PITLB, 0, "pitlb", mmgtDasm }, 1117 { PITLBE, 0, "pitlbe", mmgtDasm }, 1118 { IDTLBA, 0, "idtlba", mmgtDasm }, 1119 { IITLBA, 0, "iitlba", mmgtDasm }, 1120 { IDTLBP, 0, "idtlbp", mmgtDasm }, 1121 { IITLBP, 0, "iitlbp", mmgtDasm }, 1122 { FIC, 0, "fic", mmgtDasm }, 1123 { FICE, 0, "fice", mmgtDasm }, 1124 { PDC, 0, "pdc", mmgtDasm }, 1125 { FDC, 0, "fdc", mmgtDasm }, 1126 { FDCE, 0, "fdce", mmgtDasm }, 1127 { SYNC, 0, "sync", 0 }, 1128 { MTSP, 0, "mtsp", scDasm }, 1129 { MTCTL, 0, "mtctl", scDasm }, 1130 { MFSP, 0, "mfsp", scDasm }, 1131 { MFCTL, 0, "mfctl", scDasm }, 1132 { DIAG, 0, "diag", diagDasm }, 1133 { SPOP, 0, "???", 0 }, 1134 { COPR, 0, "copr", coprDasm }, 1135 { CLDWX, 0, "cldw", coprDasm }, 1136 { CLDDX, 0, "cldd", coprDasm }, 1137 { CSTWX, 0, "cstw", coprDasm }, 1138 { CSTDX, 0, "cstd", coprDasm }, 1139 { CLDWS, 0, "cldw", coprDasm }, 1140 { CLDDS, 0, "cldd", coprDasm }, 1141 { CSTWS, 0, "cstw", coprDasm }, 1142 { CSTDS, 0, "cstd", coprDasm }, 1143 { FLOAT0, 0, "f", floatDasm }, 1144 { FLOAT1, 0, "fcnv", floatDasm }, 1145 { FLOAT2, 0, "f", floatDasm }, 1146 { FLOAT3, 0, "f", floatDasm }, 1147 { FMPYSUB,0, "fmpy", fmpysubDasm }, 1148 { FMPYADD,0, "fmpy", fmpyaddDasm }, 1149 { FSTQX, 0, "fstqx", lpkDasm }, 1150 { FSTQS, 0, "fstqs", lpkDasm }, 1151 {0} 1152 }; 1153 1154 1155 static const struct inst illeg = { 0, 0, 0, 0, 0, "???", 0 }; 1156 static const struct inst *so_sysop[0xd0]; 1157 static const struct inst *so_mmuop[0x50]; 1158 static const struct inst *so_arith[0x80]; 1159 static const struct inst *so_loads[0x50]; 1160 static const struct inst *so_cldw [0x0A]; 1161 static const struct inst *so_cldd [0x0A]; 1162 static const struct inst *so_float[0x04]; 1163 static const struct inst *so_fstq [0x0A]; 1164 static const struct inst *so_ebran[0x08]; 1165 static const struct inst *so_addit[0x02]; 1166 static const struct inst *so_addi [0x02]; 1167 static const struct inst *so_subi [0x02]; 1168 static const struct inst *so_shext[0x08]; 1169 static const struct inst *so_deps [0x08]; 1170 1171 #define ILLEG (const struct inst **)&illeg 1172 #define NENTS(a) (sizeof(a)/sizeof(a[0])-1) 1173 static struct majoropcode majopcs[NMAJOPCS] = { 1174 { so_sysop, NENTS(so_sysop) }, /* 00 */ 1175 { so_mmuop, NENTS(so_mmuop) }, /* 01 */ 1176 { so_arith, NENTS(so_arith) }, /* 02 */ 1177 { so_loads, NENTS(so_loads) }, /* 03 */ 1178 { ILLEG, 1 }, /* 04 */ 1179 { ILLEG, 1 }, /* 05 */ 1180 { ILLEG, 1 }, /* 06 */ 1181 { ILLEG, 1 }, /* 07 */ 1182 { ILLEG, 1 }, /* 08 */ 1183 { so_cldw , NENTS(so_cldw ) }, /* 09 */ 1184 { ILLEG, 1 }, /* 0A */ 1185 { so_cldd , NENTS(so_cldd ) }, /* 0B */ 1186 { ILLEG, 1 }, /* 0C */ 1187 { ILLEG, 1 }, /* 0D */ 1188 { so_float, NENTS(so_float) }, /* 0E */ 1189 { so_fstq , NENTS(so_fstq ) }, /* 0F */ 1190 { ILLEG, 1 }, /* 10 */ 1191 { ILLEG, 1 }, /* 11 */ 1192 { ILLEG, 1 }, /* 12 */ 1193 { ILLEG, 1 }, /* 13 */ 1194 { ILLEG, 1 }, /* 14 */ 1195 { ILLEG, 1 }, /* 15 */ 1196 { ILLEG, 1 }, /* 16 */ 1197 { ILLEG, 1 }, /* 17 */ 1198 { ILLEG, 1 }, /* 18 */ 1199 { ILLEG, 1 }, /* 19 */ 1200 { ILLEG, 1 }, /* 1A */ 1201 { ILLEG, 1 }, /* 1B */ 1202 { ILLEG, 1 }, /* 1C */ 1203 { ILLEG, 1 }, /* 1D */ 1204 { ILLEG, 1 }, /* 1E */ 1205 { ILLEG, 1 }, /* 1F */ 1206 { ILLEG, 1 }, /* 20 */ 1207 { ILLEG, 1 }, /* 21 */ 1208 { ILLEG, 1 }, /* 22 */ 1209 { ILLEG, 1 }, /* 23 */ 1210 { ILLEG, 1 }, /* 24 */ 1211 { so_subi , NENTS(so_subi ) }, /* 25 */ 1212 { ILLEG, 1 }, /* 26 */ 1213 { ILLEG, 1 }, /* 27 */ 1214 { ILLEG, 1 }, /* 28 */ 1215 { ILLEG, 1 }, /* 29 */ 1216 { ILLEG, 1 }, /* 2A */ 1217 { ILLEG, 1 }, /* 2B */ 1218 { so_addit, NENTS(so_addit) }, /* 2C */ 1219 { so_addi , NENTS(so_addi ) }, /* 2D */ 1220 { ILLEG, 1 }, /* 2E */ 1221 { ILLEG, 1 }, /* 2F */ 1222 { ILLEG, 1 }, /* 30 */ 1223 { ILLEG, 1 }, /* 31 */ 1224 { ILLEG, 1 }, /* 32 */ 1225 { ILLEG, 1 }, /* 33 */ 1226 { so_shext, NENTS(so_shext) }, /* 34 */ 1227 { so_deps , NENTS(so_deps ) }, /* 35 */ 1228 { ILLEG, 1 }, /* 36 */ 1229 { ILLEG, 1 }, /* 37 */ 1230 { ILLEG, 1 }, /* 38 */ 1231 { ILLEG, 1 }, /* 39 */ 1232 { so_ebran, NENTS(so_ebran) }, /* 3A */ 1233 { ILLEG, 1 }, /* 3B */ 1234 { ILLEG, 1 }, /* 3C */ 1235 { ILLEG, 1 }, /* 3D */ 1236 { ILLEG, 1 }, /* 3E */ 1237 { ILLEG, 1 }, /* 3F */ 1238 }; 1239 #undef NENTS 1240 #undef ILLEG 1241 1242 /*-------------------------------------------------------------------------- 1243 * instruction$ExecutionInitialize - Initialize the instruction execution 1244 * data structures. 1245 *---------------------------------------------------------------------------*/ 1246 static int iExInit __P((void)); 1247 static int 1248 iExInit(void) 1249 { 1250 static int unasm_initted = 0; 1251 const struct inst *i; 1252 struct majoropcode *m; 1253 u_int shft, mask; 1254 1255 if (unasm_initted) 1256 return 0; 1257 1258 /* 1259 * Determine maxsubop for each major opcode. 1260 * Also, check all instructions of a given major opcode 1261 * for consistent opcode extension field definition, and 1262 * save a converted form of this definition in the majopcs 1263 * entry for this major opcode. 1264 */ 1265 for (i = &instrs[0]; *i->mnem; i++) { 1266 m = &majopcs[i->majopc]; 1267 if (m->maxsubop < i->opcext) 1268 panic("iExInit not enough space for opcode %d", 1269 i->majopc); 1270 shft = 32 - i->extbs - i->extbl; 1271 mask = (1 << i->extbl) - 1; 1272 if (m->extshft || m->extmask) { 1273 if (m->extshft != shft || m->extmask != mask) { 1274 db_printf("%s - Bad instruction initialization!\n", i->mnem); 1275 return (0); 1276 } 1277 } else { 1278 m->extshft = shft; 1279 m->extmask = mask; 1280 } 1281 } 1282 1283 /* 1284 * Lastly, fill in all legal subops with the appropriate info. 1285 */ 1286 for (i = &instrs[0]; *i->mnem; i++) { 1287 m = &majopcs[i->majopc]; 1288 if (m->maxsubop == 1) 1289 m->subops = (const struct inst **)i; 1290 else 1291 m->subops[i->opcext] = i; 1292 } 1293 1294 unasm_initted++; 1295 return (1); 1296 } 1297 1298 1299 1300 /*##################### Functions and Subroutines ##########################*/ 1301 1302 /**************************************/ 1303 /* Miscellaneous Disassembly Routines */ 1304 /**************************************/ 1305 1306 /* Add instructions */ 1307 int 1308 addDasm(i, ofs, w) 1309 const struct inst *i; 1310 OFS ofs; 1311 int w; 1312 { 1313 db_printf("%s\t%%r%d,%%r%d,%%r%d",addDCond(Cond4(w)), 1314 Rsa(w),Rsb(w),Rtc(w)); 1315 return (1); 1316 } 1317 1318 /* Unit instructions */ 1319 int 1320 unitDasm(i, ofs, w) 1321 const struct inst *i; 1322 OFS ofs; 1323 int w; 1324 { 1325 db_printf(unitDCond(Cond4(w))); 1326 if (Match("dcor") || Match("idcor")) 1327 db_printf("\t%%r%d,%%r%d",Rsb(w),Rtc(w)); 1328 else 1329 db_printf("\t%%r%d,%%r%d,%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1330 return (1); 1331 } 1332 1333 /* Immediate Arithmetic instructions */ 1334 int 1335 iaDasm(i, ofs, w) 1336 const struct inst *i; 1337 OFS ofs; 1338 int w; 1339 { 1340 if (Match("addi")) 1341 db_printf("%s\t%d,%%r%d,%%r%d", 1342 addDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1343 else 1344 db_printf("%s\t%d,%%r%d,%%r%d", 1345 subDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1346 return (1); 1347 } 1348 1349 /* Shift double instructions */ 1350 int 1351 shdDasm(i, ofs, w) 1352 const struct inst *i; 1353 OFS ofs; 1354 int w; 1355 { 1356 if (Match("vshd")) 1357 db_printf("%s\t%%r%d,%%r%d,%%r%d", 1358 edDCond(Cond(w)), Rsa(w),Rsb(w),Rtc(w)); 1359 else 1360 db_printf("%s\t%%r%d,%%r%d,%d,%%r%d", 1361 edDCond(Cond(w)),Rsa(w),Rsb(w),31-Imd5(w),Rtc(w)); 1362 return (1); 1363 } 1364 1365 /* Extract instructions */ 1366 int 1367 extrDasm(i, ofs, w) 1368 const struct inst *i; 1369 OFS ofs; 1370 int w; 1371 { 1372 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1373 edDCond(Cond(w)),Rsb(w),Imd5(w),32 - Rsc(w),Rta(w)); 1374 return (1); 1375 } 1376 1377 1378 /* Variable extract instructions */ 1379 int 1380 vextrDasm(i, ofs, w) 1381 const struct inst *i; 1382 OFS ofs; 1383 int w; 1384 { 1385 db_printf("%s\t%%r%d,%d,%%r%d", 1386 edDCond(Cond(w)),Rsb(w),32 - Rsc(w),Rta(w)); 1387 return (1); 1388 } 1389 1390 1391 /* Deposit instructions */ 1392 int 1393 depDasm(i, ofs, w) 1394 const struct inst *i; 1395 OFS ofs; 1396 int w; 1397 { 1398 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1399 edDCond(Cond(w)),Rsa(w),31 - Imd5(w),32 - Rsc(w),Rtb(w)); 1400 return (1); 1401 } 1402 1403 1404 /* Variable deposit instructions */ 1405 int 1406 vdepDasm(i, ofs, w) 1407 const struct inst *i; 1408 OFS ofs; 1409 int w; 1410 { 1411 db_printf("%s\t%%r%d,%d,%%r%d", 1412 edDCond(Cond(w)),Rsa(w),32 - Rsc(w),Rtb(w)); 1413 return (1); 1414 } 1415 1416 1417 /* Deposit Immediate instructions */ 1418 int 1419 depiDasm(i, ofs, w) 1420 const struct inst *i; 1421 OFS ofs; 1422 int w; 1423 { 1424 db_printf("%s\t%d,%d,%d,%%r%d", 1425 edDCond(Cond(w)),Ima5(w),31 - Imd5(w),32 - Imc5A(w),Rtb(w)); 1426 return (1); 1427 } 1428 1429 /* Variable Deposit Immediate instructions */ 1430 int 1431 vdepiDasm(i, ofs, w) 1432 const struct inst *i; 1433 OFS ofs; 1434 int w; 1435 { 1436 db_printf("%s\t%d,%d,%%r%d",edDCond(Cond(w)),Ima5(w),32-Imc5A(w),Rtb(w)); 1437 return (1); 1438 } 1439 1440 /*--------------------------------------------------------------------------- 1441 * conditionType$DisassembleCondition - Return a string which contains the 1442 * ascii description of the passed numeric condition. 1443 *---------------------------------------------------------------------------*/ 1444 1445 char * 1446 subDCond(cond) 1447 u_int cond; 1448 { 1449 switch(cond) { 1450 case EQZ: return(",="); 1451 case LT: return(",<"); 1452 case LE: return(",<="); 1453 case LLT: return(",<<"); 1454 case LLE: return(",<<="); 1455 case SV: return(",sv"); 1456 case OD: return(",od"); 1457 case NEQZ: return(",<>"); 1458 case GE: return(",>="); 1459 case GT: return(",>"); 1460 case LGE: return(",>>="); 1461 case LGT: return(",>>"); 1462 case NSV: return(",nsv"); 1463 case EV: return(",ev"); 1464 case TR: return(",tr"); 1465 case NEV: return(""); 1466 default: 1467 panic("subDCond: unknown condition"); 1468 } 1469 } 1470 1471 1472 /*--------------------------------------------------------------------------- 1473 * conditionType$DisassembleCondition - Return a string which contains the 1474 * ascii description of the passed numeric condition. 1475 *---------------------------------------------------------------------------*/ 1476 1477 char * 1478 addDCond(cond) 1479 u_int cond; 1480 { 1481 switch(cond) { 1482 case EQZ: return(",="); 1483 case LT: return(",<"); 1484 case LE: return(",<="); 1485 case NUV: return(",nuv"); 1486 case ZNV: return(",znv"); 1487 case SV: return(",sv"); 1488 case OD: return(",od"); 1489 case NEQZ: return(",<>"); 1490 case GE: return(",>="); 1491 case GT: return(",>"); 1492 case UV: return(",uv"); 1493 case VNZ: return(",vnz"); 1494 case NSV: return(",nsv"); 1495 case EV: return(",ev"); 1496 case TR: return(",tr"); 1497 case NEV: return(""); 1498 default: 1499 panic("addDCond: unknown condition"); 1500 } 1501 } 1502 1503 char * 1504 unitDCond(cond) 1505 u_int cond; 1506 { 1507 switch(cond) { 1508 case SHC: return(",shc"); 1509 case SHZ: return(",shz"); 1510 case SBC: return(",sbc"); 1511 case SBZ: return(",sbz"); 1512 case SDC: return(",sdc"); 1513 case NHC: return(",nhc"); 1514 case NHZ: return(",nhz"); 1515 case NBC: return(",nbc"); 1516 case NBZ: return(",nbz"); 1517 case NDC: return(",ndc"); 1518 case TR: return(",tr"); 1519 case NEV: return(""); 1520 default: 1521 panic("unitDCond: unknown condition"); 1522 } 1523 } 1524 1525 char * 1526 edDCond(cond) 1527 u_int cond; 1528 { 1529 switch(cond) { 1530 case XOD: return(",od"); 1531 case XTR: return(",tr"); 1532 case XNE: return(",<>"); 1533 case XLT: return(",<"); 1534 case XEQ: return(",="); 1535 case XGE: return(",>="); 1536 case XEV: return(",ev"); 1537 case NEV: return(""); 1538 default: 1539 panic("edDCond: unknown condition"); 1540 } 1541 } 1542 1543 1544 1545 /****************************************/ 1546 /* Format Specific Disassembly Routines */ 1547 /****************************************/ 1548 1549 1550 /* Load [modify] instructions */ 1551 int 1552 ldDasm(i, ofs, w) 1553 const struct inst *i; 1554 OFS ofs; 1555 int w; 1556 { 1557 int d = Disp(w); 1558 char s[2]; 1559 1560 s[1] = '\0'; 1561 if (d < 0) { 1562 d = -d; 1563 s[0] = '-'; 1564 } else 1565 s[0] = '\0'; 1566 1567 if (Rsb(w) == 0 && Match("ldo")) { 1568 db_printf("ldi\t%s%X,%%r%d",s,d,Rta(w)); 1569 return (1); 1570 } 1571 db_printf("%s\t%s%s%X",i->mnem,(d < 2048? "R'":""), s, d); 1572 if (Dss(w)) 1573 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rta(w)); 1574 else 1575 db_printf("(%%r%d),%%r%d",Rsb(w),Rta(w)); 1576 return (1); 1577 } 1578 1579 /* Store [modify] instructions */ 1580 int 1581 stDasm(i, ofs, w) 1582 const struct inst *i; 1583 OFS ofs; 1584 int w; 1585 { 1586 int d = Disp(w); 1587 char s[2]; 1588 1589 db_printf("\t%%r%d,",Rta(w)); 1590 1591 s[1] = '\0'; 1592 if (d < 0) { 1593 d = -d; 1594 s[0] = '-'; 1595 } else 1596 s[0] = '\0'; 1597 1598 db_printf("%s%s%X", (d < 2048? "R'":""), s, d); 1599 1600 if (Dss(w)) 1601 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 1602 else 1603 db_printf("(%%r%d)",Rsb(w)); 1604 return (1); 1605 } 1606 1607 /* Load indexed instructions */ 1608 int 1609 ldxDasm(i, ofs, w) 1610 const struct inst *i; 1611 OFS ofs; 1612 int w; 1613 { 1614 const char *p; 1615 1616 if (ShortDisp(w)) { 1617 db_printf("s"); 1618 if (Modify(w)) 1619 db_printf(",m%s", ModBefore(w)? "b": "a"); 1620 } else { 1621 db_printf("x"); 1622 if (Modify(w)) 1623 db_printf(",%sm", IndxShft(w)? "s":""); 1624 } 1625 switch (CacheCtrl(w)) { 1626 case NOACTION: p = ""; break; 1627 case STACKREF: p = ",c"; break; 1628 case SEQPASS: p = ",q"; break; 1629 case PREFETCH: p = ",p"; break; 1630 } 1631 if (ShortDisp(w)) 1632 db_printf("%s\t%d", p, Ima5(w)); 1633 else 1634 db_printf("%s\t%%r%d", p, Rsa(w)); 1635 1636 if (Dss(w)) 1637 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1638 else 1639 db_printf("(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1640 return (1); 1641 } 1642 1643 /* Store short displacement instructions */ 1644 int 1645 stsDasm(i, ofs, w) 1646 const struct inst *i; 1647 OFS ofs; 1648 int w; 1649 { 1650 const char *p; 1651 if (Modify(w)) 1652 db_printf(",m%s", ModBefore(w)? "b":"a"); 1653 1654 switch (CacheCtrl(w)) { 1655 case NOACTION: p = ""; break; 1656 case STACKREF: p = ",c"; break; 1657 case SEQPASS: p = ",q"; break; 1658 case PREFETCH: p = ",p"; break; 1659 } 1660 db_printf("%s\t%%r%d,", p, Rta(w)); 1661 if (Dss(w)) 1662 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1663 else 1664 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1665 return (1); 1666 } 1667 1668 /* Store Bytes Instruction */ 1669 int 1670 stbysDasm(i, ofs, w) 1671 const struct inst *i; 1672 OFS ofs; 1673 int w; 1674 { 1675 const char *p; 1676 db_printf(ModBefore(w)? ",e":",b"); 1677 if (Modify(w)) 1678 db_printf(",m"); 1679 switch (CacheCtrl(w)) { 1680 case NOACTION: p = ""; break; 1681 case STACKREF: p = ",f"; break; 1682 case SEQPASS: p = ",r"; break; 1683 case PREFETCH: p = ",z"; break; 1684 } 1685 db_printf("%s\t%%r%d,", p, Rta(w)); 1686 if (Dss(w)) 1687 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1688 else 1689 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1690 return (1); 1691 } 1692 1693 /* Long Immediate instructions */ 1694 int 1695 limmDasm(i, ofs, w) 1696 const struct inst *i; 1697 OFS ofs; 1698 int w; 1699 { 1700 db_printf("\tL'%X,%%r%d", Im21(w), Rtb(w)); 1701 return (1); 1702 } 1703 1704 1705 /* Branch and Link instruction(s) (Branch, too!!) */ 1706 int 1707 blDasm(i, ofs, w) 1708 const struct inst *i; 1709 OFS ofs; 1710 int w; 1711 { 1712 OFS tgtofs = ofs + 8 + Bdisp(w); 1713 u_int link = Rtb(w); 1714 1715 if (link && !Match("gate")) 1716 db_printf("l"); 1717 if (Nu(w)) 1718 db_printf(",n"); 1719 db_printf("\t"); 1720 1721 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1722 1723 if (link || Match("gate")) 1724 db_printf(",%%r%d",link); 1725 1726 return (1); 1727 } 1728 1729 /* Branch Register instruction */ 1730 int 1731 brDasm(i, ofs, w) 1732 const struct inst *i; 1733 OFS ofs; 1734 int w; 1735 { 1736 db_printf("%s\t%%r%d,%%r%d", Nu(w)?",n":"", Rsa(w), Rtb(w)); 1737 return (1); 1738 } 1739 1740 /* Dispatch instructions */ 1741 int 1742 bvDasm(i, ofs, w) 1743 const struct inst *i; 1744 OFS ofs; 1745 int w; 1746 { 1747 db_printf("%s\t%%r%d(%%r%d)", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1748 return (1); 1749 } 1750 1751 /* Branch External instructions */ 1752 int 1753 beDasm(i, ofs, w) 1754 const struct inst *i; 1755 OFS ofs; 1756 int w; 1757 { 1758 int d = Bdisp(w); 1759 const char *p; 1760 char s[2]; 1761 1762 s[1] = '\0'; 1763 if (d < 0) { 1764 d = -d; 1765 s[0] = '-'; 1766 } else 1767 s[0] = '\0'; 1768 1769 p = Nu(w)? ",n":""; 1770 db_printf("%s\tR'%s%X(%%sr%d,%%r%d)", p, 1771 s, d, Sr(w), Rsb(w)); 1772 return (1); 1773 } 1774 1775 1776 /* Compare/Add and Branch instructions */ 1777 int 1778 cbDasm(i, ofs, w) 1779 const struct inst *i; 1780 OFS ofs; 1781 int w; 1782 { 1783 OFS tgtofs = ofs + 8 + Cbdisp(w); 1784 1785 if (Match("movb")) 1786 db_printf(edDCond(Cond(w))); 1787 else if (Match("addb")) 1788 db_printf(addDCond(Cond(w) << 1)); 1789 else 1790 db_printf(subDCond(Cond(w) << 1)); 1791 db_printf("%s\t%%r%d,%%r%d,", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1792 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1793 return (1); 1794 } 1795 1796 /* Compare/Add and Branch Immediate instructions */ 1797 int 1798 cbiDasm(i, ofs, w) 1799 const struct inst *i; 1800 OFS ofs; 1801 int w; 1802 { 1803 OFS tgtofs = ofs + 8 + Cbdisp(w); 1804 1805 if (Match("movib")) 1806 db_printf(edDCond(Cond(w))); 1807 else if (Match("addib")) 1808 db_printf(addDCond(Cond(w) << 1)); 1809 else 1810 db_printf(subDCond(Cond(w) << 1)); 1811 db_printf("%s\t%d,%%r%d,", Nu(w)? ",n":"", Ima5(w), Rsb(w)); 1812 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1813 return (1); 1814 } 1815 1816 /* Branch on Bit instructions */ 1817 int 1818 bbDasm(i, ofs, w) 1819 const struct inst *i; 1820 OFS ofs; 1821 int w; 1822 { 1823 OFS tgtofs = ofs + 8 + Cbdisp(w); 1824 const char *p; 1825 1826 db_printf(edDCond(Cond(w))); 1827 p = Nu(w)? ",n":""; 1828 if (Match("bvb")) 1829 db_printf("%s\t%%r%d,", p, Rta(w)); 1830 else 1831 db_printf("%s\t%%r%d,%d,", p, Rsa(w), Imb5(w)); 1832 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1833 return (1); 1834 } 1835 1836 /* Arithmetic instructions */ 1837 int 1838 ariDasm(i, ofs, w) 1839 const struct inst *i; 1840 OFS ofs; 1841 int w; 1842 { 1843 if (Match("or") && Rsb(w) == 0 && Cond4(w) == NEV) { 1844 if (Rsa(w) == 0 && Rtc(w) == 0) 1845 db_printf("nop"); 1846 else 1847 db_printf("copy\t%%r%d,%%r%d",Rsa(w),Rtc(w)); 1848 } else 1849 db_printf("%s%s\t%%r%d,%%r%d,%%r%d", i->mnem, 1850 subDCond(Cond4(w)), Rsa(w),Rsb(w),Rtc(w)); 1851 return(1); 1852 } 1853 1854 /* System control operations */ 1855 int 1856 scDasm(i, ofs, w) 1857 const struct inst *i; 1858 OFS ofs; 1859 int w; 1860 { 1861 if (Match("mtctl")) { 1862 if (Rtb(w) == 11) 1863 db_printf("mtsar\t%%r%d",Rsa(w)); 1864 else 1865 db_printf("mtctl\t%%r%d,%%cr%d",Rsa(w),Rtb(w)); 1866 return (1); 1867 } 1868 db_printf(i->mnem); 1869 if (Match("ssm") || Match("rsm")) 1870 db_printf("\t%d,%%r%d",Ima5A(w),Rtc(w)); 1871 else if (Match("mtsm")) db_printf("\t%%r%d",Rsa(w)); 1872 else if (Match("ldprid")) db_printf("\t%%r%d",Rtc(w)); 1873 else if (Match("mtsp")) db_printf("\t%%r%d,%%sr%d",Rsa(w),Sr(w)); 1874 else if (Match("mfsp")) db_printf("\t%%sr%d,%%r%d",Sr(w),Rtc(w)); 1875 else if (Match("mfctl")) db_printf("\t%%cr%d,%%r%d",Rsb(w),Rtc(w)); 1876 else if (Match("ldsid")) { 1877 if (Dss(w)) 1878 db_printf("\t(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1879 else 1880 db_printf("\t(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1881 } else { 1882 db_printf("?????"); 1883 return (0); 1884 } 1885 return (1); 1886 } 1887 1888 /* Instruction cache/tlb control instructions */ 1889 int 1890 mmgtDasm(i, ofs, w) 1891 const struct inst *i; 1892 OFS ofs; 1893 int w; 1894 { 1895 if (Match("probe")) { 1896 if (ProbeI(w)) { 1897 if (Dss(w)) 1898 db_printf("i\t(%%sr%d,%%r%d),%d,%%r%d", 1899 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1900 else 1901 db_printf("i\t(%%r%d),%d,%%r%d", 1902 Rsb(w),Rsa(w),Rtc(w)); 1903 } else { 1904 if (Dss(w)) 1905 db_printf("\t(%%sr%d,%%r%d),%%r%d,%%r%d", 1906 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1907 else 1908 db_printf("\t(%%r%d),%%r%d,%%r%d", 1909 Rsb(w),Rsa(w),Rtc(w)); 1910 } 1911 } 1912 else if (Match("lha") || Match("lpa")) { 1913 if (Modify(w)) 1914 db_printf(",m"); 1915 if (Dss(w)) 1916 db_printf("\t%%r%d(%%sr%d,%%r%d),%%r%d", 1917 Rsa(w),Dss(w),Rsb(w),Rtc(w)); 1918 else 1919 db_printf("\t%%r%d(%%r%d),%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1920 } 1921 else if (Match("pdtlb") || Match("pdc") || Match("fdc")) { 1922 if (Modify(w)) db_printf(",m"); 1923 if (Dss(w)) 1924 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1925 else 1926 db_printf("\t%%r%d(%%r%d)",Rsa(w),Rsb(w)); 1927 } 1928 else if (Match("pitlb") || Match("fic")) { 1929 if (Modify(w)) 1930 db_printf(",m"); 1931 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1932 } 1933 else if (Match("idtlb")) { 1934 if (Dss(w)) 1935 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1936 else 1937 db_printf("\t%%r%d,(%%r%d)",Rsa(w),Rsb(w)); 1938 } 1939 else if (Match("iitlb")) 1940 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1941 else { 1942 db_printf("?????"); 1943 return (0); 1944 } 1945 return(1); 1946 } 1947 1948 /* break instruction */ 1949 int 1950 brkDasm(i, ofs, w) 1951 const struct inst *i; 1952 OFS ofs; 1953 int w; 1954 { 1955 db_printf("\t%d,%d",Bi1(w),Bi2(w)); 1956 return (1); 1957 } 1958 1959 int 1960 floatDasm(i, ofs, w) 1961 const struct inst *i; 1962 OFS ofs; 1963 int w; 1964 { 1965 u_int op1, r1, fmt, t; 1966 u_int op2, r2, dfmt; 1967 char *p; 1968 1969 op1 = CoprExt1(w); 1970 op2 = CoprExt2(w); 1971 fmt = (op1 >> 2) & 3; /* get precision of source */ 1972 1973 #define ST(r) ((fmt & 1)? fdreg[(r)]:fsreg[(r)]) 1974 /* 1975 * get first (or only) source register 1976 * (independent of class) 1977 */ 1978 r1 = (op1 >> 11) & 0x3e; 1979 if ((fmt & 1) == 0 && (Uid(w) & 2)) 1980 r1++; 1981 1982 if (op1 & 2) { /* class 2 or 3 */ 1983 /* 1984 * get second source register 1985 */ 1986 r2 = (op1 >> 6) & 0x3e; 1987 if (fmt == 2) 1988 r2++; 1989 1990 if ((op1 & 1) == 0) { /* class 2 */ 1991 /* Opclass 2: 2 sources, no destination */ 1992 switch((op1 >> 4) & 7) { 1993 case 0: 1994 p = "cmp"; 1995 break; 1996 default: 1997 db_printf(fcoprUndef); 1998 return(0); 1999 } 2000 db_printf("%s,%s",p,fmtStrTbl[fmt]); 2001 db_printf(",%s\t%%f%s,%%f%s", 2002 condStrTbl[op2], ST(r1), ST(r2)); 2003 return (1); 2004 } 2005 /* 2006 * get target register (class 3) 2007 */ 2008 t = (op2 << 1); 2009 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2010 t++; 2011 /* Opclass 3: 2 sources, 1 destination */ 2012 switch((op1 >> 4) & 7) { 2013 case 0: p = "add"; break; 2014 case 1: p = "sub"; break; 2015 case 2: p = (Fpi(w)) ? "mpyi" : "mpy"; break; 2016 case 3: p = "div"; break; 2017 case 4: p = "rem"; break; 2018 default: db_printf(fcoprUndef); return (0); 2019 } 2020 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2021 db_printf("\t%%f%s,%%f%s,%%f%s",ST(r1),ST(r2),ST(t)); 2022 } else if (op1 & 1) { /* class 1 */ 2023 dfmt = (op1 >> 4) & 3; 2024 #define DT(r) ((dfmt & 1)? fdreg[(r)]:fsreg[(r)]) 2025 2026 /* 2027 * get target register 2028 */ 2029 t = (op2 << 1); 2030 if ((dfmt & 1) == 0 && (Uid(w) & 1)) 2031 t++; 2032 /* Opclass 1: 1 source, 1 destination conversions */ 2033 switch((op1 >> 6) & 3) { 2034 case 0: p = "ff"; break; 2035 case 1: p = "xf"; break; 2036 case 2: p = "fx"; break; 2037 case 3: p = "fxt"; break; 2038 } 2039 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2040 db_printf(",%s\t%%f%s,%%f%s",fmtStrTbl[dfmt],ST(r1),DT(t)); 2041 } else { /* class 0 */ 2042 /* 2043 * get target register 2044 */ 2045 t = (op2 << 1); 2046 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2047 t++; 2048 /* Opclass 0: 1 source, 1 destination */ 2049 switch((op1 >> 4) & 7) { 2050 case 1: p = "rsqrt"; break; 2051 case 2: p = "cpy"; break; 2052 case 3: p = "abs"; break; 2053 case 4: p = "sqrt"; break; 2054 case 5: p = "rnd"; break; 2055 default: db_printf(fcoprUndef); return (0); 2056 } 2057 db_printf("%s,%s",p,fmtStrTbl[fmt]); 2058 db_printf("\t%%f%s,%%f%s",ST(r1),ST(t)); 2059 } 2060 return (1); 2061 } 2062 2063 int 2064 fcoprDasm(w, op1, op2) 2065 int w; 2066 u_int op1, op2; 2067 { 2068 u_int r1, r2, t, fmt, dfmt; 2069 char *p; 2070 2071 if (AstNu(w) && op1 == ((1<<4) | 2)) { 2072 if (op2 == 0 || op2 == 1 || op2 == 2) { 2073 db_printf("ftest"); 2074 if (op2 == 1) 2075 db_printf(",acc"); 2076 else if (op2 == 2) 2077 db_printf(",rej"); 2078 return (1); 2079 } 2080 return (0); 2081 } else if (0 == op1 && 0 == op2) { 2082 db_printf("fcopr identify"); 2083 return (1); 2084 } 2085 switch(op1 & 3) { 2086 case 0: 2087 /* Opclass 0: 1 source, 1 destination */ 2088 r1 = (op1 >> 12) & 0x1f; t = op2; fmt = (op1 >> 2) & 3; 2089 switch((op1 >> 4) & 7) { 2090 case 1: p = "rsqrt"; break; 2091 case 2: p = "cpy"; break; 2092 case 3: p = "abs"; break; 2093 case 4: p = "sqrt"; break; 2094 case 5: p = "rnd"; break; 2095 default: db_printf(fcoprUndef); return(0); 2096 } 2097 db_printf("f%s,%s\t%%fr%d,%%fr%d", p, fmtStrTbl[fmt], r1, t); 2098 break; 2099 case 1: 2100 /* Opclass 1: 1 source, 1 destination conversions */ 2101 r1 = (op1 >> 12) & 0x1f; t = op2; 2102 fmt = (op1 >> 2) & 3; dfmt = (op1 >> 4) & 3; 2103 switch((op1 >> 6) & 3) { 2104 case 0: p = "ff"; break; 2105 case 1: p = "xf"; break; 2106 case 2: p = "fx"; break; 2107 case 3: p = "fxt"; break; 2108 } 2109 db_printf("fcnv%s,%s,%s\t%%fr%d,%%fr%d", 2110 p, fmtStrTbl[fmt], fmtStrTbl[dfmt], r1, t); 2111 break; 2112 case 2: 2113 /* Opclass 2: 2 sources, no destination */ 2114 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; 2115 fmt = (op1 >> 2) & 3; 2116 switch((op1 >> 4) & 7) { 2117 case 0: p = "fcmp"; break; 2118 default: db_printf(fcoprUndef); return (0); 2119 } 2120 db_printf("%s,%s,%s\t%%fr%d,%%fr%d", 2121 p,fmtStrTbl[fmt],condStrTbl[op2],r1,r2); 2122 break; 2123 case 3: 2124 /* Opclass 3: 2 sources, 1 destination */ 2125 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; t = op2; 2126 fmt = (op1 >> 2) & 3; 2127 switch((op1 >> 4) & 7) { 2128 case 0: p = "add"; break; 2129 case 1: p = "sub"; break; 2130 case 2: p = "mpy"; break; 2131 case 3: p = "div"; break; 2132 case 4: p = "rem"; break; 2133 default: db_printf(fcoprUndef); return (0); 2134 } 2135 db_printf("f%s,%s\t%%fr%d,%%fr%d,%%fr%d", 2136 p, fmtStrTbl[fmt], r1, r2, t); 2137 break; 2138 default: 2139 db_printf(fcoprUndef); 2140 return(0); 2141 } 2142 return (1); 2143 } 2144 2145 int 2146 coprDasm(i, ofs, w) 2147 const struct inst *i; 2148 OFS ofs; 2149 int w; 2150 { 2151 u_int uid = Uid(w); 2152 int load = 0; 2153 char *pfx = uid > 1 ? "c" : "f"; 2154 int dreg; 2155 2156 if (Match("copr")) { 2157 if (uid) { 2158 db_printf("copr,%d,0x%x",uid,CoprExt(w)); 2159 if (AstNu(w)) 2160 db_printf(",n"); 2161 return (1); 2162 } 2163 return fcoprDasm(w, CoprExt1(w),CoprExt2(w)); 2164 } 2165 if (Match("cldd")) { 2166 dreg = 1; 2167 load = 1; 2168 db_printf("%sldd",pfx); 2169 } else if (Match("cldw")) { 2170 load = 1; 2171 db_printf("%sldw",pfx); 2172 } else if (Match("cstd")) { 2173 dreg = 1; 2174 db_printf("%sstd",pfx); 2175 } else if (Match("cstw")) 2176 db_printf("%sstw",pfx); 2177 else { 2178 db_printf("copr???"); 2179 return (0); 2180 } 2181 if (ShortDisp(w)) { 2182 db_printf("s"); 2183 if (AstNu(w)) 2184 db_printf(",m%s", ModBefore(w)?"b":"a"); 2185 } 2186 else { 2187 db_printf("x"); 2188 if (AstNu(w)) 2189 db_printf(",%sm", IndxShft(w)?"s":""); 2190 else if (IndxShft(w)) 2191 db_printf(",s"); 2192 } 2193 switch (CacheCtrl(w)) { 2194 case NOACTION: break; 2195 case STACKREF: db_printf(",c"); break; 2196 case SEQPASS: db_printf(",q"); break; 2197 case PREFETCH: db_printf(",p"); break; 2198 } 2199 if (load) { 2200 const char *p; 2201 2202 if (dreg) 2203 p = fdreg[(Rtc(w)<<1)+(uid&1)]; 2204 else 2205 p = fsreg[(Rtc(w)<<1)+(uid&1)]; 2206 2207 if (ShortDisp(w)) 2208 db_printf("\t%d",Ima5(w)); 2209 else 2210 db_printf("\t%%r%d",Rsa(w)); 2211 if (Dss(w)) 2212 db_printf("(%%sr%d,%%r%d),%%f%s", Dss(w),Rsb(w), p); 2213 else 2214 db_printf("(%%r%d),%%f%s",Rsb(w), p); 2215 } else { 2216 const char *p; 2217 2218 if (dreg) 2219 p = fdreg[(Rsc(w)<<1)+(uid&1)]; 2220 else 2221 p = fsreg[(Rsc(w)<<1)+(uid&1)]; 2222 2223 if (ShortDisp(w)) 2224 db_printf("\t%%f%s,%d", p, Ima5(w)); 2225 else 2226 db_printf("\t%%f%s,%%r%d", p, Rta(w)); 2227 if (Dss(w)) 2228 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2229 else 2230 db_printf("(%%r%d)",Rsb(w)); 2231 } 2232 return (1); 2233 } 2234 2235 int 2236 lpkDasm(i, ofs, w) 2237 const struct inst *i; 2238 OFS ofs; 2239 int w; 2240 { 2241 /* 2242 * Floating point STore Quad 2243 * Short or Indexed 2244 */ 2245 if (ShortDisp(w)) { 2246 if (Modify(w)) 2247 db_printf(",m%s", ModBefore(w)?"b":"a"); 2248 } else { 2249 if (Modify(w)) 2250 db_printf(",%sm", IndxShft(w)? "s":""); 2251 else if (IndxShft(w)) 2252 db_printf(",s"); 2253 } 2254 switch (CacheCtrl(w)) { 2255 case NOACTION: break; 2256 case STACKREF: db_printf(",c"); break; 2257 case SEQPASS: db_printf(",q"); break; 2258 case PREFETCH: db_printf(",p"); break; 2259 } 2260 if (ShortDisp(w)) 2261 db_printf("\t%%fr%d,%d",Rsc(w),Ima5(w)); 2262 else 2263 db_printf("\t%%fr%d,%%r%d",Rsc(w),Rta(w)); 2264 if (Dss(w)) 2265 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2266 else 2267 db_printf("(%%r%d)",Rsb(w)); 2268 return (1); 2269 } 2270 2271 int 2272 diagDasm(i, ofs, w) 2273 const struct inst *i; 2274 OFS ofs; 2275 int w; 2276 { 2277 if (0x0b0 == BitfR(w,19,8,_b198)) /* mtcpu */ 2278 db_printf("mtcpu\t%%r%d,%%dr%d", Rsa(w), Rtb(w)); 2279 else if (0x0d0 == BitfR(w,19,8,_b198)) /* mfcpu */ 2280 db_printf("mfcpu\t%%dr%d,%%r%d", Rsb(w), Rta(w)); 2281 else { 2282 db_printf(i->mnem); 2283 if (Match("diag")) 2284 db_printf("\t0x%X",w & 0x03ffffff); 2285 else { 2286 db_printf("?????"); 2287 return (0); 2288 } 2289 } 2290 return (1); 2291 } 2292 2293 int 2294 fmpysubDasm(i, ofs, w) 2295 const struct inst *i; 2296 OFS ofs; 2297 int w; 2298 { 2299 if (SinglePrec(w)) 2300 db_printf("SUB,SGL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2301 fsreg[Ms1(w)], fsreg[Ms2(w)], fsreg[Mt(w)], 2302 fsreg[As(w)], fsreg[Ad(w)]); 2303 else 2304 db_printf("SUB,DBL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2305 fdreg[Ms1(w)], fdreg[Ms2(w)], fdreg[Mt(w)], 2306 fdreg[As(w)], fdreg[Ad(w)]); 2307 return (1); 2308 } 2309 2310 int 2311 fmpyaddDasm(i, ofs, w) 2312 const struct inst *i; 2313 OFS ofs; 2314 int w; 2315 { 2316 const char 2317 *ms1 = SinglePrec(w) ? fsreg[Ms1(w)] : fdreg[Ms1(w)], 2318 *ms2 = SinglePrec(w) ? fsreg[Ms2(w)] : fdreg[Ms2(w)], 2319 *mt = SinglePrec(w) ? fsreg[Mt(w)] : fdreg[Mt(w)], 2320 *as = SinglePrec(w) ? fsreg[As(w)] : fdreg[As(w)], 2321 *ad = SinglePrec(w) ? fsreg[Ad(w)] : fdreg[Ad(w)]; 2322 2323 if (Rsd(w) == 0) 2324 db_printf("\t%%fcfxt,%s,%%f%s,%%f%s,%%f%s", 2325 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt); 2326 else 2327 db_printf("add%s\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2328 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt, as, ad); 2329 2330 return (1); 2331 } 2332 2333 vaddr_t 2334 db_disasm(loc, flag) 2335 vaddr_t loc; 2336 boolean_t flag; 2337 { 2338 const struct inst *i; 2339 const struct majoropcode *m; 2340 u_int ext; 2341 int instruct; 2342 OFS ofs = 0; 2343 2344 iExInit(); 2345 2346 if (USERMODE(loc)) { 2347 if (copyin((caddr_t)(loc &~ HPPA_PC_PRIV_MASK), 2348 &instruct, sizeof(instruct))) 2349 instruct = 0; 2350 } else 2351 instruct = *(int *)loc; 2352 2353 m = &majopcs[Opcode(instruct)]; 2354 ext = OpExt(instruct, m); 2355 if (ext <= m->maxsubop) { 2356 /* special hack for majopcs table layout */ 2357 if (m->maxsubop == 1) 2358 i = (const struct inst *)m->subops; 2359 else 2360 i = m->subops[ext]; 2361 2362 if (i->dasmfcn != coprDasm && i->dasmfcn != diagDasm && 2363 i->dasmfcn != ariDasm && i->dasmfcn != scDasm && 2364 i->dasmfcn != ldDasm) 2365 db_printf(i->mnem); 2366 if (i->dasmfcn) 2367 (*i->dasmfcn)(i, ofs, instruct); 2368 else if (i->mnem[0] == '?') 2369 db_printf(illeg.mnem); 2370 } else 2371 db_printf(illeg.mnem); 2372 2373 db_printf("\n"); 2374 return (loc + sizeof(instruct)); 2375 } 2376
Indexes created Tue Sep 30 07:10:03 GMT 2025