db_disasm.c revision 1.4
1 /* $NetBSD: db_disasm.c,v 1.4 2003/11/01 18:23:38 matt Exp $ */ 2 3 /* $OpenBSD: db_disasm.c,v 1.9 2000/04/18 20:02:45 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Michael Shalayeff. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * (c) Copyright 1992 HEWLETT-PACKARD COMPANY 36 * 37 * To anyone who acknowledges that this file is provided "AS IS" 38 * without any express or implied warranty: 39 * permission to use, copy, modify, and distribute this file 40 * for any purpose is hereby granted without fee, provided that 41 * the above copyright notice and this notice appears in all 42 * copies, and that the name of Hewlett-Packard Company not be 43 * used in advertising or publicity pertaining to distribution 44 * of the software without specific, written prior permission. 45 * Hewlett-Packard Company makes no representations about the 46 * suitability of this software for any purpose. 47 */ 48 49 /* 50 * unasm.c -- HP_PA Instruction Printer 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.4 2003/11/01 18:23:38 matt Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 59 #include <machine/db_machdep.h> 60 #include <ddb/db_access.h> 61 #include <ddb/db_sym.h> 62 #include <ddb/db_output.h> 63 #include <ddb/db_interface.h> 64 65 66 /* IMPORTANT NOTE: 67 * All modules using this header may assume that the datatype "int" is a 68 * 32-bit (or > 32-bit) signed quantity. 69 */ 70 71 72 /* Spectrum Architecturally Defined Datatypes */ 73 struct doubleword { 74 int wd0; 75 int wd1; 76 }; 77 78 struct quadword { 79 struct doubleword d0; 80 struct doubleword d1; 81 }; 82 83 /* datatypes for halfword and byte fields of a word are defined 84 * in ssBits.h */ 85 86 /* Memory addressing datatypes */ 87 typedef unsigned int SID, /* range [0..MAXSID] */ 88 PGID, /* range [0..MAXPGID] */ 89 OFS, /* range [0..MAXINT] */ 90 REALADR; /* range [0..MAXINT] */ 91 92 93 /* data sizes */ 94 enum datasize { Byte, Halfword, Word, Doubleword, Quadword, Variable }; 95 96 /* Miscellaneous datatypes */ 97 typedef unsigned int FLAGS; 98 99 /* struct for entry in unwind table */ 100 struct ute { 101 int word1; 102 int word2; 103 int word3; 104 int word4; 105 }; 106 /* 107 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 108 * 109 * Spectrum Instruction Set Condition Completer Bit Assignments 110 * Dan Magenheimer - 6/14/82 111 * Terrence Miller - 6/21/82 112 * Computer Research Center, Hewlett-Packard Labs 113 * 114 * (c) copyright 1982 115 * (p) protected 1982 116 * The Hewlett-Packard Company 117 * Hewlett-Packard Laboratories 118 * Computer Research Center 119 * Palo Alto, California 120 * 121 * *** HP Company Confidential *** 122 * 123 * Log: unasm.c,v 124 * Revision 1.5 1994/07/21 22:32:05 mike 125 * official HP copyright notice 126 * 127 * Revision 1.4 1992/07/08 12:19:52 dalton 128 * Checkin before split to 1.0.4 release (by LBS). 129 * 130 * Revision 1.3 92/06/06 16:16:45 dalton 131 * *** empty log message *** 132 * 133 * Revision 1.2 92/06/06 15:42:28 dalton 134 * Changed include to be a path relative to hp800. 135 * 136 * Revision 1.1 92/06/06 14:05:33 dalton 137 * Initial revision 138 * 139 * Revision 1.2 91/04/14 20:29:49 osfrcs 140 * Initial version. 141 * [91/03/30 09:20:34 brezak] 142 * 143 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 144 * Initial version. 145 * [91/03/30 09:20:34 brezak] 146 * 147 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 148 * Initial version. 149 * 150 * Revision 1.1 88/07/11 14:05:15 14:05:15 ren (Bob Naas) 151 * Initial revision 152 * 153 * Revision 5.2 87/07/02 14:45:57 14:45:57 kent (Kent McMullen) 154 * added constants to support addDasm and addDCond added to ssDID.c 155 * 156 * Revision 5.1 87/02/27 11:12:08 11:12:08 kent (Kent McMullen) 157 * update all src to 5.1 158 * 159 * Revision 5.0 87/02/18 16:31:15 16:31:15 kent (Kent McMullen) 160 * update all revision numbers to 5.0 for release 161 * 162 * Revision 1.1 86/07/15 08:34:55 08:34:55 kent (Kent McMullen) 163 * Initial revision 164 * 165 * Revision 4.1 83/10/25 17:01:22 17:01:22 djm (Daniel J Magenheimer) 166 * First release for ACD v4 167 * 168 * Revision 3.0 83/06/13 10:22:59 djm (Daniel Magenheimer) 169 * First release for distribution 170 * 171 * 172 */ 173 174 175 /* Arithmetic/Logical Conditions */ 176 #define NEV 0x0 177 #define EQZ 0x2 178 #define LT 0x4 179 #define LE 0x6 180 #define LLT 0x8 181 #define NUV 0x8 182 #define LLE 0xA 183 #define ZNV 0xA 184 #define SV 0xC 185 #define OD 0xE 186 #define TR 0x1 187 #define NEQZ 0x3 188 #define GE 0x5 189 #define GT 0x7 190 #define LGE 0x9 191 #define UV 0x9 192 #define LGT 0xB 193 #define VNZ 0xB 194 #define NSV 0xD 195 #define EV 0xF 196 197 /* unit conditions */ 198 #define SBZ 0x4 199 #define SHZ 0x6 200 #define SDC 0x8 201 #define SBC 0xC 202 #define SHC 0xE 203 #define NBZ 0x5 204 #define NHZ 0x7 205 #define NDC 0x9 206 #define NBC 0xD 207 #define NHC 0xF 208 209 /*field conditions */ 210 #define XEQ 0x1 211 #define XLT 0x2 212 #define XOD 0x3 213 #define XTR 0x4 214 #define XNE 0x5 215 #define XGE 0x6 216 #define XEV 0x7 217 218 219 220 /* 221 * These macros are designed to be portable to all machines that have 222 * a wordsize greater than or equal to 32 bits that support the portable 223 * C compiler and the standard C preprocessor. Wordsize (default 32) 224 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11) 225 * should be predefined using the constants HOSTWDSZ and BITFRL and 226 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20). 227 * Note that the macro arguments assume that the integer being referenced 228 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the 229 * most significant bit. 230 */ 231 232 #ifndef HOSTWDSZ 233 #define HOSTWDSZ 32 234 #endif 235 236 #ifdef vax 237 #ifndef BITFLR 238 #define BITFRL 239 #endif 240 #else 241 #define BITFLR 242 #endif 243 244 /*########################### Macros ######################################*/ 245 246 /*--------------------------------------------------------------------------- 247 * DeclareBitfield$Reference - Declare a structure to be used to reference 248 * a specified bitfield within an integer (using BitfR, see below). 249 * The argument "n" must be an identifier name not used elsewhere in the 250 * program , "s" and "l" must (alas!) be constants. (Suggestion: if 251 * "s" == 2 and "l" == 8, use _b28 for "n".) The name "BITFLR" should 252 * be pre-defined if the compiler assigns bitfields from left-to-right. 253 * The resultant macro expansion defines a stucture in which the bit field 254 * starting at position "s" with length "l" may be referenced by accessing 255 * member "n". [Note: The leftmost bits in a 36-bit word may be accessed 256 * by specifying -4 <= s < 0 on the DEC-20.] 257 *---------------------------------------------------------------------------*/ 258 259 #ifdef BITFRL 260 #define DeclBitfR(s,l,n) struct n { int:(HOSTWDSZ-(s)-(l)); unsigned n:l;} n; 261 #else 262 #define DeclBitfR(s,l,n) struct n { int:((s)+(HOSTWDSZ-32)); unsigned n:l;} n; 263 #endif 264 265 /*--------------------------------------------------------------------------- 266 * Bitfield$Reference - Reference a specified bitfield within an integer. 267 * The argument "i" must be an addressable variable (i.e., not a register 268 * variable or an expression... but see BitfX below), "n" must be an 269 * identifier name declared in a DeclBitfR invocation. The resultant 270 * macro expansion references the bit field in "i" described by the 271 * DeclBitfR invocation with the same name ("n"). BitfR may be used as 272 * an lvalue or an rvalue. (i.e., either side of an assignment statement) 273 * The "s" and "l" arguments are historical and are now unused. (They 274 * correspond to the "s" and "l" arguments in DeclBitfR) 275 * Translates to a single instruction on both the VAX and the DEC-20. 276 *---------------------------------------------------------------------------*/ 277 #define BitfR(i,s,l,n) (i.n.n) 278 279 /*--------------------------------------------------------------------------- 280 * Bitfield$eXtract - Extract the specified field from an integer. Arguments 281 * are the same as for BitfR (except no "n"), however both "s" and "l" need 282 * no longer be constants. May only be used as an rvalue. Translates to 283 * two instructions on the VAX, three on the DEC-20. 284 *---------------------------------------------------------------------------*/ 285 286 #define BitfX(i,s,l) (((i.w) >> (32-(s)-(l))) & ((1 << (l)) - 1)) 287 288 289 /*--------------------------------------------------------------------------- 290 * Mask$32bits - Mask the low order 32 bits of passed word. No-op on 32 291 * bit machines. 292 *---------------------------------------------------------------------------*/ 293 294 #if HOSTWDSZ > 32 295 #define Mask32(x) ((x) & 0xffffffff) 296 #else 297 #define Mask32(x) (x) 298 #endif 299 300 301 /*--------------------------------------------------------------------------- 302 * SignExtend$32bits - Force the high-order bits in machines with wordsize 303 * longer than 32 to match bit 0. 304 *---------------------------------------------------------------------------*/ 305 306 #if HOSTWDSZ > 32 307 #define SignEx32(x) (((x) & 0x80000000) ? ((x) | ((unsigned)-1 << 32)) \ 308 : Mask32(x)) 309 #else 310 #define SignEx32(x) (x) 311 #endif 312 313 /**************************/ 314 /* bit field declarations */ 315 /**************************/ 316 317 /* since the compiler complains if a structure name is declared twice, even 318 * if the declarations are identical, all DeclBitfR invocations are 319 * given here in one file. */ 320 321 union insn { 322 int w; 323 DeclBitfR(0,1,_b01) 324 DeclBitfR(0,15,_b015) 325 DeclBitfR(0,16,_b016) 326 DeclBitfR(0,4,_b04) 327 DeclBitfR(0,6,_b06) 328 DeclBitfR(0,8,_b08) 329 DeclBitfR(4,1,_b41) 330 DeclBitfR(4,4,_b44) 331 DeclBitfR(6,1,_b61) 332 DeclBitfR(6,13,_b613) 333 DeclBitfR(6,15,_b615) 334 DeclBitfR(6,17,_b617) 335 DeclBitfR(6,26,_b626) 336 DeclBitfR(6,5,_b65) 337 DeclBitfR(7,1,_b71) 338 DeclBitfR(8,1,_b81) 339 DeclBitfR(8,4,_b84) 340 DeclBitfR(8,8,_b88) 341 DeclBitfR(9,1,_b91) 342 DeclBitfR(10,1,_b101) 343 DeclBitfR(11,1,_b111) 344 DeclBitfR(11,10,_b1110) 345 DeclBitfR(11,4,_b114) 346 DeclBitfR(11,5,_b115) 347 DeclBitfR(12,1,_b121) 348 DeclBitfR(12,4,_b124) 349 DeclBitfR(13,1,_b131) 350 DeclBitfR(14,1,_b141) 351 DeclBitfR(15,1,_b151) 352 DeclBitfR(16,1,_b161) 353 DeclBitfR(16,15,_b1615) 354 DeclBitfR(16,16,_b1616) 355 DeclBitfR(16,2,_b162) 356 DeclBitfR(16,3,_b163) 357 DeclBitfR(16,4,_b164) 358 DeclBitfR(16,5,_b165) 359 DeclBitfR(16,8,_b168) 360 DeclBitfR(17,1,_b171) 361 DeclBitfR(18,1,_b181) 362 DeclBitfR(18,13,_b1813) 363 DeclBitfR(18,2,_b182) 364 DeclBitfR(18,7,_b187) 365 DeclBitfR(19,1,_b191) 366 DeclBitfR(19,8,_b198) 367 DeclBitfR(19,10,_b1910) 368 DeclBitfR(20,11,_b2011) 369 DeclBitfR(20,2,_b202) 370 DeclBitfR(20,4,_b204) 371 DeclBitfR(21,10,_b2110) 372 DeclBitfR(21,2,_b212) 373 DeclBitfR(21,5,_b215) 374 DeclBitfR(22,5,_b225) 375 DeclBitfR(23,3,_b233) 376 DeclBitfR(24,1,_b241) 377 DeclBitfR(24,4,_b244) 378 DeclBitfR(24,8,_b248) 379 DeclBitfR(25,1,_b251) 380 DeclBitfR(26,1,_b261) 381 DeclBitfR(27,1,_b271) 382 DeclBitfR(27,4,_b274) 383 DeclBitfR(27,5,_b275) 384 DeclBitfR(28,1,_b281) 385 DeclBitfR(28,4,_b284) 386 DeclBitfR(29,1,_b291) 387 DeclBitfR(30,1,_b301) 388 DeclBitfR(30,2,_b302) 389 DeclBitfR(31,1,_b311) 390 }; 391 392 /******************/ 393 /* Word subfields */ 394 /******************/ 395 396 #define Sign(i) BitfR(i,0,1,_b01) 397 /* halfwords */ 398 #define Hwd0(i) BitfR(i,0,16,_b016) 399 #define Hwd1sign(i) BitfR(i,16,1,_b161) 400 #define Hwd1(i) BitfR(i,16,16,_b1616) 401 /* bytes */ 402 #define Byte0(i) BitfR(i,0,8,_b08) 403 #define Byte1sign(i) BitfR(i,8,1,_b81) 404 #define Byte1(i) BitfR(i,8,8,_b88) 405 #define Byte2(i) BitfR(i,16,8,_b168) 406 #define Byte3sign(i) BitfR(i,24,1,_b241) 407 #define Byte3(i) BitfR(i,24,8,_b248) 408 /* digits */ 409 #define Digit0(i) BitfR(i,0,4,_b04) 410 #define Digit1(i) BitfR(i,4,4,_b44) 411 #define Digit2(i) BitfR(i,8,4,_b84) 412 #define Digit3(i) BitfR(i,12,4,_b124) 413 #define Digit4(i) BitfR(i,16,4,_b164) 414 #define Digit5(i) BitfR(i,20,4,_b204) 415 #define Digit6(i) BitfR(i,24,4,_b244) 416 #define Digit7(i) BitfR(i,28,4,_b284) 417 418 /* Wordsize definitions */ 419 420 #define BIT_P_DW 64 /* bits/doubleword */ 421 #define BIT_P_WD 32 /* bits/word */ 422 #define BIT_P_HW 16 /* bits/halfword */ 423 #define BIT_P_BYT 8 /* bits/byte */ 424 #define BYT_P_DW 8 /* bytes/doubleword */ 425 #define BYT_P_WD 4 /* bytes/word */ 426 #define BYT_P_HW 2 /* bytes/halfword */ 427 428 /* Masks */ 429 430 #define WDMASK 0xffffffff /* 32-bit mask */ 431 #define OFSMASK 0xffffffff /* 32-bit mask */ 432 #define SIDMASK 0xffffffff /* 32-bit mask */ 433 #define SIGNMASK 0x80000000 /* 32 bit word sign bit */ 434 435 /* Alignments */ 436 437 #define wdalign(ofs) (ofs &= ~3) 438 /* 439 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 440 * 441 * Spectrum Simulator Instruction Opcode Definitions 442 * Dan Magenheimer 443 * Computer Research Center, Hewlett-Packard Labs 444 * 445 * (c) copyright 1982 446 * (p) protected 1982 447 * The Hewlett-Packard Company 448 * Hewlett-Packard Laboratories 449 * Computer Research Center 450 * Palo Alto, California 451 * 452 * *** HP Company Confidential *** 453 * 454 * Log: unasm.c,v 455 * Revision 1.5 1994/07/21 22:32:05 mike 456 * official HP copyright notice 457 * 458 * Revision 1.4 1992/07/08 12:19:52 dalton 459 * Checkin before split to 1.0.4 release (by LBS). 460 * 461 * Revision 1.3 92/06/06 16:16:45 dalton 462 * *** empty log message *** 463 * 464 * Revision 1.2 92/06/06 15:42:28 dalton 465 * Changed include to be a path relative to hp800. 466 * 467 * Revision 1.1 92/06/06 14:05:33 dalton 468 * Initial revision 469 * 470 * Revision 1.2 91/04/14 20:29:49 osfrcs 471 * Initial version. 472 * [91/03/30 09:20:34 brezak] 473 * 474 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 475 * Initial version. 476 * [91/03/30 09:20:34 brezak] 477 * 478 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 479 * Initial version. 480 * 481 * Revision 6.1 89/09/06 10:39:58 burroughs 482 * Added shadow registers for gr0-gr7. 483 * gr0-7 are copied into sh0-7 whenever a trap occurs 484 * the instruction RFIR restores gr0-7 from sh0-7 and returns from 485 * interrupt. 486 * the "sh" command displays the shadow registers 487 * = sh7 0x789 works, too. 488 * 489 * Revision 6.0 89/09/01 15:46:37 15:46:37 burroughs (Greg Burroughs) 490 * baseline for pcx simple offsite 491 * 492 * Revision 5.2 87/09/02 14:30:23 14:30:23 kent 493 * separated stat gathering for indexed vs short. 494 * this will NOT work if cache hints ever get used 495 * since this field was assumed always zero 496 * 497 * Revision 5.1 87/02/27 11:12:16 11:12:16 kent (Kent McMullen) 498 * update all src to 5.1 499 * 500 * Revision 5.0 87/02/18 16:31:35 16:31:35 kent (Kent McMullen) 501 * update all revision numbers to 5.0 for release 502 * 503 * Revision 1.1 86/07/15 08:34:57 08:34:57 kent (Kent McMullen) 504 * Initial revision 505 * 506 * Revision 4.1 83/10/25 17:02:34 17:02:34 djm (Daniel J Magenheimer) 507 * First release for ACD v4 508 * 509 * Revision 3.0 83/06/13 10:24:45 djm (Daniel Magenheimer) 510 * First release for distribution 511 * 512 * 513 */ 514 515 /* 516 * Changes: 517 * 01/30/90 ejf Simplify SPOPn support, now only gives assist emulation trap. 518 * 01/19/90 ejf Replace linpak instructions with just FSTQ[SX]. 519 * 12/19/89 ejf Add PA89 new floating point opcode 0E. 520 * 12/18/89 ejf Change 5 ops to PA89 format. 521 * 12/01/89 ejf Move additional instructions fmas, fmaa, fld2, fst2 to ssILst 522 * 09/22/89 ejf Fix unbalanced comments. 523 */ 524 525 526 /* ..and modified by hand to remove the load/store short references */ 527 /* ..and modified by hand to make memory management ops conform to the 528 * requirement that all subops of a major opcode begin in the same 529 * place and have the same length */ 530 531 #define LDW 0x12, 0x00, 0, 0 /* LOAD WORD */ 532 #define LDWM 0x13, 0x00, 0, 0 /* LOAD WORD and MODIFY */ 533 #define LDH 0x11, 0x00, 0, 0 /* LOAD HALFWORD */ 534 #define LDB 0x10, 0x00, 0, 0 /* LOAD BYTE */ 535 #define LDO 0x0d, 0x00, 0, 0 /* LOAD OFFSET */ 536 #define STW 0x1a, 0x00, 0, 0 /* STORE WORD */ 537 #define STWM 0x1b, 0x00, 0, 0 /* STORE WORD and MODIFY */ 538 #define STH 0x19, 0x00, 0, 0 /* STORE HALFWORD */ 539 #define STB 0x18, 0x00, 0, 0 /* STORE BYTE */ 540 #define LDWX 0x03, 0x02, 19, 7 /* LOAD WORD INDEXED */ 541 #define LDHX 0x03, 0x01, 19, 7 /* LOAD HALFWORD INDEXED */ 542 #define LDBX 0x03, 0x00, 19, 7 /* LOAD BYTE INDEXED */ 543 #define LDWAX 0x03, 0x06, 19, 7 /* LOAD WORD ABSOLUTE INDEXED */ 544 #define LDCWX 0x03, 0x07, 19, 7 /* LOAD and CLEAR WORD INDEXED */ 545 #define LDWS 0x03, 0x42, 19, 7 /* LOAD WORD SHORT DISP */ 546 #define LDHS 0x03, 0x41, 19, 7 /* LOAD HALFWORD SHORT DISP */ 547 #define LDBS 0x03, 0x40, 19, 7 /* LOAD BYTE SHORT DISP */ 548 #define LDWAS 0x03, 0x46, 19, 7 /* LOAD WORD ABSOLUTE SHORT DISP */ 549 #define LDCWS 0x03, 0x47, 19, 7 /* LOAD and CLEAR WORD SHORT DISP */ 550 #define STWS 0x03, 0x4a, 19, 7 /* STORE WORD SHORT DISP */ 551 #define STHS 0x03, 0x49, 19, 7 /* STORE HALFWORD SHORT DISP */ 552 #define STBS 0x03, 0x48, 19, 7 /* STORE BYTE SHORT DISP */ 553 #define STWAS 0x03, 0x4e, 19, 7 /* STORE WORD ABSOLUTE SHORT DISP */ 554 #define STBYS 0x03, 0x4c, 19, 7 /* STORE BYTES SHORT DISP */ 555 #define LDIL 0x08, 0x00, 0, 0 /* LOAD IMMED LEFT */ 556 #define ADDIL 0x0a, 0x00, 0, 0 /* ADD IMMED LEFT */ 557 #define BL 0x3a, 0x00, 16, 3 /* BRANCH [and LINK] */ 558 #define GATE 0x3a, 0x01, 16, 3 /* GATEWAY */ 559 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ 560 #define BV 0x3a, 0x06, 16, 3 /* BRANCH VECTORED */ 561 #define BE 0x38, 0x00, 0, 0 /* BRANCH EXTERNAL */ 562 #define BLE 0x39, 0x00, 0, 0 /* BRANCH and LINK EXTERNAL */ 563 #define MOVB 0x32, 0x00, 0, 0 /* MOVE and BRANCH */ 564 #define MOVIB 0x33, 0x00, 0, 0 /* MOVE IMMED and BRANCH */ 565 #define COMBT 0x20, 0x00, 0, 0 /* COMPARE and BRANCH if TRUE */ 566 #define COMBF 0x22, 0x00, 0, 0 /* COMPARE and BRANCH if FALSE */ 567 #define COMIBT 0x21, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if TRUE */ 568 #define COMIBF 0x23, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if FALSE */ 569 #define ADDBT 0x28, 0x00, 0, 0 /* ADD and BRANCH if TRUE */ 570 #define ADDBF 0x2a, 0x00, 0, 0 /* ADD and BRANCH if FALSE */ 571 #define ADDIBT 0x29, 0x00, 0, 0 /* ADD IMMED and BRANCH if TRUE */ 572 #define ADDIBF 0x2b, 0x00, 0, 0 /* ADD IMMED and BRANCH if FALSE */ 573 #define BVB 0x30, 0x00, 0, 0 /* BRANCH on VARIABLE BIT */ 574 #define BB 0x31, 0x00, 0, 0 /* BRANCH on BIT */ 575 #define ADD 0x02, 0x30, 20, 7 /* ADD */ 576 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ 577 #define ADDO 0x02, 0x70, 20, 7 /* ADD and TRAP on OVFLO */ 578 #define SH1ADD 0x02, 0x32, 20, 7 /* SHIFT 1, ADD */ 579 #define SH1ADDL 0x02, 0x52, 20, 7 /* SHIFT 1, ADD LOGICAL */ 580 #define SH1ADDO 0x02, 0x72, 20, 7 /* SHIFT 1, ADD and TRAP on OVFLO */ 581 #define SH2ADD 0x02, 0x34, 20, 7 /* SHIFT 2, ADD */ 582 #define SH2ADDL 0x02, 0x54, 20, 7 /* SHIFT 2, ADD LOGICAL */ 583 #define SH2ADDO 0x02, 0x74, 20, 7 /* SHIFT 2, ADD and TRAP on OVFLO */ 584 #define SH3ADD 0x02, 0x36, 20, 7 /* SHIFT 3, ADD */ 585 #define SH3ADDL 0x02, 0x56, 20, 7 /* SHIFT 3, ADD LOGICAL */ 586 #define SH3ADDO 0x02, 0x76, 20, 7 /* SHIFT 3, ADD and TRAP on OVFLO */ 587 #define ADDC 0x02, 0x38, 20, 7 /* ADD with CARRY */ 588 #define ADDCO 0x02, 0x78, 20, 7 /* ADD with CARRY and TRAP on OVFLO */ 589 #define SUB 0x02, 0x20, 20, 7 /* SUBTRACT */ 590 #define SUBO 0x02, 0x60, 20, 7 /* SUBTRACT and TRAP on OVFLO */ 591 #define SUBB 0x02, 0x28, 20, 7 /* SUBTRACT with BORROW */ 592 #define SUBBO 0x02, 0x68, 20, 7 /* SUBTRACT with BORROW and TRAP on OVFLO */ 593 #define SUBT 0x02, 0x26, 20, 7 /* SUBTRACT and TRAP on COND */ 594 #define SUBTO 0x02, 0x66, 20, 7 /* SUBTRACT and TRAP on COND or OVFLO */ 595 #define DS 0x02, 0x22, 20, 7 /* DIVIDE STEP */ 596 #define COMCLR 0x02, 0x44, 20, 7 /* COMPARE and CLEAR */ 597 #define OR 0x02, 0x12, 20, 7 /* INCLUSIVE OR */ 598 #define XOR 0x02, 0x14, 20, 7 /* EXCLUSIVE OR */ 599 #define AND 0x02, 0x10, 20, 7 /* AND */ 600 #define ANDCM 0x02, 0x00, 20, 7 /* AND COMPLEMENT */ 601 #define UXOR 0x02, 0x1c, 20, 7 /* UNIT XOR */ 602 #define UADDCM 0x02, 0x4c, 20, 7 /* UNIT ADD COMPLEMENT */ 603 #define UADDCMT 0x02, 0x4e, 20, 7 /* UNIT ADD COMPLEMENT and TRAP on COND */ 604 #define DCOR 0x02, 0x5c, 20, 7 /* DECIMAL CORRECT */ 605 #define IDCOR 0x02, 0x5e, 20, 7 /* INTERMEDIATE DECIMAL CORRECT */ 606 #define ADDI 0x2d, 0x00, 20, 1 /* ADD to IMMED */ 607 #define ADDIO 0x2d, 0x01, 20, 1 /* ADD to IMMED and TRAP on OVFLO */ 608 #define ADDIT 0x2c, 0x00, 20, 1 /* ADD to IMMED and TRAP on COND */ 609 #define ADDITO 0x2c, 0x01, 20, 1 /* ADD to IMMED and TRAP on COND or OVFLO */ 610 #define SUBI 0x25, 0x00, 20, 1 /* SUBTRACT from IMMED */ 611 #define SUBIO 0x25, 0x01, 20, 1 /* SUBTRACT from IMMED and TRAP on OVFLO */ 612 #define COMICLR 0x24, 0x00, 0, 0 /* COMPARE IMMED and CLEAR */ 613 #define VSHD 0x34, 0x00, 19, 3 /* VARIABLE SHIFT DOUBLE */ 614 #define SHD 0x34, 0x02, 19, 3 /* SHIFT DOUBLE */ 615 #define VEXTRU 0x34, 0x04, 19, 3 /* VARIABLE EXTRACT RIGHT UNSIGNED */ 616 #define VEXTRS 0x34, 0x05, 19, 3 /* VARIABLE EXTRACT RIGHT SIGNED */ 617 #define EXTRU 0x34, 0x06, 19, 3 /* EXTRACT RIGHT UNSIGNED */ 618 #define EXTRS 0x34, 0x07, 19, 3 /* EXTRACT RIGHT SIGNED */ 619 #define VDEP 0x35, 0x01, 19, 3 /* VARIABLE DEPOSIT */ 620 #define DEP 0x35, 0x03, 19, 3 /* DEPOSIT */ 621 #define VDEPI 0x35, 0x05, 19, 3 /* VARIABLE DEPOSIT IMMED */ 622 #define DEPI 0x35, 0x07, 19, 3 /* DEPOSIT IMMED */ 623 #define ZVDEP 0x35, 0x00, 19, 3 /* ZERO and VARIABLE DEPOSIT */ 624 #define ZDEP 0x35, 0x02, 19, 3 /* ZERO and DEPOSIT */ 625 #define ZVDEPI 0x35, 0x04, 19, 3 /* ZERO and VARIABLE DEPOSIT IMMED */ 626 #define ZDEPI 0x35, 0x06, 19, 3 /* ZERO and DEPOSIT IMMED */ 627 #define BREAK 0x00, 0x00, 19, 8 /* BREAK */ 628 #define RFI 0x00, 0x60, 19, 8 /* RETURN FROM INTERRUPTION */ 629 #define RFIR 0x00, 0x65, 19, 8 /* RFI & RESTORE SHADOW REGISTERS */ 630 #define SSM 0x00, 0x6b, 19, 8 /* SET SYSTEM MASK */ 631 #define RSM 0x00, 0x73, 19, 8 /* RESET SYSTEM MASK */ 632 #define MTSM 0x00, 0xc3, 19, 8 /* MOVE TO SYSTEM MASK */ 633 #define LDSID 0x00, 0x85, 19, 8 /* LOAD SPACE IDENTIFIER */ 634 #define MTSP 0x00, 0xc1, 19, 8 /* MOVE TO SPACE REGISTER */ 635 #define MTCTL 0x00, 0xc2, 19, 8 /* MOVE TO SYSTEM CONTROL REGISTER */ 636 #define MFSP 0x00, 0x25, 19, 8 /* MOVE FROM SPACE REGISTER */ 637 #define MFCTL 0x00, 0x45, 19, 8 /* MOVE FROM SYSTEM CONTROL REGISTER */ 638 #define SYNC 0x00, 0x20, 19, 8 /* SYNCHRONIZE DATA CACHE */ 639 #define DIAG 0x05, 0x00, 0, 0 /* DIAGNOSE */ 640 #define SPOP 0x04, 0x00, 0, 0 /* SPECIAL FUNCTION UNIT */ 641 #define COPR 0x0c, 0x00, 0, 0 /* COPROCESSOR */ 642 #define CLDWX 0x09, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 643 #define CLDDX 0x0b, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 644 #define CSTWX 0x09, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 645 #define CSTDX 0x0b, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 646 #define CLDWS 0x09, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 647 #define CLDDS 0x0b, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 648 #define CSTWS 0x09, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 649 #define CSTDS 0x0b, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 650 #define FLOAT0 0x0e, 0x00, 21, 2 /* FLOATING POINT CLASS 0 */ 651 #define FLOAT1 0x0e, 0x01, 21, 2 /* FLOATING POINT CLASS 1 */ 652 #define FLOAT2 0x0e, 0x02, 21, 2 /* FLOATING POINT CLASS 2 */ 653 #define FLOAT3 0x0e, 0x03, 21, 2 /* FLOATING POINT CLASS 3 */ 654 #define FMPYSUB 0x26, 0x00, 0, 0 /* FP MULTIPLY AND SUBTRACT */ 655 #define FMPYADD 0x06, 0x00, 0, 0 /* FP MULTIPLY AND ADD/TRUNCATE */ 656 #define FSTQX 0x0f, 0x01, 19, 4 /* FLOATING POINT STORE QUAD INDEXED */ 657 #define FSTQS 0x0f, 0x09, 19, 4 /* FLOATING POINT STORE QUAD SHORT */ 658 /* all of the following have been pushed around to conform */ 659 #define PROBER 0x01, 0x46, 19, 7 /* PROBE READ ACCESS */ 660 #ifdef notdef 661 #define PROBERI 0x01, 0xc6, 19, 7 /* PROBE READ ACCESS IMMEDIATE */ 662 #endif 663 #define PROBEW 0x01, 0x47, 19, 7 /* PROBE WRITE ACCESS */ 664 #ifdef notdef 665 #define PROBEWI 0x01, 0xc7, 19, 7 /* PROBE WRITE ACCESS IMMEDIATE */ 666 #endif 667 #define LPA 0x01, 0x4d, 19, 7 /* LOAD PHYSICAL ADDRESS */ 668 #define LHA 0x01, 0x4c, 19, 7 /* LOAD HASH ADDRESS */ 669 #define PDTLB 0x01, 0x48, 19, 7 /* PURGE DATA TRANS LOOKASIDE BUFFER */ 670 #define PITLB 0x01, 0x08, 19, 7 /* PURGE INST TRANS LOOKASIDE BUFFER */ 671 #define PDTLBE 0x01, 0x49, 19, 7 /* PURGE DATA TLB ENTRY */ 672 #define PITLBE 0x01, 0x09, 19, 7 /* PURGE INST TLB ENTRY */ 673 #define IDTLBA 0x01, 0x41, 19, 7 /* INSERT DATA TLB ADDRESS */ 674 #define IITLBA 0x01, 0x01, 19, 7 /* INSERT INSTRUCTION TLB ADDRESS */ 675 #define IDTLBP 0x01, 0x40, 19, 7 /* INSERT DATA TLB PROTECTION */ 676 #define IITLBP 0x01, 0x00, 19, 7 /* INSERT INSTRUCTION TLB PROTECTION */ 677 #define PDC 0x01, 0x4e, 19, 7 /* PURGE DATA CACHE */ 678 #define FDC 0x01, 0x4a, 19, 7 /* FLUSH DATA CACHE */ 679 #define FIC 0x01, 0x0a, 19, 7 /* FLUSH INSTRUCTION CACHE */ 680 #define FDCE 0x01, 0x4b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 681 #define FICE 0x01, 0x0b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 682 683 /* 684 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 685 * 686 * Spectrum Simulator Instruction Set Constants and Datatypes 687 * Dan Magenheimer - 4/28/82 688 * Computer Research Center, Hewlett-Packard Labs 689 * 690 * (c) copyright 1982 691 * (p) protected 1982 692 * The Hewlett-Packard Company 693 * Hewlett-Packard Laboratories 694 * Computer Research Center 695 * Palo Alto, California 696 * 697 * *** HP Company Confidential *** 698 * 699 * Log: unasm.c,v 700 * Revision 1.5 1994/07/21 22:32:05 mike 701 * official HP copyright notice 702 * 703 * Revision 1.4 1992/07/08 12:19:52 dalton 704 * Checkin before split to 1.0.4 release (by LBS). 705 * 706 * Revision 1.3 92/06/06 16:16:45 dalton 707 * *** empty log message *** 708 * 709 * Revision 1.2 92/06/06 15:42:28 dalton 710 * Changed include to be a path relative to hp800. 711 * 712 * Revision 1.1 92/06/06 14:05:33 dalton 713 * Initial revision 714 * 715 * Revision 1.2 91/04/14 20:29:49 osfrcs 716 * Initial version. 717 * [91/03/30 09:20:34 brezak] 718 * 719 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 720 * Initial version. 721 * [91/03/30 09:20:34 brezak] 722 * 723 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 724 * Initial version. 725 * 726 ;Revision 1.1 88/07/11 14:05:21 14:05:21 ren (Bob Naas) 727 ;Initial revision 728 ; 729 * Revision 5.1 87/02/27 11:12:23 11:12:23 kent (Kent McMullen) 730 * update all src to 5.1 731 * 732 * Revision 5.0 87/02/18 16:31:52 16:31:52 kent (Kent McMullen) 733 * update all revision numbers to 5.0 for release 734 * 735 * Revision 1.1 86/07/15 08:35:00 08:35:00 kent (Kent McMullen) 736 * Initial revision 737 * 738 * Revision 4.3 85/11/12 09:28:44 09:28:44 viggy (Viggy Mokkarala) 739 * first mpsim version, partially stable 740 * 741 * Revision 4.2 84/07/16 17:20:57 17:20:57 djm () 742 * Define field macros for COPR and SFU insts 743 * 744 * Revision 4.1 83/10/25 17:10:14 djm (Daniel Magenheimer) 745 * First release for ACD v4 746 * 747 * Revision 3.1 83/08/03 14:09:59 djm (Daniel Magenheimer) 748 * Sys calls, args, -S, bug fixes, etc. 749 * 750 * Revision 3.0 83/06/13 10:25:13 djm (Daniel Magenheimer) 751 * First release for distribution 752 * 753 * 754 */ 755 /* 756 * Changes: 757 * 12/01/89 ejf Add Rsd(), Rse(), Rtd(), Rte() for 5 ops. 758 * 11/30/89 ejf Make instruction use counters shared, not per cpu. 759 * 11/28/89 ejf Change majoropcode for quicker extension extract. 760 */ 761 762 763 764 /* 765 * Dependencies: std.h, ssDefs.h, bits.h 766 */ 767 768 769 /* Lookup/Execute structure for instructions */ 770 struct inst { 771 u_char majopc; /* major opcode of instruction, 0..MAXOPC */ 772 u_char opcext; /* opcode extension, 0 if not applic. */ 773 u_char extbs; /* starting bit pos of extension field */ 774 u_char extbl; /* bit length of extension field */ 775 u_int count; /* frequency counter for analysis */ 776 char mnem[8]; /* ascii mnemonic */ 777 /* disassembly function */ 778 int (*dasmfcn)(const struct inst *, OFS, union insn); 779 }; 780 781 782 #define NMAJOPCS 64 783 784 struct majoropcode { 785 const struct inst **subops; /* pointer to table of subops indexed by 786 * opcode extension */ 787 u_int maxsubop; /* largest opcode extension value or 0 */ 788 u_int extshft; /* right shift amount for extension field */ 789 u_int extmask; /* post shift mask for extension field */ 790 }; 791 792 #define OpExt(i,m) ((i >> m->extshft) & m->extmask) /* extract opcode extension */ 793 794 795 /*****************************/ 796 /* Miscellaneous definitions */ 797 /*****************************/ 798 799 /* Load/Store Indexed Opcode Extension Cache Control */ 800 #define NOACTION 0 801 #define STACKREF 1 802 #define SEQPASS 2 803 #define PREFETCH 3 804 805 /******************************/ 806 /* Fields within instructions */ 807 /******************************/ 808 809 /* opcode */ 810 #define Opcode(i) BitfR(i,0,6,_b06) 811 /* opcode true/false bit */ 812 #define OpcTF(i) BitfR(i,4,1,_b41) 813 /* register sources */ 814 #define Rsa(i) BitfR(i,11,5,_b115) 815 #define Rsb(i) BitfR(i,6,5,_b65) 816 #define Rsc(i) BitfR(i,27,5,_b275) 817 #define Rsd(i) BitfR(i,21,5,_b215) 818 #define Rse(i) BitfR(i,16,5,_b165) 819 /* register targets */ 820 #define Rta(i) BitfR(i,11,5,_b115) 821 #define Rtb(i) BitfR(i,6,5,_b65) 822 #define Rtc(i) BitfR(i,27,5,_b275) 823 #define Rtd(i) BitfR(i,21,5,_b215) 824 #define Rte(i) BitfR(i,16,5,_b165) 825 /* 5-bit immediates (Magnitude, Sign) */ 826 #define Imb5(i) BitfR(i,6,5,_b65) 827 #define Ima5M(i) BitfR(i,11,4,_b114) 828 #define Ima5S(i) BitfR(i,15,1,_b151) 829 #define Ima5A(i) BitfR(i,11,5,_b115) 830 #define Imd5(i) BitfR(i,22,5,_b225) 831 #define Imc5M(i) BitfR(i,27,4,_b274) 832 #define Imc5S(i) BitfR(i,31,1,_b311) 833 #define Imc5A(i) BitfR(i,27,5,_b275) 834 /* Other immediates */ 835 #define Im21L(i) BitfR(i,18,2,_b182) 836 #define Im21H(i) BitfR(i,20,11,_b2011) 837 #define Im21M1(i) BitfR(i,16,2,_b162) 838 #define Im21M2(i) BitfR(i,11,5,_b115) 839 #define Im21S(i) BitfR(i,31,1,_b311) 840 #define Im11M(i) BitfR(i,21,10,_b2110) 841 #define Im11S(i) BitfR(i,31,1,_b311) 842 /* displacements/offsets */ 843 #define DispM(i) BitfR(i,18,13,_b1813) 844 #define DispS(i) BitfR(i,31,1,_b311) 845 #define Off5(i) BitfR(i,11,5,_b115) 846 #define Off11H(i) BitfR(i,19,10,_b1910) 847 #define Off11L(i) BitfR(i,29,1,_b291) 848 #define OffS(i) BitfR(i,31,1,_b311) 849 /* miscellaneous */ 850 #define Dss(i) BitfR(i,16,2,_b162) 851 #define Cond(i) BitfR(i,16,3,_b163) 852 #define Cneg(i) BitfR(i,19,1,_b191) 853 #define Cond4(i) BitfR(i,16,4,_b164) /* Cond AND Cneg */ 854 #define Nu(i) BitfR(i,30,1,_b301) 855 #define SrL(i) BitfR(i,16,2,_b162) 856 #define SrH(i) BitfR(i,18,1,_b181) 857 #define ShortDisp(i) BitfR(i,19,1,_b191) 858 #define IndxShft(i) BitfR(i,18,1,_b181) 859 #define ModBefore(i) BitfR(i,18,1,_b181) 860 #define CacheCtrl(i) BitfR(i,20,2,_b202) 861 #define Modify(i) BitfR(i,26,1,_b261) 862 #define ProbeI(i) BitfR(i,18,1,_b181) 863 #define Uid(i) BitfR(i,23,3,_b233) 864 #define Sfu(i) BitfR(i,23,3,_b233) 865 #define CopExt17(i) BitfR(i,6,17,_b617) 866 #define CopExt5(i) BitfR(i,27,5,_b275) 867 #define SpopType(i) BitfR(i,21,2,_b212) 868 #define SpopExt15(i) BitfR(i,6,15,_b615) 869 #define SpopExt10(i) BitfR(i,11,10,_b1110) 870 #define SpopExt5L(i) BitfR(i,16,5,_b165) 871 #define SpopExt5(i) BitfR(i,27,5,_b275) 872 #define NoMajOpc(i) BitfR(i,6,26,_b626) 873 #define Bi1(i) BitfR(i,27,5,_b275) /* fields in BREAK */ 874 #define Bi2(i) BitfR(i,6,13,_b613) 875 876 /* fragmented field collating macros */ 877 #define Ima5(i) (Ima5S(i) ? Ima5M(i) | (-1<<4) : Ima5M(i)) 878 879 #define Imc5(i) (Imc5S(i) ? Imc5M(i) | (-1<<4) : Imc5M(i)) 880 881 #define Disp(i) (DispS(i) ? DispM(i) | (-1<<13) : DispM(i)) 882 883 #define Im21(i) (Im21S(i) << 31 | Im21H(i) << 20 | Im21M1(i) << 18 | \ 884 Im21M2(i) << 13 | Im21L(i) << 11) 885 886 #define Im11(i) (Im11S(i) ? Im11M(i) | (-1<<10) : Im11M(i)) 887 888 #define Bdisp(i) ((OffS(i) ? (Off5(i)<<11 | Off11L(i)<<10|Off11H(i)) \ 889 /* branch displacement (bytes) */ | (-1 << 16) \ 890 : (Off5(i)<<11|Off11L(i)<<10|Off11H(i))) << 2) 891 892 #define Cbdisp(i) ((OffS(i) ? (Off11L(i) << 10 | Off11H(i)) \ 893 /* compare/branch disp (bytes) */ | (-1 << 11) \ 894 : Off11L(i) << 10 | Off11H(i)) << 2) 895 896 #define Sr(i) (SrH(i)<<2 | SrL(i)) 897 898 /* sfu/copr */ 899 #define CoprExt1(i) (CopExt17(i)) 900 #define CoprExt2(i) (CopExt5(i)) 901 #define CoprExt(i) ((CopExt17(i)<<5) | CopExt5(i)) 902 #define Spop0Ext(i) ((SpopExt15(i)<<5) | SpopExt5(i)) 903 #define Spop1Ext(i) (SpopExt15(i)) 904 #define Spop2Ext(i) ((SpopExt10(i)<<5) | SpopExt5(i)) 905 #define Spop3Ext(i) ((SpopExt5L(i)<<5) | SpopExt5(i)) 906 907 908 /*##################### Globals - Imports ##################################*/ 909 910 /* Disassembly functions */ 911 int fcoprDasm __P((union insn, u_int, u_int)); 912 char *edDCond __P((u_int cond)); 913 char *unitDCond __P((u_int cond)); 914 char *addDCond __P((u_int cond)); 915 char *subDCond __P((u_int cond)); 916 int blDasm __P((const struct inst *i, OFS, union insn)); 917 int ldDasm __P((const struct inst *, OFS, union insn)); 918 int stDasm __P((const struct inst *i, OFS, union insn)); 919 int addDasm __P((const struct inst *i, OFS, union insn)); 920 int unitDasm __P((const struct inst *i, OFS, union insn)); 921 int iaDasm __P((const struct inst *i, OFS, union insn)); 922 int shdDasm __P((const struct inst *i, OFS, union insn)); 923 int extrDasm __P((const struct inst *i, OFS, union insn)); 924 int vextrDasm __P((const struct inst *i, OFS, union insn)); 925 int depDasm __P((const struct inst *i, OFS, union insn)); 926 int vdepDasm __P((const struct inst *i, OFS, union insn)); 927 int depiDasm __P((const struct inst *i, OFS, union insn)); 928 int vdepiDasm __P((const struct inst *i, OFS, union insn)); 929 int limmDasm __P((const struct inst *i, OFS, union insn)); 930 int brkDasm __P((const struct inst *i, OFS, union insn)); 931 int lpkDasm __P((const struct inst *i, OFS, union insn)); 932 int fmpyaddDasm __P((const struct inst *i, OFS, union insn)); 933 int fmpysubDasm __P((const struct inst *i, OFS, union insn)); 934 int floatDasm __P((const struct inst *i, OFS, union insn)); 935 int coprDasm __P((const struct inst *i, OFS, union insn)); 936 int diagDasm __P((const struct inst *i, OFS, union insn)); 937 int scDasm __P((const struct inst *i, OFS, union insn)); 938 int mmgtDasm __P((const struct inst *i, OFS, union insn)); 939 int ldxDasm __P((const struct inst *i, OFS, union insn)); 940 int stsDasm __P((const struct inst *i, OFS, union insn)); 941 int stbysDasm __P((const struct inst *i, OFS, union insn)); 942 int brDasm __P((const struct inst *i, OFS, union insn)); 943 int bvDasm __P((const struct inst *i, OFS, union insn)); 944 int beDasm __P((const struct inst *i, OFS, union insn)); 945 int cbDasm __P((const struct inst *i,OFS ofs, union insn)); 946 int cbiDasm __P((const struct inst *i,OFS ofs, union insn)); 947 int bbDasm __P((const struct inst *i,OFS ofs, union insn)); 948 int ariDasm __P((const struct inst *i, OFS, union insn)); 949 950 /*##################### Globals - Exports ##################################*/ 951 /*##################### Local Variables ####################################*/ 952 953 static const char fcoprUndef[] = "copr\t(rsvd or undef.)"; 954 static const char fmtStrTbl[][5] = { "sgl", "dbl", "sgl", "quad" }; 955 static const char condStrTbl[][7] = { 956 "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", 957 "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", 958 "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", 959 "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" 960 }; 961 static const char fsreg[][5] = { 962 "r0L", "r0R", "r1L", "r1R", "r2L", "r2R", "r3L", "r3R", 963 "r4L", "r4R", "r5L", "r5R", "r6L", "r6R", "r7L", "r7R", 964 "r8L", "r8R", "r9L", "r9R", "r10L", "r10R", "r11L", "r11R", 965 "r12L", "r12R", "r13L", "r13R", "r14L", "r14R", "r15L", "r15R", 966 "r16L", "r16R", "r17L", "r17R", "r18L", "r18R", "r19L", "r19R", 967 "r20L", "r20R", "r21L", "r21R", "r22L", "r22R", "r23L", "r23R", 968 "r24L", "r24R", "r25L", "r25R", "r26L", "r26R", "r27L", "r27R", 969 "r28L", "r28R", "r29L", "r29R", "r30L", "r30R", "r31L", "r31R" 970 }; 971 static const char fdreg[][4] = { 972 "r0", "r0", "r1", "r1", "r2", "r2", "r3", "r3", 973 "r4", "r4", "r5", "r5", "r6", "r6", "r7", "r7", 974 "r8", "r8", "r9", "r9", "r10", "r10", "r11", "r11", 975 "r12", "r12", "r13", "r13", "r14", "r14", "r15", "r15", 976 "r16", "r16", "r17", "r17", "r18", "r18", "r19", "r19", 977 "r20", "r20", "r21", "r21", "r22", "r22", "r23", "r23", 978 "r24", "r24", "r25", "r25", "r26", "r26", "r27", "r27", 979 "r28", "r28", "r29", "r29", "r30", "r30", "r31", "r31" 980 }; 981 982 /*##################### Macros #############################################*/ 983 984 #define Match(s) (strncmp(s,i->mnem,sizeof(s)-1) == 0) 985 986 /* bits for assist ops */ 987 #define AstNu(w) Modify(w) 988 #define Fpi(w) (Uid(w)>3) 989 990 /* bits for 5 ops */ 991 #define SinglePrec(i) Modify(i) 992 #define Ms1(i) ((Rsb(i)<<1)+(SinglePrec(i)?((Rsb(i)>15)?1:32):0)) 993 #define Ms2(i) ((Rsa(i)<<1)+(SinglePrec(i)?((Rsa(i)>15)?1:32):0)) 994 #define Mt(i) ((Rtc(i)<<1)+(SinglePrec(i)?((Rtc(i)>15)?1:32):0)) 995 #define As(i) ((Rsd(i)<<1)+(SinglePrec(i)?((Rsd(i)>15)?1:32):0)) 996 #define Ad(i) ((Rte(i)<<1)+(SinglePrec(i)?((Rte(i)>15)?1:32):0)) 997 998 /*##################### Globals - Exports ##################################*/ 999 1000 /* To replace instr function, do the following: */ 1001 /* a) locate the desired entry in instrs[] below */ 1002 /* b) change the 3rd field if an alternate mneumonic is */ 1003 /* desired for window disassembly */ 1004 /* c) change the 4th field to the name of the function being */ 1005 /* used for replacement (i.e. ldwRepl instead of ldw) */ 1006 /* d) change the 5th field if an alternate disassembly routine */ 1007 /* is desired (i.e. ldDasmRepl) */ 1008 1009 static const struct inst instrs[] = { 1010 { LDW, 0, "ldw", ldDasm }, 1011 { LDH, 0, "ldh", ldDasm }, 1012 { LDB, 0, "ldb", ldDasm }, 1013 { LDWM, 0, "ldwm", ldDasm }, 1014 { LDO, 0, "ldo", ldDasm }, 1015 { STW, 0, "stw", stDasm }, 1016 { STH, 0, "sth", stDasm }, 1017 { STB, 0, "stb", stDasm }, 1018 { STWM, 0, "stwm", stDasm }, 1019 { LDWX, 0, "ldw", ldxDasm }, 1020 { LDHX, 0, "ldh", ldxDasm }, 1021 { LDBX, 0, "ldb", ldxDasm }, 1022 { LDCWX, 0, "ldcw", ldxDasm }, 1023 { LDWAX, 0, "ldwa", ldxDasm }, 1024 { LDWS, 0, "ldw", ldxDasm }, 1025 { LDHS, 0, "ldh", ldxDasm }, 1026 { LDBS, 0, "ldb", ldxDasm }, 1027 { LDCWS, 0, "ldcw", ldxDasm }, 1028 { LDWAS, 0, "ldwa", ldxDasm }, 1029 { STWS, 0, "stws", stsDasm }, 1030 { STHS, 0, "sths", stsDasm }, 1031 { STBS, 0, "stbs", stsDasm }, 1032 { STWAS, 0, "stwas", stsDasm }, 1033 { STBYS, 0, "stbys", stbysDasm }, 1034 { LDIL, 0, "ldil", limmDasm }, 1035 { ADDIL, 0, "addil", limmDasm }, 1036 { GATE, 0, "gate", blDasm }, 1037 { BL, 0, "b", blDasm }, 1038 { BLR, 0, "blr", brDasm }, 1039 { BV, 0, "bv", bvDasm }, 1040 { BE, 0, "be", beDasm }, 1041 { BLE, 0, "ble", beDasm }, 1042 { COMBT, 0, "combt", cbDasm }, 1043 { COMBF, 0, "combf", cbDasm }, 1044 { COMIBT, 0, "comibt", cbiDasm }, 1045 { COMIBF, 0, "comibf", cbiDasm }, 1046 { ADDBT, 0, "addbt", cbDasm }, 1047 { ADDBF, 0, "addbf", cbDasm }, 1048 { ADDIBT, 0, "addibt", cbiDasm }, 1049 { ADDIBF, 0, "addibf", cbiDasm }, 1050 { MOVB, 0, "movb", cbDasm }, 1051 { MOVIB, 0, "movib", cbiDasm }, 1052 { BB, 0, "bb", bbDasm }, 1053 { BVB, 0, "bvb", bbDasm }, 1054 { SUBO, 0, "subo", ariDasm }, 1055 { ADD, 0, "add", addDasm }, 1056 { ADDL, 0, "addl", addDasm }, 1057 { ADDO, 0, "addo", ariDasm }, 1058 { SH1ADD, 0, "sh1add", ariDasm }, 1059 { SH1ADDL,0, "sh1addl", ariDasm }, 1060 { SH1ADDO,0, "sh1addo", ariDasm }, 1061 { SH2ADD, 0, "sh2add", ariDasm }, 1062 { SH2ADDL,0, "sh2addl", ariDasm }, 1063 { SH2ADDO,0, "sh2addo", ariDasm }, 1064 { SH3ADD, 0, "sh3add", ariDasm }, 1065 { SH3ADDL,0, "sh3addl", ariDasm }, 1066 { SH3ADDO,0, "sh3addo", ariDasm }, 1067 { SUB, 0, "sub", ariDasm }, 1068 { ADDCO, 0, "addco", ariDasm }, 1069 { SUBBO, 0, "subbo", ariDasm }, 1070 { ADDC, 0, "addc", ariDasm }, 1071 { SUBB, 0, "subb", ariDasm }, 1072 { COMCLR, 0, "comclr", ariDasm }, 1073 { OR, 0, "or", ariDasm }, 1074 { AND, 0, "and", ariDasm }, 1075 { XOR, 0, "xor", ariDasm }, 1076 { ANDCM, 0, "andcm", ariDasm }, 1077 { DS, 0, "ds", ariDasm }, 1078 { UXOR, 0, "uxor", unitDasm }, 1079 { UADDCM, 0, "uaddcm", unitDasm }, 1080 { UADDCMT,0, "uaddcmt", unitDasm }, 1081 { SUBTO, 0, "subto", ariDasm }, 1082 { SUBT, 0, "subt", ariDasm }, 1083 { DCOR, 0, "dcor", unitDasm }, 1084 { IDCOR, 0, "idcor", unitDasm }, 1085 { ADDIO, 0, "addio", iaDasm }, 1086 { SUBIO, 0, "subio", iaDasm }, 1087 { ADDI, 0, "addi", iaDasm }, 1088 { SUBI, 0, "subi", iaDasm }, 1089 { COMICLR,0, "comiclr", iaDasm }, 1090 { ADDITO, 0, "addito", iaDasm }, 1091 { ADDIT, 0, "addit", iaDasm }, 1092 { SHD, 0, "shd", shdDasm }, 1093 { VSHD, 0, "vshd", shdDasm }, 1094 { EXTRU, 0, "extru", extrDasm }, 1095 { EXTRS, 0, "extrs", extrDasm }, 1096 { VEXTRU, 0, "vextru", vextrDasm }, 1097 { VEXTRS, 0, "vextrs", vextrDasm }, 1098 { DEP, 0, "dep", depDasm }, 1099 { VDEP, 0, "vdep", vdepDasm }, 1100 { DEPI, 0, "depi", depiDasm }, 1101 { VDEPI, 0, "vdepi", vdepiDasm }, 1102 { ZDEP, 0, "zdep", depDasm }, 1103 { ZVDEP, 0, "zvdep", vdepDasm }, 1104 { ZDEPI, 0, "zdepi", depiDasm }, 1105 { ZVDEPI, 0, "zvdepi", vdepiDasm }, 1106 { BREAK, 0, "break", brkDasm }, 1107 { RFI, 0, "rfi", 0 }, 1108 { RFIR, 0, "rfir", 0 }, 1109 { SSM, 0, "ssm", scDasm }, 1110 { RSM, 0, "rsm", scDasm }, 1111 { MTSM, 0, "mtsm", scDasm }, 1112 { PROBER, 0, "prober", mmgtDasm }, 1113 { PROBEW, 0, "probew", mmgtDasm }, 1114 { LPA, 0, "lpa", mmgtDasm }, 1115 { LHA, 0, "lha", mmgtDasm }, 1116 { LDSID, 0, "ldsid", scDasm }, 1117 { PDTLB, 0, "pdtlb", mmgtDasm }, 1118 { PDTLBE, 0, "pdtlbe", mmgtDasm }, 1119 { PITLB, 0, "pitlb", mmgtDasm }, 1120 { PITLBE, 0, "pitlbe", mmgtDasm }, 1121 { IDTLBA, 0, "idtlba", mmgtDasm }, 1122 { IITLBA, 0, "iitlba", mmgtDasm }, 1123 { IDTLBP, 0, "idtlbp", mmgtDasm }, 1124 { IITLBP, 0, "iitlbp", mmgtDasm }, 1125 { FIC, 0, "fic", mmgtDasm }, 1126 { FICE, 0, "fice", mmgtDasm }, 1127 { PDC, 0, "pdc", mmgtDasm }, 1128 { FDC, 0, "fdc", mmgtDasm }, 1129 { FDCE, 0, "fdce", mmgtDasm }, 1130 { SYNC, 0, "sync", 0 }, 1131 { MTSP, 0, "mtsp", scDasm }, 1132 { MTCTL, 0, "mtctl", scDasm }, 1133 { MFSP, 0, "mfsp", scDasm }, 1134 { MFCTL, 0, "mfctl", scDasm }, 1135 { DIAG, 0, "diag", diagDasm }, 1136 { SPOP, 0, "???", 0 }, 1137 { COPR, 0, "copr", coprDasm }, 1138 { CLDWX, 0, "cldw", coprDasm }, 1139 { CLDDX, 0, "cldd", coprDasm }, 1140 { CSTWX, 0, "cstw", coprDasm }, 1141 { CSTDX, 0, "cstd", coprDasm }, 1142 { CLDWS, 0, "cldw", coprDasm }, 1143 { CLDDS, 0, "cldd", coprDasm }, 1144 { CSTWS, 0, "cstw", coprDasm }, 1145 { CSTDS, 0, "cstd", coprDasm }, 1146 { FLOAT0, 0, "f", floatDasm }, 1147 { FLOAT1, 0, "fcnv", floatDasm }, 1148 { FLOAT2, 0, "f", floatDasm }, 1149 { FLOAT3, 0, "f", floatDasm }, 1150 { FMPYSUB,0, "fmpy", fmpysubDasm }, 1151 { FMPYADD,0, "fmpy", fmpyaddDasm }, 1152 { FSTQX, 0, "fstqx", lpkDasm }, 1153 { FSTQS, 0, "fstqs", lpkDasm }, 1154 {0} 1155 }; 1156 1157 1158 static const struct inst illeg = { 0, 0, 0, 0, 0, "???", 0 }; 1159 static const struct inst *so_sysop[0xd0]; 1160 static const struct inst *so_mmuop[0x50]; 1161 static const struct inst *so_arith[0x80]; 1162 static const struct inst *so_loads[0x50]; 1163 static const struct inst *so_cldw [0x0A]; 1164 static const struct inst *so_cldd [0x0A]; 1165 static const struct inst *so_float[0x04]; 1166 static const struct inst *so_fstq [0x0A]; 1167 static const struct inst *so_ebran[0x08]; 1168 static const struct inst *so_addit[0x02]; 1169 static const struct inst *so_addi [0x02]; 1170 static const struct inst *so_subi [0x02]; 1171 static const struct inst *so_shext[0x08]; 1172 static const struct inst *so_deps [0x08]; 1173 1174 #define ILLEG (const struct inst **)&illeg 1175 #define NENTS(a) (sizeof(a)/sizeof(a[0])-1) 1176 static struct majoropcode majopcs[NMAJOPCS] = { 1177 { so_sysop, NENTS(so_sysop) }, /* 00 */ 1178 { so_mmuop, NENTS(so_mmuop) }, /* 01 */ 1179 { so_arith, NENTS(so_arith) }, /* 02 */ 1180 { so_loads, NENTS(so_loads) }, /* 03 */ 1181 { ILLEG, 1 }, /* 04 */ 1182 { ILLEG, 1 }, /* 05 */ 1183 { ILLEG, 1 }, /* 06 */ 1184 { ILLEG, 1 }, /* 07 */ 1185 { ILLEG, 1 }, /* 08 */ 1186 { so_cldw , NENTS(so_cldw ) }, /* 09 */ 1187 { ILLEG, 1 }, /* 0A */ 1188 { so_cldd , NENTS(so_cldd ) }, /* 0B */ 1189 { ILLEG, 1 }, /* 0C */ 1190 { ILLEG, 1 }, /* 0D */ 1191 { so_float, NENTS(so_float) }, /* 0E */ 1192 { so_fstq , NENTS(so_fstq ) }, /* 0F */ 1193 { ILLEG, 1 }, /* 10 */ 1194 { ILLEG, 1 }, /* 11 */ 1195 { ILLEG, 1 }, /* 12 */ 1196 { ILLEG, 1 }, /* 13 */ 1197 { ILLEG, 1 }, /* 14 */ 1198 { ILLEG, 1 }, /* 15 */ 1199 { ILLEG, 1 }, /* 16 */ 1200 { ILLEG, 1 }, /* 17 */ 1201 { ILLEG, 1 }, /* 18 */ 1202 { ILLEG, 1 }, /* 19 */ 1203 { ILLEG, 1 }, /* 1A */ 1204 { ILLEG, 1 }, /* 1B */ 1205 { ILLEG, 1 }, /* 1C */ 1206 { ILLEG, 1 }, /* 1D */ 1207 { ILLEG, 1 }, /* 1E */ 1208 { ILLEG, 1 }, /* 1F */ 1209 { ILLEG, 1 }, /* 20 */ 1210 { ILLEG, 1 }, /* 21 */ 1211 { ILLEG, 1 }, /* 22 */ 1212 { ILLEG, 1 }, /* 23 */ 1213 { ILLEG, 1 }, /* 24 */ 1214 { so_subi , NENTS(so_subi ) }, /* 25 */ 1215 { ILLEG, 1 }, /* 26 */ 1216 { ILLEG, 1 }, /* 27 */ 1217 { ILLEG, 1 }, /* 28 */ 1218 { ILLEG, 1 }, /* 29 */ 1219 { ILLEG, 1 }, /* 2A */ 1220 { ILLEG, 1 }, /* 2B */ 1221 { so_addit, NENTS(so_addit) }, /* 2C */ 1222 { so_addi , NENTS(so_addi ) }, /* 2D */ 1223 { ILLEG, 1 }, /* 2E */ 1224 { ILLEG, 1 }, /* 2F */ 1225 { ILLEG, 1 }, /* 30 */ 1226 { ILLEG, 1 }, /* 31 */ 1227 { ILLEG, 1 }, /* 32 */ 1228 { ILLEG, 1 }, /* 33 */ 1229 { so_shext, NENTS(so_shext) }, /* 34 */ 1230 { so_deps , NENTS(so_deps ) }, /* 35 */ 1231 { ILLEG, 1 }, /* 36 */ 1232 { ILLEG, 1 }, /* 37 */ 1233 { ILLEG, 1 }, /* 38 */ 1234 { ILLEG, 1 }, /* 39 */ 1235 { so_ebran, NENTS(so_ebran) }, /* 3A */ 1236 { ILLEG, 1 }, /* 3B */ 1237 { ILLEG, 1 }, /* 3C */ 1238 { ILLEG, 1 }, /* 3D */ 1239 { ILLEG, 1 }, /* 3E */ 1240 { ILLEG, 1 }, /* 3F */ 1241 }; 1242 #undef NENTS 1243 #undef ILLEG 1244 1245 /*-------------------------------------------------------------------------- 1246 * instruction$ExecutionInitialize - Initialize the instruction execution 1247 * data structures. 1248 *---------------------------------------------------------------------------*/ 1249 static int iExInit __P((void)); 1250 static int 1251 iExInit(void) 1252 { 1253 static int unasm_initted = 0; 1254 const struct inst *i; 1255 struct majoropcode *m; 1256 u_int shft, mask; 1257 1258 if (unasm_initted) 1259 return 0; 1260 1261 /* 1262 * Determine maxsubop for each major opcode. 1263 * Also, check all instructions of a given major opcode 1264 * for consistent opcode extension field definition, and 1265 * save a converted form of this definition in the majopcs 1266 * entry for this major opcode. 1267 */ 1268 for (i = &instrs[0]; *i->mnem; i++) { 1269 m = &majopcs[i->majopc]; 1270 if (m->maxsubop < i->opcext) 1271 panic("iExInit not enough space for opcode %d", 1272 i->majopc); 1273 shft = 32 - i->extbs - i->extbl; 1274 mask = (1 << i->extbl) - 1; 1275 if (m->extshft || m->extmask) { 1276 if (m->extshft != shft || m->extmask != mask) { 1277 db_printf("%s - Bad instruction initialization!\n", i->mnem); 1278 return (0); 1279 } 1280 } else { 1281 m->extshft = shft; 1282 m->extmask = mask; 1283 } 1284 } 1285 1286 /* 1287 * Lastly, fill in all legal subops with the appropriate info. 1288 */ 1289 for (i = &instrs[0]; *i->mnem; i++) { 1290 m = &majopcs[i->majopc]; 1291 if (m->maxsubop == 1) 1292 m->subops = (const struct inst **)i; 1293 else 1294 m->subops[i->opcext] = i; 1295 } 1296 1297 unasm_initted++; 1298 return (1); 1299 } 1300 1301 1302 1303 /*##################### Functions and Subroutines ##########################*/ 1304 1305 /**************************************/ 1306 /* Miscellaneous Disassembly Routines */ 1307 /**************************************/ 1308 1309 /* Add instructions */ 1310 int 1311 addDasm(i, ofs, w) 1312 const struct inst *i; 1313 OFS ofs; 1314 union insn w; 1315 { 1316 db_printf("%s\t%%r%d,%%r%d,%%r%d",addDCond(Cond4(w)), 1317 Rsa(w),Rsb(w),Rtc(w)); 1318 return (1); 1319 } 1320 1321 /* Unit instructions */ 1322 int 1323 unitDasm(i, ofs, w) 1324 const struct inst *i; 1325 OFS ofs; 1326 union insn w; 1327 { 1328 db_printf(unitDCond(Cond4(w))); 1329 if (Match("dcor") || Match("idcor")) 1330 db_printf("\t%%r%d,%%r%d",Rsb(w),Rtc(w)); 1331 else 1332 db_printf("\t%%r%d,%%r%d,%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1333 return (1); 1334 } 1335 1336 /* Immediate Arithmetic instructions */ 1337 int 1338 iaDasm(i, ofs, w) 1339 const struct inst *i; 1340 OFS ofs; 1341 union insn w; 1342 { 1343 if (Match("addi")) 1344 db_printf("%s\t%d,%%r%d,%%r%d", 1345 addDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1346 else 1347 db_printf("%s\t%d,%%r%d,%%r%d", 1348 subDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1349 return (1); 1350 } 1351 1352 /* Shift double instructions */ 1353 int 1354 shdDasm(i, ofs, w) 1355 const struct inst *i; 1356 OFS ofs; 1357 union insn w; 1358 { 1359 if (Match("vshd")) 1360 db_printf("%s\t%%r%d,%%r%d,%%r%d", 1361 edDCond(Cond(w)), Rsa(w),Rsb(w),Rtc(w)); 1362 else 1363 db_printf("%s\t%%r%d,%%r%d,%d,%%r%d", 1364 edDCond(Cond(w)),Rsa(w),Rsb(w),31-Imd5(w),Rtc(w)); 1365 return (1); 1366 } 1367 1368 /* Extract instructions */ 1369 int 1370 extrDasm(i, ofs, w) 1371 const struct inst *i; 1372 OFS ofs; 1373 union insn w; 1374 { 1375 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1376 edDCond(Cond(w)),Rsb(w),Imd5(w),32 - Rsc(w),Rta(w)); 1377 return (1); 1378 } 1379 1380 1381 /* Variable extract instructions */ 1382 int 1383 vextrDasm(i, ofs, w) 1384 const struct inst *i; 1385 OFS ofs; 1386 union insn w; 1387 { 1388 db_printf("%s\t%%r%d,%d,%%r%d", 1389 edDCond(Cond(w)),Rsb(w),32 - Rsc(w),Rta(w)); 1390 return (1); 1391 } 1392 1393 1394 /* Deposit instructions */ 1395 int 1396 depDasm(i, ofs, w) 1397 const struct inst *i; 1398 OFS ofs; 1399 union insn w; 1400 { 1401 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1402 edDCond(Cond(w)),Rsa(w),31 - Imd5(w),32 - Rsc(w),Rtb(w)); 1403 return (1); 1404 } 1405 1406 1407 /* Variable deposit instructions */ 1408 int 1409 vdepDasm(i, ofs, w) 1410 const struct inst *i; 1411 OFS ofs; 1412 union insn w; 1413 { 1414 db_printf("%s\t%%r%d,%d,%%r%d", 1415 edDCond(Cond(w)),Rsa(w),32 - Rsc(w),Rtb(w)); 1416 return (1); 1417 } 1418 1419 1420 /* Deposit Immediate instructions */ 1421 int 1422 depiDasm(i, ofs, w) 1423 const struct inst *i; 1424 OFS ofs; 1425 union insn w; 1426 { 1427 db_printf("%s\t%d,%d,%d,%%r%d", 1428 edDCond(Cond(w)),Ima5(w),31 - Imd5(w),32 - Imc5A(w),Rtb(w)); 1429 return (1); 1430 } 1431 1432 /* Variable Deposit Immediate instructions */ 1433 int 1434 vdepiDasm(i, ofs, w) 1435 const struct inst *i; 1436 OFS ofs; 1437 union insn w; 1438 { 1439 db_printf("%s\t%d,%d,%%r%d",edDCond(Cond(w)),Ima5(w),32-Imc5A(w),Rtb(w)); 1440 return (1); 1441 } 1442 1443 /*--------------------------------------------------------------------------- 1444 * conditionType$DisassembleCondition - Return a string which contains the 1445 * ascii description of the passed numeric condition. 1446 *---------------------------------------------------------------------------*/ 1447 1448 char * 1449 subDCond(cond) 1450 u_int cond; 1451 { 1452 switch(cond) { 1453 case EQZ: return(",="); 1454 case LT: return(",<"); 1455 case LE: return(",<="); 1456 case LLT: return(",<<"); 1457 case LLE: return(",<<="); 1458 case SV: return(",sv"); 1459 case OD: return(",od"); 1460 case NEQZ: return(",<>"); 1461 case GE: return(",>="); 1462 case GT: return(",>"); 1463 case LGE: return(",>>="); 1464 case LGT: return(",>>"); 1465 case NSV: return(",nsv"); 1466 case EV: return(",ev"); 1467 case TR: return(",tr"); 1468 case NEV: return(""); 1469 default: 1470 panic("subDCond: unknown condition"); 1471 } 1472 } 1473 1474 1475 /*--------------------------------------------------------------------------- 1476 * conditionType$DisassembleCondition - Return a string which contains the 1477 * ascii description of the passed numeric condition. 1478 *---------------------------------------------------------------------------*/ 1479 1480 char * 1481 addDCond(cond) 1482 u_int cond; 1483 { 1484 switch(cond) { 1485 case EQZ: return(",="); 1486 case LT: return(",<"); 1487 case LE: return(",<="); 1488 case NUV: return(",nuv"); 1489 case ZNV: return(",znv"); 1490 case SV: return(",sv"); 1491 case OD: return(",od"); 1492 case NEQZ: return(",<>"); 1493 case GE: return(",>="); 1494 case GT: return(",>"); 1495 case UV: return(",uv"); 1496 case VNZ: return(",vnz"); 1497 case NSV: return(",nsv"); 1498 case EV: return(",ev"); 1499 case TR: return(",tr"); 1500 case NEV: return(""); 1501 default: 1502 panic("addDCond: unknown condition"); 1503 } 1504 } 1505 1506 char * 1507 unitDCond(cond) 1508 u_int cond; 1509 { 1510 switch(cond) { 1511 case SHC: return(",shc"); 1512 case SHZ: return(",shz"); 1513 case SBC: return(",sbc"); 1514 case SBZ: return(",sbz"); 1515 case SDC: return(",sdc"); 1516 case NHC: return(",nhc"); 1517 case NHZ: return(",nhz"); 1518 case NBC: return(",nbc"); 1519 case NBZ: return(",nbz"); 1520 case NDC: return(",ndc"); 1521 case TR: return(",tr"); 1522 case NEV: return(""); 1523 default: 1524 panic("unitDCond: unknown condition"); 1525 } 1526 } 1527 1528 char * 1529 edDCond(cond) 1530 u_int cond; 1531 { 1532 switch(cond) { 1533 case XOD: return(",od"); 1534 case XTR: return(",tr"); 1535 case XNE: return(",<>"); 1536 case XLT: return(",<"); 1537 case XEQ: return(",="); 1538 case XGE: return(",>="); 1539 case XEV: return(",ev"); 1540 case NEV: return(""); 1541 default: 1542 panic("edDCond: unknown condition"); 1543 } 1544 } 1545 1546 1547 1548 /****************************************/ 1549 /* Format Specific Disassembly Routines */ 1550 /****************************************/ 1551 1552 1553 /* Load [modify] instructions */ 1554 int 1555 ldDasm(i, ofs, w) 1556 const struct inst *i; 1557 OFS ofs; 1558 union insn w; 1559 { 1560 int d = Disp(w); 1561 char s[2]; 1562 1563 s[1] = '\0'; 1564 if (d < 0) { 1565 d = -d; 1566 s[0] = '-'; 1567 } else 1568 s[0] = '\0'; 1569 1570 if (Rsb(w) == 0 && Match("ldo")) { 1571 db_printf("ldi\t%s%X,%%r%d",s,d,Rta(w)); 1572 return (1); 1573 } 1574 db_printf("%s\t%s%s%X",i->mnem,(d < 2048? "R'":""), s, d); 1575 if (Dss(w)) 1576 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rta(w)); 1577 else 1578 db_printf("(%%r%d),%%r%d",Rsb(w),Rta(w)); 1579 return (1); 1580 } 1581 1582 /* Store [modify] instructions */ 1583 int 1584 stDasm(i, ofs, w) 1585 const struct inst *i; 1586 OFS ofs; 1587 union insn w; 1588 { 1589 int d = Disp(w); 1590 char s[2]; 1591 1592 db_printf("\t%%r%d,",Rta(w)); 1593 1594 s[1] = '\0'; 1595 if (d < 0) { 1596 d = -d; 1597 s[0] = '-'; 1598 } else 1599 s[0] = '\0'; 1600 1601 db_printf("%s%s%X", (d < 2048? "R'":""), s, d); 1602 1603 if (Dss(w)) 1604 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 1605 else 1606 db_printf("(%%r%d)",Rsb(w)); 1607 return (1); 1608 } 1609 1610 /* Load indexed instructions */ 1611 int 1612 ldxDasm(i, ofs, w) 1613 const struct inst *i; 1614 OFS ofs; 1615 union insn w; 1616 { 1617 const char *p; 1618 1619 if (ShortDisp(w)) { 1620 db_printf("s"); 1621 if (Modify(w)) 1622 db_printf(",m%s", ModBefore(w)? "b": "a"); 1623 } else { 1624 db_printf("x"); 1625 if (Modify(w)) 1626 db_printf(",%sm", IndxShft(w)? "s":""); 1627 } 1628 switch (CacheCtrl(w)) { 1629 default: 1630 case NOACTION: p = ""; break; 1631 case STACKREF: p = ",c"; break; 1632 case SEQPASS: p = ",q"; break; 1633 case PREFETCH: p = ",p"; break; 1634 } 1635 if (ShortDisp(w)) 1636 db_printf("%s\t%d", p, Ima5(w)); 1637 else 1638 db_printf("%s\t%%r%d", p, Rsa(w)); 1639 1640 if (Dss(w)) 1641 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1642 else 1643 db_printf("(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1644 return (1); 1645 } 1646 1647 /* Store short displacement instructions */ 1648 int 1649 stsDasm(i, ofs, w) 1650 const struct inst *i; 1651 OFS ofs; 1652 union insn w; 1653 { 1654 const char *p; 1655 if (Modify(w)) 1656 db_printf(",m%s", ModBefore(w)? "b":"a"); 1657 1658 switch (CacheCtrl(w)) { 1659 default: 1660 case NOACTION: p = ""; break; 1661 case STACKREF: p = ",c"; break; 1662 case SEQPASS: p = ",q"; break; 1663 case PREFETCH: p = ",p"; break; 1664 } 1665 db_printf("%s\t%%r%d,", p, Rta(w)); 1666 if (Dss(w)) 1667 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1668 else 1669 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1670 return (1); 1671 } 1672 1673 /* Store Bytes Instruction */ 1674 int 1675 stbysDasm(i, ofs, w) 1676 const struct inst *i; 1677 OFS ofs; 1678 union insn w; 1679 { 1680 const char *p; 1681 db_printf(ModBefore(w)? ",e":",b"); 1682 if (Modify(w)) 1683 db_printf(",m"); 1684 switch (CacheCtrl(w)) { 1685 default: 1686 case NOACTION: p = ""; break; 1687 case STACKREF: p = ",f"; break; 1688 case SEQPASS: p = ",r"; break; 1689 case PREFETCH: p = ",z"; break; 1690 } 1691 db_printf("%s\t%%r%d,", p, Rta(w)); 1692 if (Dss(w)) 1693 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1694 else 1695 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1696 return (1); 1697 } 1698 1699 /* Long Immediate instructions */ 1700 int 1701 limmDasm(i, ofs, w) 1702 const struct inst *i; 1703 OFS ofs; 1704 union insn w; 1705 { 1706 db_printf("\tL'%X,%%r%d", Im21(w), Rtb(w)); 1707 return (1); 1708 } 1709 1710 1711 /* Branch and Link instruction(s) (Branch, too!!) */ 1712 int 1713 blDasm(i, ofs, w) 1714 const struct inst *i; 1715 OFS ofs; 1716 union insn w; 1717 { 1718 OFS tgtofs = ofs + 8 + Bdisp(w); 1719 u_int link = Rtb(w); 1720 1721 if (link && !Match("gate")) 1722 db_printf("l"); 1723 if (Nu(w)) 1724 db_printf(",n"); 1725 db_printf("\t"); 1726 1727 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1728 1729 if (link || Match("gate")) 1730 db_printf(",%%r%d",link); 1731 1732 return (1); 1733 } 1734 1735 /* Branch Register instruction */ 1736 int 1737 brDasm(i, ofs, w) 1738 const struct inst *i; 1739 OFS ofs; 1740 union insn w; 1741 { 1742 db_printf("%s\t%%r%d,%%r%d", Nu(w)?",n":"", Rsa(w), Rtb(w)); 1743 return (1); 1744 } 1745 1746 /* Dispatch instructions */ 1747 int 1748 bvDasm(i, ofs, w) 1749 const struct inst *i; 1750 OFS ofs; 1751 union insn w; 1752 { 1753 db_printf("%s\t%%r%d(%%r%d)", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1754 return (1); 1755 } 1756 1757 /* Branch External instructions */ 1758 int 1759 beDasm(i, ofs, w) 1760 const struct inst *i; 1761 OFS ofs; 1762 union insn w; 1763 { 1764 int d = Bdisp(w); 1765 const char *p; 1766 char s[2]; 1767 1768 s[1] = '\0'; 1769 if (d < 0) { 1770 d = -d; 1771 s[0] = '-'; 1772 } else 1773 s[0] = '\0'; 1774 1775 p = Nu(w)? ",n":""; 1776 db_printf("%s\tR'%s%X(%%sr%d,%%r%d)", p, 1777 s, d, Sr(w), Rsb(w)); 1778 return (1); 1779 } 1780 1781 1782 /* Compare/Add and Branch instructions */ 1783 int 1784 cbDasm(i, ofs, w) 1785 const struct inst *i; 1786 OFS ofs; 1787 union insn w; 1788 { 1789 OFS tgtofs = ofs + 8 + Cbdisp(w); 1790 1791 if (Match("movb")) 1792 db_printf(edDCond(Cond(w))); 1793 else if (Match("addb")) 1794 db_printf(addDCond(Cond(w) << 1)); 1795 else 1796 db_printf(subDCond(Cond(w) << 1)); 1797 db_printf("%s\t%%r%d,%%r%d,", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1798 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1799 return (1); 1800 } 1801 1802 /* Compare/Add and Branch Immediate instructions */ 1803 int 1804 cbiDasm(i, ofs, w) 1805 const struct inst *i; 1806 OFS ofs; 1807 union insn w; 1808 { 1809 OFS tgtofs = ofs + 8 + Cbdisp(w); 1810 1811 if (Match("movib")) 1812 db_printf(edDCond(Cond(w))); 1813 else if (Match("addib")) 1814 db_printf(addDCond(Cond(w) << 1)); 1815 else 1816 db_printf(subDCond(Cond(w) << 1)); 1817 db_printf("%s\t%d,%%r%d,", Nu(w)? ",n":"", Ima5(w), Rsb(w)); 1818 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1819 return (1); 1820 } 1821 1822 /* Branch on Bit instructions */ 1823 int 1824 bbDasm(i, ofs, w) 1825 const struct inst *i; 1826 OFS ofs; 1827 union insn w; 1828 { 1829 OFS tgtofs = ofs + 8 + Cbdisp(w); 1830 const char *p; 1831 1832 db_printf(edDCond(Cond(w))); 1833 p = Nu(w)? ",n":""; 1834 if (Match("bvb")) 1835 db_printf("%s\t%%r%d,", p, Rta(w)); 1836 else 1837 db_printf("%s\t%%r%d,%d,", p, Rsa(w), Imb5(w)); 1838 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1839 return (1); 1840 } 1841 1842 /* Arithmetic instructions */ 1843 int 1844 ariDasm(i, ofs, w) 1845 const struct inst *i; 1846 OFS ofs; 1847 union insn w; 1848 { 1849 if (Match("or") && Rsb(w) == 0 && Cond4(w) == NEV) { 1850 if (Rsa(w) == 0 && Rtc(w) == 0) 1851 db_printf("nop"); 1852 else 1853 db_printf("copy\t%%r%d,%%r%d",Rsa(w),Rtc(w)); 1854 } else 1855 db_printf("%s%s\t%%r%d,%%r%d,%%r%d", i->mnem, 1856 subDCond(Cond4(w)), Rsa(w),Rsb(w),Rtc(w)); 1857 return(1); 1858 } 1859 1860 /* System control operations */ 1861 int 1862 scDasm(i, ofs, w) 1863 const struct inst *i; 1864 OFS ofs; 1865 union insn w; 1866 { 1867 if (Match("mtctl")) { 1868 if (Rtb(w) == 11) 1869 db_printf("mtsar\t%%r%d",Rsa(w)); 1870 else 1871 db_printf("mtctl\t%%r%d,%%cr%d",Rsa(w),Rtb(w)); 1872 return (1); 1873 } 1874 db_printf(i->mnem); 1875 if (Match("ssm") || Match("rsm")) 1876 db_printf("\t%d,%%r%d",Ima5A(w),Rtc(w)); 1877 else if (Match("mtsm")) db_printf("\t%%r%d",Rsa(w)); 1878 else if (Match("ldprid")) db_printf("\t%%r%d",Rtc(w)); 1879 else if (Match("mtsp")) db_printf("\t%%r%d,%%sr%d",Rsa(w),Sr(w)); 1880 else if (Match("mfsp")) db_printf("\t%%sr%d,%%r%d",Sr(w),Rtc(w)); 1881 else if (Match("mfctl")) db_printf("\t%%cr%d,%%r%d",Rsb(w),Rtc(w)); 1882 else if (Match("ldsid")) { 1883 if (Dss(w)) 1884 db_printf("\t(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1885 else 1886 db_printf("\t(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1887 } else { 1888 db_printf("?????"); 1889 return (0); 1890 } 1891 return (1); 1892 } 1893 1894 /* Instruction cache/tlb control instructions */ 1895 int 1896 mmgtDasm(i, ofs, w) 1897 const struct inst *i; 1898 OFS ofs; 1899 union insn w; 1900 { 1901 if (Match("probe")) { 1902 if (ProbeI(w)) { 1903 if (Dss(w)) 1904 db_printf("i\t(%%sr%d,%%r%d),%d,%%r%d", 1905 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1906 else 1907 db_printf("i\t(%%r%d),%d,%%r%d", 1908 Rsb(w),Rsa(w),Rtc(w)); 1909 } else { 1910 if (Dss(w)) 1911 db_printf("\t(%%sr%d,%%r%d),%%r%d,%%r%d", 1912 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1913 else 1914 db_printf("\t(%%r%d),%%r%d,%%r%d", 1915 Rsb(w),Rsa(w),Rtc(w)); 1916 } 1917 } 1918 else if (Match("lha") || Match("lpa")) { 1919 if (Modify(w)) 1920 db_printf(",m"); 1921 if (Dss(w)) 1922 db_printf("\t%%r%d(%%sr%d,%%r%d),%%r%d", 1923 Rsa(w),Dss(w),Rsb(w),Rtc(w)); 1924 else 1925 db_printf("\t%%r%d(%%r%d),%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1926 } 1927 else if (Match("pdtlb") || Match("pdc") || Match("fdc")) { 1928 if (Modify(w)) db_printf(",m"); 1929 if (Dss(w)) 1930 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1931 else 1932 db_printf("\t%%r%d(%%r%d)",Rsa(w),Rsb(w)); 1933 } 1934 else if (Match("pitlb") || Match("fic")) { 1935 if (Modify(w)) 1936 db_printf(",m"); 1937 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1938 } 1939 else if (Match("idtlb")) { 1940 if (Dss(w)) 1941 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1942 else 1943 db_printf("\t%%r%d,(%%r%d)",Rsa(w),Rsb(w)); 1944 } 1945 else if (Match("iitlb")) 1946 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1947 else { 1948 db_printf("?????"); 1949 return (0); 1950 } 1951 return(1); 1952 } 1953 1954 /* break instruction */ 1955 int 1956 brkDasm(i, ofs, w) 1957 const struct inst *i; 1958 OFS ofs; 1959 union insn w; 1960 { 1961 db_printf("\t%d,%d",Bi1(w),Bi2(w)); 1962 return (1); 1963 } 1964 1965 int 1966 floatDasm(i, ofs, w) 1967 const struct inst *i; 1968 OFS ofs; 1969 union insn w; 1970 { 1971 u_int op1, r1, fmt, t; 1972 u_int op2, r2, dfmt; 1973 char *p; 1974 1975 op1 = CoprExt1(w); 1976 op2 = CoprExt2(w); 1977 fmt = (op1 >> 2) & 3; /* get precision of source */ 1978 1979 #define ST(r) ((fmt & 1)? fdreg[(r)]:fsreg[(r)]) 1980 /* 1981 * get first (or only) source register 1982 * (independent of class) 1983 */ 1984 r1 = (op1 >> 11) & 0x3e; 1985 if ((fmt & 1) == 0 && (Uid(w) & 2)) 1986 r1++; 1987 1988 if (op1 & 2) { /* class 2 or 3 */ 1989 /* 1990 * get second source register 1991 */ 1992 r2 = (op1 >> 6) & 0x3e; 1993 if (fmt == 2) 1994 r2++; 1995 1996 if ((op1 & 1) == 0) { /* class 2 */ 1997 /* Opclass 2: 2 sources, no destination */ 1998 switch((op1 >> 4) & 7) { 1999 case 0: 2000 p = "cmp"; 2001 break; 2002 default: 2003 db_printf(fcoprUndef); 2004 return(0); 2005 } 2006 db_printf("%s,%s",p,fmtStrTbl[fmt]); 2007 db_printf(",%s\t%%f%s,%%f%s", 2008 condStrTbl[op2], ST(r1), ST(r2)); 2009 return (1); 2010 } 2011 /* 2012 * get target register (class 3) 2013 */ 2014 t = (op2 << 1); 2015 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2016 t++; 2017 /* Opclass 3: 2 sources, 1 destination */ 2018 switch((op1 >> 4) & 7) { 2019 case 0: p = "add"; break; 2020 case 1: p = "sub"; break; 2021 case 2: p = (Fpi(w)) ? "mpyi" : "mpy"; break; 2022 case 3: p = "div"; break; 2023 case 4: p = "rem"; break; 2024 default: db_printf(fcoprUndef); return (0); 2025 } 2026 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2027 db_printf("\t%%f%s,%%f%s,%%f%s",ST(r1),ST(r2),ST(t)); 2028 } else if (op1 & 1) { /* class 1 */ 2029 dfmt = (op1 >> 4) & 3; 2030 #define DT(r) ((dfmt & 1)? fdreg[(r)]:fsreg[(r)]) 2031 2032 /* 2033 * get target register 2034 */ 2035 t = (op2 << 1); 2036 if ((dfmt & 1) == 0 && (Uid(w) & 1)) 2037 t++; 2038 /* Opclass 1: 1 source, 1 destination conversions */ 2039 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 2040 #if 0 2041 switch((op1 >> 6) & 3) { 2042 default: 2043 case 0: p = "ff"; break; 2044 case 1: p = "xf"; break; 2045 case 2: p = "fx"; break; 2046 case 3: p = "fxt"; break; 2047 } 2048 #endif 2049 db_printf("%s,%s", p, fmtStrTbl[fmt]); 2050 db_printf(",%s\t%%f%s,%%f%s",fmtStrTbl[dfmt],ST(r1),DT(t)); 2051 } else { /* class 0 */ 2052 /* 2053 * get target register 2054 */ 2055 t = (op2 << 1); 2056 if ((fmt & 1) == 0 && (Uid(w) & 1)) 2057 t++; 2058 /* Opclass 0: 1 source, 1 destination */ 2059 switch((op1 >> 4) & 7) { 2060 case 1: p = "rsqrt"; break; 2061 case 2: p = "cpy"; break; 2062 case 3: p = "abs"; break; 2063 case 4: p = "sqrt"; break; 2064 case 5: p = "rnd"; break; 2065 default: db_printf(fcoprUndef); return (0); 2066 } 2067 db_printf("%s,%s",p,fmtStrTbl[fmt]); 2068 db_printf("\t%%f%s,%%f%s",ST(r1),ST(t)); 2069 } 2070 return (1); 2071 } 2072 2073 int 2074 fcoprDasm(w, op1, op2) 2075 union insn w; 2076 u_int op1, op2; 2077 { 2078 u_int r1, r2, t, fmt, dfmt; 2079 char *p; 2080 2081 if (AstNu(w) && op1 == ((1<<4) | 2)) { 2082 if (op2 == 0 || op2 == 1 || op2 == 2) { 2083 db_printf("ftest"); 2084 if (op2 == 1) 2085 db_printf(",acc"); 2086 else if (op2 == 2) 2087 db_printf(",rej"); 2088 return (1); 2089 } 2090 return (0); 2091 } else if (0 == op1 && 0 == op2) { 2092 db_printf("fcopr identify"); 2093 return (1); 2094 } 2095 switch(op1 & 3) { 2096 case 0: 2097 /* Opclass 0: 1 source, 1 destination */ 2098 r1 = (op1 >> 12) & 0x1f; t = op2; fmt = (op1 >> 2) & 3; 2099 switch((op1 >> 4) & 7) { 2100 case 1: p = "rsqrt"; break; 2101 case 2: p = "cpy"; break; 2102 case 3: p = "abs"; break; 2103 case 4: p = "sqrt"; break; 2104 case 5: p = "rnd"; break; 2105 default: db_printf(fcoprUndef); return(0); 2106 } 2107 db_printf("f%s,%s\t%%fr%d,%%fr%d", p, fmtStrTbl[fmt], r1, t); 2108 break; 2109 case 1: 2110 /* Opclass 1: 1 source, 1 destination conversions */ 2111 r1 = (op1 >> 12) & 0x1f; t = op2; 2112 fmt = (op1 >> 2) & 3; dfmt = (op1 >> 4) & 3; 2113 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 2114 #if 0 2115 switch((op1 >> 6) & 3) { 2116 case 0: p = "ff"; break; 2117 case 1: p = "xf"; break; 2118 case 2: p = "fx"; break; 2119 case 3: p = "fxt"; break; 2120 } 2121 #endif 2122 db_printf("fcnv%s,%s,%s\t%%fr%d,%%fr%d", 2123 p, fmtStrTbl[fmt], fmtStrTbl[dfmt], r1, t); 2124 break; 2125 case 2: 2126 /* Opclass 2: 2 sources, no destination */ 2127 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; 2128 fmt = (op1 >> 2) & 3; 2129 switch((op1 >> 4) & 7) { 2130 case 0: p = "fcmp"; break; 2131 default: db_printf(fcoprUndef); return (0); 2132 } 2133 db_printf("%s,%s,%s\t%%fr%d,%%fr%d", 2134 p,fmtStrTbl[fmt],condStrTbl[op2],r1,r2); 2135 break; 2136 case 3: 2137 /* Opclass 3: 2 sources, 1 destination */ 2138 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; t = op2; 2139 fmt = (op1 >> 2) & 3; 2140 switch((op1 >> 4) & 7) { 2141 case 0: p = "add"; break; 2142 case 1: p = "sub"; break; 2143 case 2: p = "mpy"; break; 2144 case 3: p = "div"; break; 2145 case 4: p = "rem"; break; 2146 default: db_printf(fcoprUndef); return (0); 2147 } 2148 db_printf("f%s,%s\t%%fr%d,%%fr%d,%%fr%d", 2149 p, fmtStrTbl[fmt], r1, r2, t); 2150 break; 2151 default: 2152 db_printf(fcoprUndef); 2153 return(0); 2154 } 2155 return (1); 2156 } 2157 2158 int 2159 coprDasm(i, ofs, w) 2160 const struct inst *i; 2161 OFS ofs; 2162 union insn w; 2163 { 2164 u_int uid = Uid(w); 2165 int load = 0; 2166 char *pfx = uid > 1 ? "c" : "f"; 2167 int dreg = 0; 2168 2169 if (Match("copr")) { 2170 if (uid) { 2171 db_printf("copr,%d,0x%x",uid,CoprExt(w)); 2172 if (AstNu(w)) 2173 db_printf(",n"); 2174 return (1); 2175 } 2176 return fcoprDasm(w, CoprExt1(w),CoprExt2(w)); 2177 } 2178 if (Match("cldd")) { 2179 dreg = 1; 2180 load = 1; 2181 db_printf("%sldd",pfx); 2182 } else if (Match("cldw")) { 2183 load = 1; 2184 db_printf("%sldw",pfx); 2185 } else if (Match("cstd")) { 2186 dreg = 1; 2187 db_printf("%sstd",pfx); 2188 } else if (Match("cstw")) 2189 db_printf("%sstw",pfx); 2190 else { 2191 db_printf("copr???"); 2192 return (0); 2193 } 2194 if (ShortDisp(w)) { 2195 db_printf("s"); 2196 if (AstNu(w)) 2197 db_printf(",m%s", ModBefore(w)?"b":"a"); 2198 } 2199 else { 2200 db_printf("x"); 2201 if (AstNu(w)) 2202 db_printf(",%sm", IndxShft(w)?"s":""); 2203 else if (IndxShft(w)) 2204 db_printf(",s"); 2205 } 2206 switch (CacheCtrl(w)) { 2207 case NOACTION: break; 2208 case STACKREF: db_printf(",c"); break; 2209 case SEQPASS: db_printf(",q"); break; 2210 case PREFETCH: db_printf(",p"); break; 2211 } 2212 if (load) { 2213 const char *p; 2214 2215 if (dreg) 2216 p = fdreg[(Rtc(w)<<1)+(uid&1)]; 2217 else 2218 p = fsreg[(Rtc(w)<<1)+(uid&1)]; 2219 2220 if (ShortDisp(w)) 2221 db_printf("\t%d",Ima5(w)); 2222 else 2223 db_printf("\t%%r%d",Rsa(w)); 2224 if (Dss(w)) 2225 db_printf("(%%sr%d,%%r%d),%%f%s", Dss(w),Rsb(w), p); 2226 else 2227 db_printf("(%%r%d),%%f%s",Rsb(w), p); 2228 } else { 2229 const char *p; 2230 2231 if (dreg) 2232 p = fdreg[(Rsc(w)<<1)+(uid&1)]; 2233 else 2234 p = fsreg[(Rsc(w)<<1)+(uid&1)]; 2235 2236 if (ShortDisp(w)) 2237 db_printf("\t%%f%s,%d", p, Ima5(w)); 2238 else 2239 db_printf("\t%%f%s,%%r%d", p, Rta(w)); 2240 if (Dss(w)) 2241 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2242 else 2243 db_printf("(%%r%d)",Rsb(w)); 2244 } 2245 return (1); 2246 } 2247 2248 int 2249 lpkDasm(i, ofs, w) 2250 const struct inst *i; 2251 OFS ofs; 2252 union insn w; 2253 { 2254 /* 2255 * Floating point STore Quad 2256 * Short or Indexed 2257 */ 2258 if (ShortDisp(w)) { 2259 if (Modify(w)) 2260 db_printf(",m%s", ModBefore(w)?"b":"a"); 2261 } else { 2262 if (Modify(w)) 2263 db_printf(",%sm", IndxShft(w)? "s":""); 2264 else if (IndxShft(w)) 2265 db_printf(",s"); 2266 } 2267 switch (CacheCtrl(w)) { 2268 case NOACTION: break; 2269 case STACKREF: db_printf(",c"); break; 2270 case SEQPASS: db_printf(",q"); break; 2271 case PREFETCH: db_printf(",p"); break; 2272 } 2273 if (ShortDisp(w)) 2274 db_printf("\t%%fr%d,%d",Rsc(w),Ima5(w)); 2275 else 2276 db_printf("\t%%fr%d,%%r%d",Rsc(w),Rta(w)); 2277 if (Dss(w)) 2278 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2279 else 2280 db_printf("(%%r%d)",Rsb(w)); 2281 return (1); 2282 } 2283 2284 int 2285 diagDasm(i, ofs, w) 2286 const struct inst *i; 2287 OFS ofs; 2288 union insn w; 2289 { 2290 if (0x0b0 == BitfR(w,19,8,_b198)) /* mtcpu */ 2291 db_printf("mtcpu\t%%r%d,%%dr%d", Rsa(w), Rtb(w)); 2292 else if (0x0d0 == BitfR(w,19,8,_b198)) /* mfcpu */ 2293 db_printf("mfcpu\t%%dr%d,%%r%d", Rsb(w), Rta(w)); 2294 else { 2295 db_printf(i->mnem); 2296 if (Match("diag")) 2297 db_printf("\t0x%X",w.w & 0x03ffffff); 2298 else { 2299 db_printf("?????"); 2300 return (0); 2301 } 2302 } 2303 return (1); 2304 } 2305 2306 int 2307 fmpysubDasm(i, ofs, w) 2308 const struct inst *i; 2309 OFS ofs; 2310 union insn w; 2311 { 2312 if (SinglePrec(w)) 2313 db_printf("SUB,SGL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2314 fsreg[Ms1(w)], fsreg[Ms2(w)], fsreg[Mt(w)], 2315 fsreg[As(w)], fsreg[Ad(w)]); 2316 else 2317 db_printf("SUB,DBL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2318 fdreg[Ms1(w)], fdreg[Ms2(w)], fdreg[Mt(w)], 2319 fdreg[As(w)], fdreg[Ad(w)]); 2320 return (1); 2321 } 2322 2323 int 2324 fmpyaddDasm(i, ofs, w) 2325 const struct inst *i; 2326 OFS ofs; 2327 union insn w; 2328 { 2329 const char 2330 *ms1 = SinglePrec(w) ? fsreg[Ms1(w)] : fdreg[Ms1(w)], 2331 *ms2 = SinglePrec(w) ? fsreg[Ms2(w)] : fdreg[Ms2(w)], 2332 *mt = SinglePrec(w) ? fsreg[Mt(w)] : fdreg[Mt(w)], 2333 *as = SinglePrec(w) ? fsreg[As(w)] : fdreg[As(w)], 2334 *ad = SinglePrec(w) ? fsreg[Ad(w)] : fdreg[Ad(w)]; 2335 2336 if (Rsd(w) == 0) 2337 db_printf("\t%%fcfxt,%s,%%f%s,%%f%s,%%f%s", 2338 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt); 2339 else 2340 db_printf("add%s\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2341 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt, as, ad); 2342 2343 return (1); 2344 } 2345 2346 vaddr_t 2347 db_disasm(loc, flag) 2348 vaddr_t loc; 2349 boolean_t flag; 2350 { 2351 const struct inst *i; 2352 const struct majoropcode *m; 2353 u_int ext; 2354 union insn instruct; 2355 OFS ofs = 0; 2356 2357 iExInit(); 2358 2359 if (USERMODE(loc)) { 2360 if (copyin((caddr_t)(loc &~ HPPA_PC_PRIV_MASK), 2361 &instruct, sizeof(instruct))) 2362 instruct.w = 0; 2363 } else 2364 instruct.w = *(int *)loc; 2365 2366 m = &majopcs[Opcode(instruct)]; 2367 ext = OpExt(instruct.w, m); 2368 if (ext <= m->maxsubop) { 2369 /* special hack for majopcs table layout */ 2370 if (m->maxsubop == 1) 2371 i = (const struct inst *)m->subops; 2372 else 2373 i = m->subops[ext]; 2374 2375 if (i->dasmfcn != coprDasm && i->dasmfcn != diagDasm && 2376 i->dasmfcn != ariDasm && i->dasmfcn != scDasm && 2377 i->dasmfcn != ldDasm) 2378 db_printf(i->mnem); 2379 if (i->dasmfcn) 2380 (*i->dasmfcn)(i, ofs, instruct); 2381 else if (i->mnem[0] == '?') 2382 db_printf(illeg.mnem); 2383 } else 2384 db_printf(illeg.mnem); 2385 2386 db_printf("\n"); 2387 return (loc + sizeof(instruct)); 2388 } 2389
Indexes created Mon Sep 29 15:09:53 GMT 2025