db_disasm.c revision 1.5
1 /* $NetBSD: db_disasm.c,v 1.5 2003/11/28 19:02:25 chs Exp $ */ 2 3 /* $OpenBSD: db_disasm.c,v 1.9 2000/04/18 20:02:45 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1999 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Michael Shalayeff. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 /* 35 * (c) Copyright 1992 HEWLETT-PACKARD COMPANY 36 * 37 * To anyone who acknowledges that this file is provided "AS IS" 38 * without any express or implied warranty: 39 * permission to use, copy, modify, and distribute this file 40 * for any purpose is hereby granted without fee, provided that 41 * the above copyright notice and this notice appears in all 42 * copies, and that the name of Hewlett-Packard Company not be 43 * used in advertising or publicity pertaining to distribution 44 * of the software without specific, written prior permission. 45 * Hewlett-Packard Company makes no representations about the 46 * suitability of this software for any purpose. 47 */ 48 49 /* 50 * unasm.c -- HP_PA Instruction Printer 51 */ 52 53 #include <sys/cdefs.h> 54 __KERNEL_RCSID(0, "$NetBSD: db_disasm.c,v 1.5 2003/11/28 19:02:25 chs Exp $"); 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 59 #include <machine/db_machdep.h> 60 #include <ddb/db_access.h> 61 #include <ddb/db_sym.h> 62 #include <ddb/db_output.h> 63 #include <ddb/db_interface.h> 64 65 66 /* IMPORTANT NOTE: 67 * All modules using this header may assume that the datatype "int" is a 68 * 32-bit (or > 32-bit) signed quantity. 69 */ 70 71 72 /* Spectrum Architecturally Defined Datatypes */ 73 struct doubleword { 74 int wd0; 75 int wd1; 76 }; 77 78 struct quadword { 79 struct doubleword d0; 80 struct doubleword d1; 81 }; 82 83 /* datatypes for halfword and byte fields of a word are defined 84 * in ssBits.h */ 85 86 /* Memory addressing datatypes */ 87 typedef unsigned int SID, /* range [0..MAXSID] */ 88 PGID, /* range [0..MAXPGID] */ 89 OFS, /* range [0..MAXINT] */ 90 REALADR; /* range [0..MAXINT] */ 91 92 93 /* data sizes */ 94 enum datasize { Byte, Halfword, Word, Doubleword, Quadword, Variable }; 95 96 /* Miscellaneous datatypes */ 97 typedef unsigned int FLAGS; 98 99 /* struct for entry in unwind table */ 100 struct ute { 101 int word1; 102 int word2; 103 int word3; 104 int word4; 105 }; 106 /* 107 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 108 * 109 * Spectrum Instruction Set Condition Completer Bit Assignments 110 * Dan Magenheimer - 6/14/82 111 * Terrence Miller - 6/21/82 112 * Computer Research Center, Hewlett-Packard Labs 113 * 114 * (c) copyright 1982 115 * (p) protected 1982 116 * The Hewlett-Packard Company 117 * Hewlett-Packard Laboratories 118 * Computer Research Center 119 * Palo Alto, California 120 * 121 * *** HP Company Confidential *** 122 * 123 * Log: unasm.c,v 124 * Revision 1.5 1994/07/21 22:32:05 mike 125 * official HP copyright notice 126 * 127 * Revision 1.4 1992/07/08 12:19:52 dalton 128 * Checkin before split to 1.0.4 release (by LBS). 129 * 130 * Revision 1.3 92/06/06 16:16:45 dalton 131 * *** empty log message *** 132 * 133 * Revision 1.2 92/06/06 15:42:28 dalton 134 * Changed include to be a path relative to hp800. 135 * 136 * Revision 1.1 92/06/06 14:05:33 dalton 137 * Initial revision 138 * 139 * Revision 1.2 91/04/14 20:29:49 osfrcs 140 * Initial version. 141 * [91/03/30 09:20:34 brezak] 142 * 143 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 144 * Initial version. 145 * [91/03/30 09:20:34 brezak] 146 * 147 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 148 * Initial version. 149 * 150 * Revision 1.1 88/07/11 14:05:15 14:05:15 ren (Bob Naas) 151 * Initial revision 152 * 153 * Revision 5.2 87/07/02 14:45:57 14:45:57 kent (Kent McMullen) 154 * added constants to support addDasm and addDCond added to ssDID.c 155 * 156 * Revision 5.1 87/02/27 11:12:08 11:12:08 kent (Kent McMullen) 157 * update all src to 5.1 158 * 159 * Revision 5.0 87/02/18 16:31:15 16:31:15 kent (Kent McMullen) 160 * update all revision numbers to 5.0 for release 161 * 162 * Revision 1.1 86/07/15 08:34:55 08:34:55 kent (Kent McMullen) 163 * Initial revision 164 * 165 * Revision 4.1 83/10/25 17:01:22 17:01:22 djm (Daniel J Magenheimer) 166 * First release for ACD v4 167 * 168 * Revision 3.0 83/06/13 10:22:59 djm (Daniel Magenheimer) 169 * First release for distribution 170 * 171 * 172 */ 173 174 175 /* Arithmetic/Logical Conditions */ 176 #define NEV 0x0 177 #define EQZ 0x2 178 #define LT 0x4 179 #define LE 0x6 180 #define LLT 0x8 181 #define NUV 0x8 182 #define LLE 0xA 183 #define ZNV 0xA 184 #define SV 0xC 185 #define OD 0xE 186 #define TR 0x1 187 #define NEQZ 0x3 188 #define GE 0x5 189 #define GT 0x7 190 #define LGE 0x9 191 #define UV 0x9 192 #define LGT 0xB 193 #define VNZ 0xB 194 #define NSV 0xD 195 #define EV 0xF 196 197 /* unit conditions */ 198 #define SBZ 0x4 199 #define SHZ 0x6 200 #define SDC 0x8 201 #define SBC 0xC 202 #define SHC 0xE 203 #define NBZ 0x5 204 #define NHZ 0x7 205 #define NDC 0x9 206 #define NBC 0xD 207 #define NHC 0xF 208 209 /*field conditions */ 210 #define XEQ 0x1 211 #define XLT 0x2 212 #define XOD 0x3 213 #define XTR 0x4 214 #define XNE 0x5 215 #define XGE 0x6 216 #define XEV 0x7 217 218 219 220 /* 221 * These macros are designed to be portable to all machines that have 222 * a wordsize greater than or equal to 32 bits that support the portable 223 * C compiler and the standard C preprocessor. Wordsize (default 32) 224 * and bitfield assignment (default left-to-right, unlike VAX, PDP-11) 225 * should be predefined using the constants HOSTWDSZ and BITFRL and 226 * the C compiler "-D" flag (e.g., -DHOSTWDSZ=36 -DBITFLR for the DEC-20). 227 * Note that the macro arguments assume that the integer being referenced 228 * is a 32-bit integer (right-justified on the 20) and that bit 0 is the 229 * most significant bit. 230 */ 231 232 #ifndef HOSTWDSZ 233 #define HOSTWDSZ 32 234 #endif 235 236 #ifdef vax 237 #ifndef BITFLR 238 #define BITFRL 239 #endif 240 #else 241 #define BITFLR 242 #endif 243 244 /*########################### Macros ######################################*/ 245 246 /*--------------------------------------------------------------------------- 247 * DeclareBitfield$Reference - Declare a structure to be used to reference 248 * a specified bitfield within an integer (using BitfR, see below). 249 * The argument "n" must be an identifier name not used elsewhere in the 250 * program , "s" and "l" must (alas!) be constants. (Suggestion: if 251 * "s" == 2 and "l" == 8, use _b28 for "n".) The name "BITFLR" should 252 * be pre-defined if the compiler assigns bitfields from left-to-right. 253 * The resultant macro expansion defines a stucture in which the bit field 254 * starting at position "s" with length "l" may be referenced by accessing 255 * member "n". [Note: The leftmost bits in a 36-bit word may be accessed 256 * by specifying -4 <= s < 0 on the DEC-20.] 257 *---------------------------------------------------------------------------*/ 258 259 #ifdef BITFRL 260 #define DeclBitfR(s,l,n) struct n { int:(HOSTWDSZ-(s)-(l)); unsigned n:l;} n; 261 #else 262 #define DeclBitfR(s,l,n) struct n { int:((s)+(HOSTWDSZ-32)); unsigned n:l;} n; 263 #endif 264 265 /*--------------------------------------------------------------------------- 266 * Bitfield$Reference - Reference a specified bitfield within an integer. 267 * The argument "i" must be an addressable variable (i.e., not a register 268 * variable or an expression... but see BitfX below), "n" must be an 269 * identifier name declared in a DeclBitfR invocation. The resultant 270 * macro expansion references the bit field in "i" described by the 271 * DeclBitfR invocation with the same name ("n"). BitfR may be used as 272 * an lvalue or an rvalue. (i.e., either side of an assignment statement) 273 * The "s" and "l" arguments are historical and are now unused. (They 274 * correspond to the "s" and "l" arguments in DeclBitfR) 275 * Translates to a single instruction on both the VAX and the DEC-20. 276 *---------------------------------------------------------------------------*/ 277 #define BitfR(i,s,l,n) (i.n.n) 278 279 /*--------------------------------------------------------------------------- 280 * Bitfield$eXtract - Extract the specified field from an integer. Arguments 281 * are the same as for BitfR (except no "n"), however both "s" and "l" need 282 * no longer be constants. May only be used as an rvalue. Translates to 283 * two instructions on the VAX, three on the DEC-20. 284 *---------------------------------------------------------------------------*/ 285 286 #define BitfX(i,s,l) (((i.w) >> (32-(s)-(l))) & ((1 << (l)) - 1)) 287 288 289 /*--------------------------------------------------------------------------- 290 * Mask$32bits - Mask the low order 32 bits of passed word. No-op on 32 291 * bit machines. 292 *---------------------------------------------------------------------------*/ 293 294 #if HOSTWDSZ > 32 295 #define Mask32(x) ((x) & 0xffffffff) 296 #else 297 #define Mask32(x) (x) 298 #endif 299 300 301 /*--------------------------------------------------------------------------- 302 * SignExtend$32bits - Force the high-order bits in machines with wordsize 303 * longer than 32 to match bit 0. 304 *---------------------------------------------------------------------------*/ 305 306 #if HOSTWDSZ > 32 307 #define SignEx32(x) (((x) & 0x80000000) ? ((x) | ((unsigned)-1 << 32)) \ 308 : Mask32(x)) 309 #else 310 #define SignEx32(x) (x) 311 #endif 312 313 /**************************/ 314 /* bit field declarations */ 315 /**************************/ 316 317 /* since the compiler complains if a structure name is declared twice, even 318 * if the declarations are identical, all DeclBitfR invocations are 319 * given here in one file. */ 320 321 union insn { 322 int w; 323 DeclBitfR(0,1,_b01) 324 DeclBitfR(0,15,_b015) 325 DeclBitfR(0,16,_b016) 326 DeclBitfR(0,4,_b04) 327 DeclBitfR(0,6,_b06) 328 DeclBitfR(0,8,_b08) 329 DeclBitfR(4,1,_b41) 330 DeclBitfR(4,4,_b44) 331 DeclBitfR(6,1,_b61) 332 DeclBitfR(6,13,_b613) 333 DeclBitfR(6,15,_b615) 334 DeclBitfR(6,17,_b617) 335 DeclBitfR(6,26,_b626) 336 DeclBitfR(6,5,_b65) 337 DeclBitfR(7,1,_b71) 338 DeclBitfR(8,1,_b81) 339 DeclBitfR(8,4,_b84) 340 DeclBitfR(8,8,_b88) 341 DeclBitfR(9,1,_b91) 342 DeclBitfR(10,1,_b101) 343 DeclBitfR(11,1,_b111) 344 DeclBitfR(11,10,_b1110) 345 DeclBitfR(11,4,_b114) 346 DeclBitfR(11,5,_b115) 347 DeclBitfR(12,1,_b121) 348 DeclBitfR(12,4,_b124) 349 DeclBitfR(13,1,_b131) 350 DeclBitfR(14,1,_b141) 351 DeclBitfR(15,1,_b151) 352 DeclBitfR(16,1,_b161) 353 DeclBitfR(16,15,_b1615) 354 DeclBitfR(16,16,_b1616) 355 DeclBitfR(16,2,_b162) 356 DeclBitfR(16,3,_b163) 357 DeclBitfR(16,4,_b164) 358 DeclBitfR(16,5,_b165) 359 DeclBitfR(16,8,_b168) 360 DeclBitfR(17,1,_b171) 361 DeclBitfR(18,1,_b181) 362 DeclBitfR(18,13,_b1813) 363 DeclBitfR(18,2,_b182) 364 DeclBitfR(18,7,_b187) 365 DeclBitfR(19,1,_b191) 366 DeclBitfR(19,8,_b198) 367 DeclBitfR(19,10,_b1910) 368 DeclBitfR(20,11,_b2011) 369 DeclBitfR(20,2,_b202) 370 DeclBitfR(20,4,_b204) 371 DeclBitfR(21,10,_b2110) 372 DeclBitfR(21,2,_b212) 373 DeclBitfR(21,5,_b215) 374 DeclBitfR(22,5,_b225) 375 DeclBitfR(23,3,_b233) 376 DeclBitfR(24,1,_b241) 377 DeclBitfR(24,4,_b244) 378 DeclBitfR(24,8,_b248) 379 DeclBitfR(25,1,_b251) 380 DeclBitfR(26,1,_b261) 381 DeclBitfR(27,1,_b271) 382 DeclBitfR(27,4,_b274) 383 DeclBitfR(27,5,_b275) 384 DeclBitfR(28,1,_b281) 385 DeclBitfR(28,4,_b284) 386 DeclBitfR(29,1,_b291) 387 DeclBitfR(30,1,_b301) 388 DeclBitfR(30,2,_b302) 389 DeclBitfR(31,1,_b311) 390 }; 391 392 /******************/ 393 /* Word subfields */ 394 /******************/ 395 396 #define Sign(i) BitfR(i,0,1,_b01) 397 /* halfwords */ 398 #define Hwd0(i) BitfR(i,0,16,_b016) 399 #define Hwd1sign(i) BitfR(i,16,1,_b161) 400 #define Hwd1(i) BitfR(i,16,16,_b1616) 401 /* bytes */ 402 #define Byte0(i) BitfR(i,0,8,_b08) 403 #define Byte1sign(i) BitfR(i,8,1,_b81) 404 #define Byte1(i) BitfR(i,8,8,_b88) 405 #define Byte2(i) BitfR(i,16,8,_b168) 406 #define Byte3sign(i) BitfR(i,24,1,_b241) 407 #define Byte3(i) BitfR(i,24,8,_b248) 408 /* digits */ 409 #define Digit0(i) BitfR(i,0,4,_b04) 410 #define Digit1(i) BitfR(i,4,4,_b44) 411 #define Digit2(i) BitfR(i,8,4,_b84) 412 #define Digit3(i) BitfR(i,12,4,_b124) 413 #define Digit4(i) BitfR(i,16,4,_b164) 414 #define Digit5(i) BitfR(i,20,4,_b204) 415 #define Digit6(i) BitfR(i,24,4,_b244) 416 #define Digit7(i) BitfR(i,28,4,_b284) 417 418 /* Wordsize definitions */ 419 420 #define BIT_P_DW 64 /* bits/doubleword */ 421 #define BIT_P_WD 32 /* bits/word */ 422 #define BIT_P_HW 16 /* bits/halfword */ 423 #define BIT_P_BYT 8 /* bits/byte */ 424 #define BYT_P_DW 8 /* bytes/doubleword */ 425 #define BYT_P_WD 4 /* bytes/word */ 426 #define BYT_P_HW 2 /* bytes/halfword */ 427 428 /* Masks */ 429 430 #define WDMASK 0xffffffff /* 32-bit mask */ 431 #define OFSMASK 0xffffffff /* 32-bit mask */ 432 #define SIDMASK 0xffffffff /* 32-bit mask */ 433 #define SIGNMASK 0x80000000 /* 32 bit word sign bit */ 434 435 /* Alignments */ 436 437 #define wdalign(ofs) (ofs &= ~3) 438 /* 439 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 440 * 441 * Spectrum Simulator Instruction Opcode Definitions 442 * Dan Magenheimer 443 * Computer Research Center, Hewlett-Packard Labs 444 * 445 * (c) copyright 1982 446 * (p) protected 1982 447 * The Hewlett-Packard Company 448 * Hewlett-Packard Laboratories 449 * Computer Research Center 450 * Palo Alto, California 451 * 452 * *** HP Company Confidential *** 453 * 454 * Log: unasm.c,v 455 * Revision 1.5 1994/07/21 22:32:05 mike 456 * official HP copyright notice 457 * 458 * Revision 1.4 1992/07/08 12:19:52 dalton 459 * Checkin before split to 1.0.4 release (by LBS). 460 * 461 * Revision 1.3 92/06/06 16:16:45 dalton 462 * *** empty log message *** 463 * 464 * Revision 1.2 92/06/06 15:42:28 dalton 465 * Changed include to be a path relative to hp800. 466 * 467 * Revision 1.1 92/06/06 14:05:33 dalton 468 * Initial revision 469 * 470 * Revision 1.2 91/04/14 20:29:49 osfrcs 471 * Initial version. 472 * [91/03/30 09:20:34 brezak] 473 * 474 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 475 * Initial version. 476 * [91/03/30 09:20:34 brezak] 477 * 478 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 479 * Initial version. 480 * 481 * Revision 6.1 89/09/06 10:39:58 burroughs 482 * Added shadow registers for gr0-gr7. 483 * gr0-7 are copied into sh0-7 whenever a trap occurs 484 * the instruction RFIR restores gr0-7 from sh0-7 and returns from 485 * interrupt. 486 * the "sh" command displays the shadow registers 487 * = sh7 0x789 works, too. 488 * 489 * Revision 6.0 89/09/01 15:46:37 15:46:37 burroughs (Greg Burroughs) 490 * baseline for pcx simple offsite 491 * 492 * Revision 5.2 87/09/02 14:30:23 14:30:23 kent 493 * separated stat gathering for indexed vs short. 494 * this will NOT work if cache hints ever get used 495 * since this field was assumed always zero 496 * 497 * Revision 5.1 87/02/27 11:12:16 11:12:16 kent (Kent McMullen) 498 * update all src to 5.1 499 * 500 * Revision 5.0 87/02/18 16:31:35 16:31:35 kent (Kent McMullen) 501 * update all revision numbers to 5.0 for release 502 * 503 * Revision 1.1 86/07/15 08:34:57 08:34:57 kent (Kent McMullen) 504 * Initial revision 505 * 506 * Revision 4.1 83/10/25 17:02:34 17:02:34 djm (Daniel J Magenheimer) 507 * First release for ACD v4 508 * 509 * Revision 3.0 83/06/13 10:24:45 djm (Daniel Magenheimer) 510 * First release for distribution 511 * 512 * 513 */ 514 515 /* 516 * Changes: 517 * 01/30/90 ejf Simplify SPOPn support, now only gives assist emulation trap. 518 * 01/19/90 ejf Replace linpak instructions with just FSTQ[SX]. 519 * 12/19/89 ejf Add PA89 new floating point opcode 0E. 520 * 12/18/89 ejf Change 5 ops to PA89 format. 521 * 12/01/89 ejf Move additional instructions fmas, fmaa, fld2, fst2 to ssILst 522 * 09/22/89 ejf Fix unbalanced comments. 523 */ 524 525 526 /* ..and modified by hand to remove the load/store short references */ 527 /* ..and modified by hand to make memory management ops conform to the 528 * requirement that all subops of a major opcode begin in the same 529 * place and have the same length */ 530 531 #define LDW 0x12, 0x00, 0, 0 /* LOAD WORD */ 532 #define LDWM 0x13, 0x00, 0, 0 /* LOAD WORD and MODIFY */ 533 #define LDH 0x11, 0x00, 0, 0 /* LOAD HALFWORD */ 534 #define LDB 0x10, 0x00, 0, 0 /* LOAD BYTE */ 535 #define LDO 0x0d, 0x00, 0, 0 /* LOAD OFFSET */ 536 #define STW 0x1a, 0x00, 0, 0 /* STORE WORD */ 537 #define STWM 0x1b, 0x00, 0, 0 /* STORE WORD and MODIFY */ 538 #define STH 0x19, 0x00, 0, 0 /* STORE HALFWORD */ 539 #define STB 0x18, 0x00, 0, 0 /* STORE BYTE */ 540 #define LDWX 0x03, 0x02, 19, 7 /* LOAD WORD INDEXED */ 541 #define LDHX 0x03, 0x01, 19, 7 /* LOAD HALFWORD INDEXED */ 542 #define LDBX 0x03, 0x00, 19, 7 /* LOAD BYTE INDEXED */ 543 #define LDWAX 0x03, 0x06, 19, 7 /* LOAD WORD ABSOLUTE INDEXED */ 544 #define LDCWX 0x03, 0x07, 19, 7 /* LOAD and CLEAR WORD INDEXED */ 545 #define LDWS 0x03, 0x42, 19, 7 /* LOAD WORD SHORT DISP */ 546 #define LDHS 0x03, 0x41, 19, 7 /* LOAD HALFWORD SHORT DISP */ 547 #define LDBS 0x03, 0x40, 19, 7 /* LOAD BYTE SHORT DISP */ 548 #define LDWAS 0x03, 0x46, 19, 7 /* LOAD WORD ABSOLUTE SHORT DISP */ 549 #define LDCWS 0x03, 0x47, 19, 7 /* LOAD and CLEAR WORD SHORT DISP */ 550 #define STWS 0x03, 0x4a, 19, 7 /* STORE WORD SHORT DISP */ 551 #define STHS 0x03, 0x49, 19, 7 /* STORE HALFWORD SHORT DISP */ 552 #define STBS 0x03, 0x48, 19, 7 /* STORE BYTE SHORT DISP */ 553 #define STWAS 0x03, 0x4e, 19, 7 /* STORE WORD ABSOLUTE SHORT DISP */ 554 #define STBYS 0x03, 0x4c, 19, 7 /* STORE BYTES SHORT DISP */ 555 #define LDIL 0x08, 0x00, 0, 0 /* LOAD IMMED LEFT */ 556 #define ADDIL 0x0a, 0x00, 0, 0 /* ADD IMMED LEFT */ 557 #define BL 0x3a, 0x00, 16, 3 /* BRANCH [and LINK] */ 558 #define GATE 0x3a, 0x01, 16, 3 /* GATEWAY */ 559 #define BLR 0x3a, 0x02, 16, 3 /* BRANCH and LINK REGISTER */ 560 #define BV 0x3a, 0x06, 16, 3 /* BRANCH VECTORED */ 561 #define BE 0x38, 0x00, 0, 0 /* BRANCH EXTERNAL */ 562 #define BLE 0x39, 0x00, 0, 0 /* BRANCH and LINK EXTERNAL */ 563 #define MOVB 0x32, 0x00, 0, 0 /* MOVE and BRANCH */ 564 #define MOVIB 0x33, 0x00, 0, 0 /* MOVE IMMED and BRANCH */ 565 #define COMBT 0x20, 0x00, 0, 0 /* COMPARE and BRANCH if TRUE */ 566 #define COMBF 0x22, 0x00, 0, 0 /* COMPARE and BRANCH if FALSE */ 567 #define COMIBT 0x21, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if TRUE */ 568 #define COMIBF 0x23, 0x00, 0, 0 /* COMPARE IMMED and BRANCH if FALSE */ 569 #define ADDBT 0x28, 0x00, 0, 0 /* ADD and BRANCH if TRUE */ 570 #define ADDBF 0x2a, 0x00, 0, 0 /* ADD and BRANCH if FALSE */ 571 #define ADDIBT 0x29, 0x00, 0, 0 /* ADD IMMED and BRANCH if TRUE */ 572 #define ADDIBF 0x2b, 0x00, 0, 0 /* ADD IMMED and BRANCH if FALSE */ 573 #define BVB 0x30, 0x00, 0, 0 /* BRANCH on VARIABLE BIT */ 574 #define BB 0x31, 0x00, 0, 0 /* BRANCH on BIT */ 575 #define ADD 0x02, 0x30, 20, 7 /* ADD */ 576 #define ADDL 0x02, 0x50, 20, 7 /* ADD LOGICAL */ 577 #define ADDO 0x02, 0x70, 20, 7 /* ADD and TRAP on OVFLO */ 578 #define SH1ADD 0x02, 0x32, 20, 7 /* SHIFT 1, ADD */ 579 #define SH1ADDL 0x02, 0x52, 20, 7 /* SHIFT 1, ADD LOGICAL */ 580 #define SH1ADDO 0x02, 0x72, 20, 7 /* SHIFT 1, ADD and TRAP on OVFLO */ 581 #define SH2ADD 0x02, 0x34, 20, 7 /* SHIFT 2, ADD */ 582 #define SH2ADDL 0x02, 0x54, 20, 7 /* SHIFT 2, ADD LOGICAL */ 583 #define SH2ADDO 0x02, 0x74, 20, 7 /* SHIFT 2, ADD and TRAP on OVFLO */ 584 #define SH3ADD 0x02, 0x36, 20, 7 /* SHIFT 3, ADD */ 585 #define SH3ADDL 0x02, 0x56, 20, 7 /* SHIFT 3, ADD LOGICAL */ 586 #define SH3ADDO 0x02, 0x76, 20, 7 /* SHIFT 3, ADD and TRAP on OVFLO */ 587 #define ADDC 0x02, 0x38, 20, 7 /* ADD with CARRY */ 588 #define ADDCO 0x02, 0x78, 20, 7 /* ADD with CARRY and TRAP on OVFLO */ 589 #define SUB 0x02, 0x20, 20, 7 /* SUBTRACT */ 590 #define SUBO 0x02, 0x60, 20, 7 /* SUBTRACT and TRAP on OVFLO */ 591 #define SUBB 0x02, 0x28, 20, 7 /* SUBTRACT with BORROW */ 592 #define SUBBO 0x02, 0x68, 20, 7 /* SUBTRACT with BORROW and TRAP on OVFLO */ 593 #define SUBT 0x02, 0x26, 20, 7 /* SUBTRACT and TRAP on COND */ 594 #define SUBTO 0x02, 0x66, 20, 7 /* SUBTRACT and TRAP on COND or OVFLO */ 595 #define DS 0x02, 0x22, 20, 7 /* DIVIDE STEP */ 596 #define COMCLR 0x02, 0x44, 20, 7 /* COMPARE and CLEAR */ 597 #define OR 0x02, 0x12, 20, 7 /* INCLUSIVE OR */ 598 #define XOR 0x02, 0x14, 20, 7 /* EXCLUSIVE OR */ 599 #define AND 0x02, 0x10, 20, 7 /* AND */ 600 #define ANDCM 0x02, 0x00, 20, 7 /* AND COMPLEMENT */ 601 #define UXOR 0x02, 0x1c, 20, 7 /* UNIT XOR */ 602 #define UADDCM 0x02, 0x4c, 20, 7 /* UNIT ADD COMPLEMENT */ 603 #define UADDCMT 0x02, 0x4e, 20, 7 /* UNIT ADD COMPLEMENT and TRAP on COND */ 604 #define DCOR 0x02, 0x5c, 20, 7 /* DECIMAL CORRECT */ 605 #define IDCOR 0x02, 0x5e, 20, 7 /* INTERMEDIATE DECIMAL CORRECT */ 606 #define ADDI 0x2d, 0x00, 20, 1 /* ADD to IMMED */ 607 #define ADDIO 0x2d, 0x01, 20, 1 /* ADD to IMMED and TRAP on OVFLO */ 608 #define ADDIT 0x2c, 0x00, 20, 1 /* ADD to IMMED and TRAP on COND */ 609 #define ADDITO 0x2c, 0x01, 20, 1 /* ADD to IMMED and TRAP on COND or OVFLO */ 610 #define SUBI 0x25, 0x00, 20, 1 /* SUBTRACT from IMMED */ 611 #define SUBIO 0x25, 0x01, 20, 1 /* SUBTRACT from IMMED and TRAP on OVFLO */ 612 #define COMICLR 0x24, 0x00, 0, 0 /* COMPARE IMMED and CLEAR */ 613 #define VSHD 0x34, 0x00, 19, 3 /* VARIABLE SHIFT DOUBLE */ 614 #define SHD 0x34, 0x02, 19, 3 /* SHIFT DOUBLE */ 615 #define VEXTRU 0x34, 0x04, 19, 3 /* VARIABLE EXTRACT RIGHT UNSIGNED */ 616 #define VEXTRS 0x34, 0x05, 19, 3 /* VARIABLE EXTRACT RIGHT SIGNED */ 617 #define EXTRU 0x34, 0x06, 19, 3 /* EXTRACT RIGHT UNSIGNED */ 618 #define EXTRS 0x34, 0x07, 19, 3 /* EXTRACT RIGHT SIGNED */ 619 #define VDEP 0x35, 0x01, 19, 3 /* VARIABLE DEPOSIT */ 620 #define DEP 0x35, 0x03, 19, 3 /* DEPOSIT */ 621 #define VDEPI 0x35, 0x05, 19, 3 /* VARIABLE DEPOSIT IMMED */ 622 #define DEPI 0x35, 0x07, 19, 3 /* DEPOSIT IMMED */ 623 #define ZVDEP 0x35, 0x00, 19, 3 /* ZERO and VARIABLE DEPOSIT */ 624 #define ZDEP 0x35, 0x02, 19, 3 /* ZERO and DEPOSIT */ 625 #define ZVDEPI 0x35, 0x04, 19, 3 /* ZERO and VARIABLE DEPOSIT IMMED */ 626 #define ZDEPI 0x35, 0x06, 19, 3 /* ZERO and DEPOSIT IMMED */ 627 #define BREAK 0x00, 0x00, 19, 8 /* BREAK */ 628 #define RFI 0x00, 0x60, 19, 8 /* RETURN FROM INTERRUPTION */ 629 #define RFIR 0x00, 0x65, 19, 8 /* RFI & RESTORE SHADOW REGISTERS */ 630 #define SSM 0x00, 0x6b, 19, 8 /* SET SYSTEM MASK */ 631 #define RSM 0x00, 0x73, 19, 8 /* RESET SYSTEM MASK */ 632 #define MTSM 0x00, 0xc3, 19, 8 /* MOVE TO SYSTEM MASK */ 633 #define LDSID 0x00, 0x85, 19, 8 /* LOAD SPACE IDENTIFIER */ 634 #define MTSP 0x00, 0xc1, 19, 8 /* MOVE TO SPACE REGISTER */ 635 #define MTCTL 0x00, 0xc2, 19, 8 /* MOVE TO SYSTEM CONTROL REGISTER */ 636 #define MFSP 0x00, 0x25, 19, 8 /* MOVE FROM SPACE REGISTER */ 637 #define MFCTL 0x00, 0x45, 19, 8 /* MOVE FROM SYSTEM CONTROL REGISTER */ 638 #define SYNC 0x00, 0x20, 19, 8 /* SYNCHRONIZE DATA CACHE */ 639 #define DIAG 0x05, 0x00, 0, 0 /* DIAGNOSE */ 640 #define SPOP 0x04, 0x00, 0, 0 /* SPECIAL FUNCTION UNIT */ 641 #define COPR 0x0c, 0x00, 0, 0 /* COPROCESSOR */ 642 #define CLDWX 0x09, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 643 #define CLDDX 0x0b, 0x00, 19, 4 /* COPROCESSOR LOAD WORD INDEXED */ 644 #define CSTWX 0x09, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 645 #define CSTDX 0x0b, 0x01, 19, 4 /* COPROCESSOR STORE WORD INDEXED */ 646 #define CLDWS 0x09, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 647 #define CLDDS 0x0b, 0x08, 19, 4 /* COPROCESSOR LOAD WORD SHORT */ 648 #define CSTWS 0x09, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 649 #define CSTDS 0x0b, 0x09, 19, 4 /* COPROCESSOR STORE WORD SHORT */ 650 #define FLOAT0 0x0e, 0x00, 21, 2 /* FLOATING POINT CLASS 0 */ 651 #define FLOAT1 0x0e, 0x01, 21, 2 /* FLOATING POINT CLASS 1 */ 652 #define FLOAT2 0x0e, 0x02, 21, 2 /* FLOATING POINT CLASS 2 */ 653 #define FLOAT3 0x0e, 0x03, 21, 2 /* FLOATING POINT CLASS 3 */ 654 #define FMPYSUB 0x26, 0x00, 0, 0 /* FP MULTIPLY AND SUBTRACT */ 655 #define FMPYADD 0x06, 0x00, 0, 0 /* FP MULTIPLY AND ADD/TRUNCATE */ 656 #define FSTQX 0x0f, 0x01, 19, 4 /* FLOATING POINT STORE QUAD INDEXED */ 657 #define FSTQS 0x0f, 0x09, 19, 4 /* FLOATING POINT STORE QUAD SHORT */ 658 /* all of the following have been pushed around to conform */ 659 #define PROBER 0x01, 0x46, 19, 7 /* PROBE READ ACCESS */ 660 #ifdef notdef 661 #define PROBERI 0x01, 0xc6, 19, 7 /* PROBE READ ACCESS IMMEDIATE */ 662 #endif 663 #define PROBEW 0x01, 0x47, 19, 7 /* PROBE WRITE ACCESS */ 664 #ifdef notdef 665 #define PROBEWI 0x01, 0xc7, 19, 7 /* PROBE WRITE ACCESS IMMEDIATE */ 666 #endif 667 #define LPA 0x01, 0x4d, 19, 7 /* LOAD PHYSICAL ADDRESS */ 668 #define LHA 0x01, 0x4c, 19, 7 /* LOAD HASH ADDRESS */ 669 #define PDTLB 0x01, 0x48, 19, 7 /* PURGE DATA TRANS LOOKASIDE BUFFER */ 670 #define PITLB 0x01, 0x08, 19, 7 /* PURGE INST TRANS LOOKASIDE BUFFER */ 671 #define PDTLBE 0x01, 0x49, 19, 7 /* PURGE DATA TLB ENTRY */ 672 #define PITLBE 0x01, 0x09, 19, 7 /* PURGE INST TLB ENTRY */ 673 #define IDTLBA 0x01, 0x41, 19, 7 /* INSERT DATA TLB ADDRESS */ 674 #define IITLBA 0x01, 0x01, 19, 7 /* INSERT INSTRUCTION TLB ADDRESS */ 675 #define IDTLBP 0x01, 0x40, 19, 7 /* INSERT DATA TLB PROTECTION */ 676 #define IITLBP 0x01, 0x00, 19, 7 /* INSERT INSTRUCTION TLB PROTECTION */ 677 #define PDC 0x01, 0x4e, 19, 7 /* PURGE DATA CACHE */ 678 #define FDC 0x01, 0x4a, 19, 7 /* FLUSH DATA CACHE */ 679 #define FIC 0x01, 0x0a, 19, 7 /* FLUSH INSTRUCTION CACHE */ 680 #define FDCE 0x01, 0x4b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 681 #define FICE 0x01, 0x0b, 19, 7 /* FLUSH DATA CACHE ENTRY */ 682 683 /* 684 * Header: /n/schirf/u/baford/CVS/mach4-parisc/kernel_unused/parisc/kdb/unasm.c,v 1.5 1994/07/21 22:32:05 mike Exp 685 * 686 * Spectrum Simulator Instruction Set Constants and Datatypes 687 * Dan Magenheimer - 4/28/82 688 * Computer Research Center, Hewlett-Packard Labs 689 * 690 * (c) copyright 1982 691 * (p) protected 1982 692 * The Hewlett-Packard Company 693 * Hewlett-Packard Laboratories 694 * Computer Research Center 695 * Palo Alto, California 696 * 697 * *** HP Company Confidential *** 698 * 699 * Log: unasm.c,v 700 * Revision 1.5 1994/07/21 22:32:05 mike 701 * official HP copyright notice 702 * 703 * Revision 1.4 1992/07/08 12:19:52 dalton 704 * Checkin before split to 1.0.4 release (by LBS). 705 * 706 * Revision 1.3 92/06/06 16:16:45 dalton 707 * *** empty log message *** 708 * 709 * Revision 1.2 92/06/06 15:42:28 dalton 710 * Changed include to be a path relative to hp800. 711 * 712 * Revision 1.1 92/06/06 14:05:33 dalton 713 * Initial revision 714 * 715 * Revision 1.2 91/04/14 20:29:49 osfrcs 716 * Initial version. 717 * [91/03/30 09:20:34 brezak] 718 * 719 * Revision 1.1.2.2 91/04/02 10:42:50 brezak 720 * Initial version. 721 * [91/03/30 09:20:34 brezak] 722 * 723 * Revision 1.1.1.2 91/03/30 09:20:34 brezak 724 * Initial version. 725 * 726 ;Revision 1.1 88/07/11 14:05:21 14:05:21 ren (Bob Naas) 727 ;Initial revision 728 ; 729 * Revision 5.1 87/02/27 11:12:23 11:12:23 kent (Kent McMullen) 730 * update all src to 5.1 731 * 732 * Revision 5.0 87/02/18 16:31:52 16:31:52 kent (Kent McMullen) 733 * update all revision numbers to 5.0 for release 734 * 735 * Revision 1.1 86/07/15 08:35:00 08:35:00 kent (Kent McMullen) 736 * Initial revision 737 * 738 * Revision 4.3 85/11/12 09:28:44 09:28:44 viggy (Viggy Mokkarala) 739 * first mpsim version, partially stable 740 * 741 * Revision 4.2 84/07/16 17:20:57 17:20:57 djm () 742 * Define field macros for COPR and SFU insts 743 * 744 * Revision 4.1 83/10/25 17:10:14 djm (Daniel Magenheimer) 745 * First release for ACD v4 746 * 747 * Revision 3.1 83/08/03 14:09:59 djm (Daniel Magenheimer) 748 * Sys calls, args, -S, bug fixes, etc. 749 * 750 * Revision 3.0 83/06/13 10:25:13 djm (Daniel Magenheimer) 751 * First release for distribution 752 * 753 * 754 */ 755 /* 756 * Changes: 757 * 12/01/89 ejf Add Rsd(), Rse(), Rtd(), Rte() for 5 ops. 758 * 11/30/89 ejf Make instruction use counters shared, not per cpu. 759 * 11/28/89 ejf Change majoropcode for quicker extension extract. 760 */ 761 762 763 764 /* 765 * Dependencies: std.h, ssDefs.h, bits.h 766 */ 767 768 769 /* Lookup/Execute structure for instructions */ 770 struct inst { 771 u_char majopc; /* major opcode of instruction, 0..MAXOPC */ 772 u_char opcext; /* opcode extension, 0 if not applic. */ 773 u_char extbs; /* starting bit pos of extension field */ 774 u_char extbl; /* bit length of extension field */ 775 u_int count; /* frequency counter for analysis */ 776 char mnem[8]; /* ascii mnemonic */ 777 /* disassembly function */ 778 int (*dasmfcn)(const struct inst *, OFS, union insn); 779 }; 780 781 782 #define NMAJOPCS 64 783 784 struct majoropcode { 785 const struct inst **subops; /* pointer to table of subops indexed by 786 * opcode extension */ 787 u_int maxsubop; /* largest opcode extension value or 0 */ 788 u_int extshft; /* right shift amount for extension field */ 789 u_int extmask; /* post shift mask for extension field */ 790 }; 791 792 #define OpExt(i,m) ((i >> m->extshft) & m->extmask) /* extract opcode extension */ 793 794 795 /*****************************/ 796 /* Miscellaneous definitions */ 797 /*****************************/ 798 799 /* Load/Store Indexed Opcode Extension Cache Control */ 800 #define NOACTION 0 801 #define STACKREF 1 802 #define SEQPASS 2 803 #define PREFETCH 3 804 805 /******************************/ 806 /* Fields within instructions */ 807 /******************************/ 808 809 /* opcode */ 810 #define Opcode(i) BitfR(i,0,6,_b06) 811 /* opcode true/false bit */ 812 #define OpcTF(i) BitfR(i,4,1,_b41) 813 /* register sources */ 814 #define Rsa(i) BitfR(i,11,5,_b115) 815 #define Rsb(i) BitfR(i,6,5,_b65) 816 #define Rsc(i) BitfR(i,27,5,_b275) 817 #define Rsd(i) BitfR(i,21,5,_b215) 818 #define Rse(i) BitfR(i,16,5,_b165) 819 /* register targets */ 820 #define Rta(i) BitfR(i,11,5,_b115) 821 #define Rtb(i) BitfR(i,6,5,_b65) 822 #define Rtc(i) BitfR(i,27,5,_b275) 823 #define Rtd(i) BitfR(i,21,5,_b215) 824 #define Rte(i) BitfR(i,16,5,_b165) 825 /* 5-bit immediates (Magnitude, Sign) */ 826 #define Imb5(i) BitfR(i,6,5,_b65) 827 #define Ima5M(i) BitfR(i,11,4,_b114) 828 #define Ima5S(i) BitfR(i,15,1,_b151) 829 #define Ima5A(i) BitfR(i,11,5,_b115) 830 #define Imd5(i) BitfR(i,22,5,_b225) 831 #define Imc5M(i) BitfR(i,27,4,_b274) 832 #define Imc5S(i) BitfR(i,31,1,_b311) 833 #define Imc5A(i) BitfR(i,27,5,_b275) 834 /* Other immediates */ 835 #define Im21L(i) BitfR(i,18,2,_b182) 836 #define Im21H(i) BitfR(i,20,11,_b2011) 837 #define Im21M1(i) BitfR(i,16,2,_b162) 838 #define Im21M2(i) BitfR(i,11,5,_b115) 839 #define Im21S(i) BitfR(i,31,1,_b311) 840 #define Im11M(i) BitfR(i,21,10,_b2110) 841 #define Im11S(i) BitfR(i,31,1,_b311) 842 /* displacements/offsets */ 843 #define DispM(i) BitfR(i,18,13,_b1813) 844 #define DispS(i) BitfR(i,31,1,_b311) 845 #define Off5(i) BitfR(i,11,5,_b115) 846 #define Off11H(i) BitfR(i,19,10,_b1910) 847 #define Off11L(i) BitfR(i,29,1,_b291) 848 #define OffS(i) BitfR(i,31,1,_b311) 849 /* miscellaneous */ 850 #define Dss(i) BitfR(i,16,2,_b162) 851 #define Cond(i) BitfR(i,16,3,_b163) 852 #define Cneg(i) BitfR(i,19,1,_b191) 853 #define Cond4(i) BitfR(i,16,4,_b164) /* Cond AND Cneg */ 854 #define Nu(i) BitfR(i,30,1,_b301) 855 #define SrL(i) BitfR(i,16,2,_b162) 856 #define SrH(i) BitfR(i,18,1,_b181) 857 #define ShortDisp(i) BitfR(i,19,1,_b191) 858 #define IndxShft(i) BitfR(i,18,1,_b181) 859 #define ModBefore(i) BitfR(i,18,1,_b181) 860 #define CacheCtrl(i) BitfR(i,20,2,_b202) 861 #define Modify(i) BitfR(i,26,1,_b261) 862 #define ProbeI(i) BitfR(i,18,1,_b181) 863 #define Uid(i) BitfR(i,23,3,_b233) 864 #define Sfu(i) BitfR(i,23,3,_b233) 865 #define CopExt17(i) BitfR(i,6,17,_b617) 866 #define CopExt5(i) BitfR(i,27,5,_b275) 867 #define SpopType(i) BitfR(i,21,2,_b212) 868 #define SpopExt15(i) BitfR(i,6,15,_b615) 869 #define SpopExt10(i) BitfR(i,11,10,_b1110) 870 #define SpopExt5L(i) BitfR(i,16,5,_b165) 871 #define SpopExt5(i) BitfR(i,27,5,_b275) 872 #define NoMajOpc(i) BitfR(i,6,26,_b626) 873 #define Bi1(i) BitfR(i,27,5,_b275) /* fields in BREAK */ 874 #define Bi2(i) BitfR(i,6,13,_b613) 875 876 /* fragmented field collating macros */ 877 #define Ima5(i) (Ima5S(i) ? Ima5M(i) | (-1<<4) : Ima5M(i)) 878 879 #define Imc5(i) (Imc5S(i) ? Imc5M(i) | (-1<<4) : Imc5M(i)) 880 881 #define Disp(i) (DispS(i) ? DispM(i) | (-1<<13) : DispM(i)) 882 883 #define Im21(i) (Im21S(i) << 31 | Im21H(i) << 20 | Im21M1(i) << 18 | \ 884 Im21M2(i) << 13 | Im21L(i) << 11) 885 886 #define Im11(i) (Im11S(i) ? Im11M(i) | (-1<<10) : Im11M(i)) 887 888 #define Bdisp(i) ((OffS(i) ? (Off5(i)<<11 | Off11L(i)<<10|Off11H(i)) \ 889 /* branch displacement (bytes) */ | (-1 << 16) \ 890 : (Off5(i)<<11|Off11L(i)<<10|Off11H(i))) << 2) 891 892 #define Cbdisp(i) ((OffS(i) ? (Off11L(i) << 10 | Off11H(i)) \ 893 /* compare/branch disp (bytes) */ | (-1 << 11) \ 894 : Off11L(i) << 10 | Off11H(i)) << 2) 895 896 #define Sr(i) (SrH(i)<<2 | SrL(i)) 897 898 /* sfu/copr */ 899 #define CoprExt1(i) (CopExt17(i)) 900 #define CoprExt2(i) (CopExt5(i)) 901 #define CoprExt(i) ((CopExt17(i)<<5) | CopExt5(i)) 902 #define Spop0Ext(i) ((SpopExt15(i)<<5) | SpopExt5(i)) 903 #define Spop1Ext(i) (SpopExt15(i)) 904 #define Spop2Ext(i) ((SpopExt10(i)<<5) | SpopExt5(i)) 905 #define Spop3Ext(i) ((SpopExt5L(i)<<5) | SpopExt5(i)) 906 907 908 /*##################### Globals - Imports ##################################*/ 909 910 /* Disassembly functions */ 911 int fcoprDasm(union insn, u_int, u_int); 912 char *edDCond(u_int); 913 char *unitDCond(u_int); 914 char *addDCond(u_int); 915 char *subDCond(u_int); 916 int blDasm(const struct inst *, OFS, union insn); 917 int ldDasm(const struct inst *, OFS, union insn); 918 int stDasm(const struct inst *, OFS, union insn); 919 int addDasm(const struct inst *, OFS, union insn); 920 int unitDasm(const struct inst *, OFS, union insn); 921 int iaDasm(const struct inst *, OFS, union insn); 922 int shdDasm(const struct inst *, OFS, union insn); 923 int extrDasm(const struct inst *, OFS, union insn); 924 int vextrDasm(const struct inst *, OFS, union insn); 925 int depDasm(const struct inst *, OFS, union insn); 926 int vdepDasm(const struct inst *, OFS, union insn); 927 int depiDasm(const struct inst *, OFS, union insn); 928 int vdepiDasm(const struct inst *, OFS, union insn); 929 int limmDasm(const struct inst *, OFS, union insn); 930 int brkDasm(const struct inst *, OFS, union insn); 931 int lpkDasm(const struct inst *, OFS, union insn); 932 int fmpyaddDasm(const struct inst *, OFS, union insn); 933 int fmpysubDasm(const struct inst *, OFS, union insn); 934 int floatDasm(const struct inst *, OFS, union insn); 935 int coprDasm(const struct inst *, OFS, union insn); 936 int diagDasm(const struct inst *, OFS, union insn); 937 int scDasm(const struct inst *, OFS, union insn); 938 int mmgtDasm(const struct inst *, OFS, union insn); 939 int ldxDasm(const struct inst *, OFS, union insn); 940 int stsDasm(const struct inst *, OFS, union insn); 941 int stbysDasm(const struct inst *, OFS, union insn); 942 int brDasm(const struct inst *, OFS, union insn); 943 int bvDasm(const struct inst *, OFS, union insn); 944 int beDasm(const struct inst *, OFS, union insn); 945 int cbDasm(const struct inst *, OFS, union insn); 946 int cbiDasm(const struct inst *, OFS, union insn); 947 int bbDasm(const struct inst *, OFS, union insn); 948 int ariDasm(const struct inst *, OFS, union insn); 949 950 /*##################### Globals - Exports ##################################*/ 951 /*##################### Local Variables ####################################*/ 952 953 static const char fcoprUndef[] = "copr\t(rsvd or undef.)"; 954 static const char fmtStrTbl[][5] = { "sgl", "dbl", "sgl", "quad" }; 955 static const char condStrTbl[][7] = { 956 "false?", "false", "?", "!<=>", "=", "=t", "?=", "!<>", 957 "!?>=", "<", "?<", "!>=", "!?>", "<=", "?<=", "!>", 958 "!?<=", ">", "?>", "!<=", "!?<", ">=", "?>=", "!<", 959 "!?=", "<>", "!=", "!=t", "!?", "<=>", "true?", "true" 960 }; 961 static const char fsreg[][5] = { 962 "r0L", "r0R", "r1L", "r1R", "r2L", "r2R", "r3L", "r3R", 963 "r4L", "r4R", "r5L", "r5R", "r6L", "r6R", "r7L", "r7R", 964 "r8L", "r8R", "r9L", "r9R", "r10L", "r10R", "r11L", "r11R", 965 "r12L", "r12R", "r13L", "r13R", "r14L", "r14R", "r15L", "r15R", 966 "r16L", "r16R", "r17L", "r17R", "r18L", "r18R", "r19L", "r19R", 967 "r20L", "r20R", "r21L", "r21R", "r22L", "r22R", "r23L", "r23R", 968 "r24L", "r24R", "r25L", "r25R", "r26L", "r26R", "r27L", "r27R", 969 "r28L", "r28R", "r29L", "r29R", "r30L", "r30R", "r31L", "r31R" 970 }; 971 static const char fdreg[][4] = { 972 "r0", "r0", "r1", "r1", "r2", "r2", "r3", "r3", 973 "r4", "r4", "r5", "r5", "r6", "r6", "r7", "r7", 974 "r8", "r8", "r9", "r9", "r10", "r10", "r11", "r11", 975 "r12", "r12", "r13", "r13", "r14", "r14", "r15", "r15", 976 "r16", "r16", "r17", "r17", "r18", "r18", "r19", "r19", 977 "r20", "r20", "r21", "r21", "r22", "r22", "r23", "r23", 978 "r24", "r24", "r25", "r25", "r26", "r26", "r27", "r27", 979 "r28", "r28", "r29", "r29", "r30", "r30", "r31", "r31" 980 }; 981 982 /*##################### Macros #############################################*/ 983 984 #define Match(s) (strncmp(s,i->mnem,sizeof(s)-1) == 0) 985 986 /* bits for assist ops */ 987 #define AstNu(w) Modify(w) 988 #define Fpi(w) (Uid(w)>3) 989 990 /* bits for 5 ops */ 991 #define SinglePrec(i) Modify(i) 992 #define Ms1(i) ((Rsb(i)<<1)+(SinglePrec(i)?((Rsb(i)>15)?1:32):0)) 993 #define Ms2(i) ((Rsa(i)<<1)+(SinglePrec(i)?((Rsa(i)>15)?1:32):0)) 994 #define Mt(i) ((Rtc(i)<<1)+(SinglePrec(i)?((Rtc(i)>15)?1:32):0)) 995 #define As(i) ((Rsd(i)<<1)+(SinglePrec(i)?((Rsd(i)>15)?1:32):0)) 996 #define Ad(i) ((Rte(i)<<1)+(SinglePrec(i)?((Rte(i)>15)?1:32):0)) 997 998 /*##################### Globals - Exports ##################################*/ 999 1000 /* To replace instr function, do the following: */ 1001 /* a) locate the desired entry in instrs[] below */ 1002 /* b) change the 3rd field if an alternate mneumonic is */ 1003 /* desired for window disassembly */ 1004 /* c) change the 4th field to the name of the function being */ 1005 /* used for replacement (i.e. ldwRepl instead of ldw) */ 1006 /* d) change the 5th field if an alternate disassembly routine */ 1007 /* is desired (i.e. ldDasmRepl) */ 1008 1009 static const struct inst instrs[] = { 1010 { LDW, 0, "ldw", ldDasm }, 1011 { LDH, 0, "ldh", ldDasm }, 1012 { LDB, 0, "ldb", ldDasm }, 1013 { LDWM, 0, "ldwm", ldDasm }, 1014 { LDO, 0, "ldo", ldDasm }, 1015 { STW, 0, "stw", stDasm }, 1016 { STH, 0, "sth", stDasm }, 1017 { STB, 0, "stb", stDasm }, 1018 { STWM, 0, "stwm", stDasm }, 1019 { LDWX, 0, "ldw", ldxDasm }, 1020 { LDHX, 0, "ldh", ldxDasm }, 1021 { LDBX, 0, "ldb", ldxDasm }, 1022 { LDCWX, 0, "ldcw", ldxDasm }, 1023 { LDWAX, 0, "ldwa", ldxDasm }, 1024 { LDWS, 0, "ldw", ldxDasm }, 1025 { LDHS, 0, "ldh", ldxDasm }, 1026 { LDBS, 0, "ldb", ldxDasm }, 1027 { LDCWS, 0, "ldcw", ldxDasm }, 1028 { LDWAS, 0, "ldwa", ldxDasm }, 1029 { STWS, 0, "stws", stsDasm }, 1030 { STHS, 0, "sths", stsDasm }, 1031 { STBS, 0, "stbs", stsDasm }, 1032 { STWAS, 0, "stwas", stsDasm }, 1033 { STBYS, 0, "stbys", stbysDasm }, 1034 { LDIL, 0, "ldil", limmDasm }, 1035 { ADDIL, 0, "addil", limmDasm }, 1036 { GATE, 0, "gate", blDasm }, 1037 { BL, 0, "b", blDasm }, 1038 { BLR, 0, "blr", brDasm }, 1039 { BV, 0, "bv", bvDasm }, 1040 { BE, 0, "be", beDasm }, 1041 { BLE, 0, "ble", beDasm }, 1042 { COMBT, 0, "combt", cbDasm }, 1043 { COMBF, 0, "combf", cbDasm }, 1044 { COMIBT, 0, "comibt", cbiDasm }, 1045 { COMIBF, 0, "comibf", cbiDasm }, 1046 { ADDBT, 0, "addbt", cbDasm }, 1047 { ADDBF, 0, "addbf", cbDasm }, 1048 { ADDIBT, 0, "addibt", cbiDasm }, 1049 { ADDIBF, 0, "addibf", cbiDasm }, 1050 { MOVB, 0, "movb", cbDasm }, 1051 { MOVIB, 0, "movib", cbiDasm }, 1052 { BB, 0, "bb", bbDasm }, 1053 { BVB, 0, "bvb", bbDasm }, 1054 { SUBO, 0, "subo", ariDasm }, 1055 { ADD, 0, "add", addDasm }, 1056 { ADDL, 0, "addl", addDasm }, 1057 { ADDO, 0, "addo", ariDasm }, 1058 { SH1ADD, 0, "sh1add", ariDasm }, 1059 { SH1ADDL,0, "sh1addl", ariDasm }, 1060 { SH1ADDO,0, "sh1addo", ariDasm }, 1061 { SH2ADD, 0, "sh2add", ariDasm }, 1062 { SH2ADDL,0, "sh2addl", ariDasm }, 1063 { SH2ADDO,0, "sh2addo", ariDasm }, 1064 { SH3ADD, 0, "sh3add", ariDasm }, 1065 { SH3ADDL,0, "sh3addl", ariDasm }, 1066 { SH3ADDO,0, "sh3addo", ariDasm }, 1067 { SUB, 0, "sub", ariDasm }, 1068 { ADDCO, 0, "addco", ariDasm }, 1069 { SUBBO, 0, "subbo", ariDasm }, 1070 { ADDC, 0, "addc", ariDasm }, 1071 { SUBB, 0, "subb", ariDasm }, 1072 { COMCLR, 0, "comclr", ariDasm }, 1073 { OR, 0, "or", ariDasm }, 1074 { AND, 0, "and", ariDasm }, 1075 { XOR, 0, "xor", ariDasm }, 1076 { ANDCM, 0, "andcm", ariDasm }, 1077 { DS, 0, "ds", ariDasm }, 1078 { UXOR, 0, "uxor", unitDasm }, 1079 { UADDCM, 0, "uaddcm", unitDasm }, 1080 { UADDCMT,0, "uaddcmt", unitDasm }, 1081 { SUBTO, 0, "subto", ariDasm }, 1082 { SUBT, 0, "subt", ariDasm }, 1083 { DCOR, 0, "dcor", unitDasm }, 1084 { IDCOR, 0, "idcor", unitDasm }, 1085 { ADDIO, 0, "addio", iaDasm }, 1086 { SUBIO, 0, "subio", iaDasm }, 1087 { ADDI, 0, "addi", iaDasm }, 1088 { SUBI, 0, "subi", iaDasm }, 1089 { COMICLR,0, "comiclr", iaDasm }, 1090 { ADDITO, 0, "addito", iaDasm }, 1091 { ADDIT, 0, "addit", iaDasm }, 1092 { SHD, 0, "shd", shdDasm }, 1093 { VSHD, 0, "vshd", shdDasm }, 1094 { EXTRU, 0, "extru", extrDasm }, 1095 { EXTRS, 0, "extrs", extrDasm }, 1096 { VEXTRU, 0, "vextru", vextrDasm }, 1097 { VEXTRS, 0, "vextrs", vextrDasm }, 1098 { DEP, 0, "dep", depDasm }, 1099 { VDEP, 0, "vdep", vdepDasm }, 1100 { DEPI, 0, "depi", depiDasm }, 1101 { VDEPI, 0, "vdepi", vdepiDasm }, 1102 { ZDEP, 0, "zdep", depDasm }, 1103 { ZVDEP, 0, "zvdep", vdepDasm }, 1104 { ZDEPI, 0, "zdepi", depiDasm }, 1105 { ZVDEPI, 0, "zvdepi", vdepiDasm }, 1106 { BREAK, 0, "break", brkDasm }, 1107 { RFI, 0, "rfi", 0 }, 1108 { RFIR, 0, "rfir", 0 }, 1109 { SSM, 0, "ssm", scDasm }, 1110 { RSM, 0, "rsm", scDasm }, 1111 { MTSM, 0, "mtsm", scDasm }, 1112 { PROBER, 0, "prober", mmgtDasm }, 1113 { PROBEW, 0, "probew", mmgtDasm }, 1114 { LPA, 0, "lpa", mmgtDasm }, 1115 { LHA, 0, "lha", mmgtDasm }, 1116 { LDSID, 0, "ldsid", scDasm }, 1117 { PDTLB, 0, "pdtlb", mmgtDasm }, 1118 { PDTLBE, 0, "pdtlbe", mmgtDasm }, 1119 { PITLB, 0, "pitlb", mmgtDasm }, 1120 { PITLBE, 0, "pitlbe", mmgtDasm }, 1121 { IDTLBA, 0, "idtlba", mmgtDasm }, 1122 { IITLBA, 0, "iitlba", mmgtDasm }, 1123 { IDTLBP, 0, "idtlbp", mmgtDasm }, 1124 { IITLBP, 0, "iitlbp", mmgtDasm }, 1125 { FIC, 0, "fic", mmgtDasm }, 1126 { FICE, 0, "fice", mmgtDasm }, 1127 { PDC, 0, "pdc", mmgtDasm }, 1128 { FDC, 0, "fdc", mmgtDasm }, 1129 { FDCE, 0, "fdce", mmgtDasm }, 1130 { SYNC, 0, "sync", 0 }, 1131 { MTSP, 0, "mtsp", scDasm }, 1132 { MTCTL, 0, "mtctl", scDasm }, 1133 { MFSP, 0, "mfsp", scDasm }, 1134 { MFCTL, 0, "mfctl", scDasm }, 1135 { DIAG, 0, "diag", diagDasm }, 1136 { SPOP, 0, "???", 0 }, 1137 { COPR, 0, "copr", coprDasm }, 1138 { CLDWX, 0, "cldw", coprDasm }, 1139 { CLDDX, 0, "cldd", coprDasm }, 1140 { CSTWX, 0, "cstw", coprDasm }, 1141 { CSTDX, 0, "cstd", coprDasm }, 1142 { CLDWS, 0, "cldw", coprDasm }, 1143 { CLDDS, 0, "cldd", coprDasm }, 1144 { CSTWS, 0, "cstw", coprDasm }, 1145 { CSTDS, 0, "cstd", coprDasm }, 1146 { FLOAT0, 0, "f", floatDasm }, 1147 { FLOAT1, 0, "fcnv", floatDasm }, 1148 { FLOAT2, 0, "f", floatDasm }, 1149 { FLOAT3, 0, "f", floatDasm }, 1150 { FMPYSUB,0, "fmpy", fmpysubDasm }, 1151 { FMPYADD,0, "fmpy", fmpyaddDasm }, 1152 { FSTQX, 0, "fstqx", lpkDasm }, 1153 { FSTQS, 0, "fstqs", lpkDasm }, 1154 {0} 1155 }; 1156 1157 1158 static const struct inst illeg = { 0, 0, 0, 0, 0, "???", 0 }; 1159 static const struct inst *so_sysop[0xd0]; 1160 static const struct inst *so_mmuop[0x50]; 1161 static const struct inst *so_arith[0x80]; 1162 static const struct inst *so_loads[0x50]; 1163 static const struct inst *so_cldw [0x0A]; 1164 static const struct inst *so_cldd [0x0A]; 1165 static const struct inst *so_float[0x04]; 1166 static const struct inst *so_fstq [0x0A]; 1167 static const struct inst *so_ebran[0x08]; 1168 static const struct inst *so_addit[0x02]; 1169 static const struct inst *so_addi [0x02]; 1170 static const struct inst *so_subi [0x02]; 1171 static const struct inst *so_shext[0x08]; 1172 static const struct inst *so_deps [0x08]; 1173 1174 #define ILLEG (const struct inst **)&illeg 1175 #define NENTS(a) (sizeof(a)/sizeof(a[0])-1) 1176 static struct majoropcode majopcs[NMAJOPCS] = { 1177 { so_sysop, NENTS(so_sysop) }, /* 00 */ 1178 { so_mmuop, NENTS(so_mmuop) }, /* 01 */ 1179 { so_arith, NENTS(so_arith) }, /* 02 */ 1180 { so_loads, NENTS(so_loads) }, /* 03 */ 1181 { ILLEG, 1 }, /* 04 */ 1182 { ILLEG, 1 }, /* 05 */ 1183 { ILLEG, 1 }, /* 06 */ 1184 { ILLEG, 1 }, /* 07 */ 1185 { ILLEG, 1 }, /* 08 */ 1186 { so_cldw , NENTS(so_cldw ) }, /* 09 */ 1187 { ILLEG, 1 }, /* 0A */ 1188 { so_cldd , NENTS(so_cldd ) }, /* 0B */ 1189 { ILLEG, 1 }, /* 0C */ 1190 { ILLEG, 1 }, /* 0D */ 1191 { so_float, NENTS(so_float) }, /* 0E */ 1192 { so_fstq , NENTS(so_fstq ) }, /* 0F */ 1193 { ILLEG, 1 }, /* 10 */ 1194 { ILLEG, 1 }, /* 11 */ 1195 { ILLEG, 1 }, /* 12 */ 1196 { ILLEG, 1 }, /* 13 */ 1197 { ILLEG, 1 }, /* 14 */ 1198 { ILLEG, 1 }, /* 15 */ 1199 { ILLEG, 1 }, /* 16 */ 1200 { ILLEG, 1 }, /* 17 */ 1201 { ILLEG, 1 }, /* 18 */ 1202 { ILLEG, 1 }, /* 19 */ 1203 { ILLEG, 1 }, /* 1A */ 1204 { ILLEG, 1 }, /* 1B */ 1205 { ILLEG, 1 }, /* 1C */ 1206 { ILLEG, 1 }, /* 1D */ 1207 { ILLEG, 1 }, /* 1E */ 1208 { ILLEG, 1 }, /* 1F */ 1209 { ILLEG, 1 }, /* 20 */ 1210 { ILLEG, 1 }, /* 21 */ 1211 { ILLEG, 1 }, /* 22 */ 1212 { ILLEG, 1 }, /* 23 */ 1213 { ILLEG, 1 }, /* 24 */ 1214 { so_subi , NENTS(so_subi ) }, /* 25 */ 1215 { ILLEG, 1 }, /* 26 */ 1216 { ILLEG, 1 }, /* 27 */ 1217 { ILLEG, 1 }, /* 28 */ 1218 { ILLEG, 1 }, /* 29 */ 1219 { ILLEG, 1 }, /* 2A */ 1220 { ILLEG, 1 }, /* 2B */ 1221 { so_addit, NENTS(so_addit) }, /* 2C */ 1222 { so_addi , NENTS(so_addi ) }, /* 2D */ 1223 { ILLEG, 1 }, /* 2E */ 1224 { ILLEG, 1 }, /* 2F */ 1225 { ILLEG, 1 }, /* 30 */ 1226 { ILLEG, 1 }, /* 31 */ 1227 { ILLEG, 1 }, /* 32 */ 1228 { ILLEG, 1 }, /* 33 */ 1229 { so_shext, NENTS(so_shext) }, /* 34 */ 1230 { so_deps , NENTS(so_deps ) }, /* 35 */ 1231 { ILLEG, 1 }, /* 36 */ 1232 { ILLEG, 1 }, /* 37 */ 1233 { ILLEG, 1 }, /* 38 */ 1234 { ILLEG, 1 }, /* 39 */ 1235 { so_ebran, NENTS(so_ebran) }, /* 3A */ 1236 { ILLEG, 1 }, /* 3B */ 1237 { ILLEG, 1 }, /* 3C */ 1238 { ILLEG, 1 }, /* 3D */ 1239 { ILLEG, 1 }, /* 3E */ 1240 { ILLEG, 1 }, /* 3F */ 1241 }; 1242 #undef NENTS 1243 #undef ILLEG 1244 1245 /*-------------------------------------------------------------------------- 1246 * instruction$ExecutionInitialize - Initialize the instruction execution 1247 * data structures. 1248 *---------------------------------------------------------------------------*/ 1249 static int iExInit(void); 1250 static int 1251 iExInit(void) 1252 { 1253 static int unasm_initted = 0; 1254 const struct inst *i; 1255 struct majoropcode *m; 1256 u_int shft, mask; 1257 1258 if (unasm_initted) 1259 return 0; 1260 1261 /* 1262 * Determine maxsubop for each major opcode. 1263 * Also, check all instructions of a given major opcode 1264 * for consistent opcode extension field definition, and 1265 * save a converted form of this definition in the majopcs 1266 * entry for this major opcode. 1267 */ 1268 for (i = &instrs[0]; *i->mnem; i++) { 1269 m = &majopcs[i->majopc]; 1270 if (m->maxsubop < i->opcext) 1271 panic("iExInit not enough space for opcode %d", 1272 i->majopc); 1273 shft = 32 - i->extbs - i->extbl; 1274 mask = (1 << i->extbl) - 1; 1275 if (m->extshft || m->extmask) { 1276 if (m->extshft != shft || m->extmask != mask) { 1277 db_printf("%s - Bad instruction initialization!\n", i->mnem); 1278 return (0); 1279 } 1280 } else { 1281 m->extshft = shft; 1282 m->extmask = mask; 1283 } 1284 } 1285 1286 /* 1287 * Lastly, fill in all legal subops with the appropriate info. 1288 */ 1289 for (i = &instrs[0]; *i->mnem; i++) { 1290 m = &majopcs[i->majopc]; 1291 if (m->maxsubop == 1) 1292 m->subops = (const struct inst **)i; 1293 else 1294 m->subops[i->opcext] = i; 1295 } 1296 1297 unasm_initted++; 1298 return (1); 1299 } 1300 1301 1302 1303 /*##################### Functions and Subroutines ##########################*/ 1304 1305 /**************************************/ 1306 /* Miscellaneous Disassembly Routines */ 1307 /**************************************/ 1308 1309 /* Add instructions */ 1310 int 1311 addDasm(const struct inst *i, OFS ofs, union insn w) 1312 { 1313 db_printf("%s\t%%r%d,%%r%d,%%r%d",addDCond(Cond4(w)), 1314 Rsa(w),Rsb(w),Rtc(w)); 1315 return (1); 1316 } 1317 1318 /* Unit instructions */ 1319 int 1320 unitDasm(const struct inst *i, OFS ofs, union insn w) 1321 { 1322 db_printf(unitDCond(Cond4(w))); 1323 if (Match("dcor") || Match("idcor")) 1324 db_printf("\t%%r%d,%%r%d",Rsb(w),Rtc(w)); 1325 else 1326 db_printf("\t%%r%d,%%r%d,%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1327 return (1); 1328 } 1329 1330 /* Immediate Arithmetic instructions */ 1331 int 1332 iaDasm(const struct inst *i, OFS ofs, union insn w) 1333 { 1334 if (Match("addi")) 1335 db_printf("%s\t%d,%%r%d,%%r%d", 1336 addDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1337 else 1338 db_printf("%s\t%d,%%r%d,%%r%d", 1339 subDCond(Cond4(w)),Im11(w),Rsb(w),Rta(w)); 1340 return (1); 1341 } 1342 1343 /* Shift double instructions */ 1344 int 1345 shdDasm(const struct inst *i, OFS ofs, union insn w) 1346 { 1347 if (Match("vshd")) 1348 db_printf("%s\t%%r%d,%%r%d,%%r%d", 1349 edDCond(Cond(w)), Rsa(w),Rsb(w),Rtc(w)); 1350 else 1351 db_printf("%s\t%%r%d,%%r%d,%d,%%r%d", 1352 edDCond(Cond(w)),Rsa(w),Rsb(w),31-Imd5(w),Rtc(w)); 1353 return (1); 1354 } 1355 1356 /* Extract instructions */ 1357 int 1358 extrDasm(const struct inst *i, OFS ofs, union insn w) 1359 { 1360 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1361 edDCond(Cond(w)),Rsb(w),Imd5(w),32 - Rsc(w),Rta(w)); 1362 return (1); 1363 } 1364 1365 1366 /* Variable extract instructions */ 1367 int 1368 vextrDasm(const struct inst *i, OFS ofs, union insn w) 1369 { 1370 db_printf("%s\t%%r%d,%d,%%r%d", 1371 edDCond(Cond(w)),Rsb(w),32 - Rsc(w),Rta(w)); 1372 return (1); 1373 } 1374 1375 1376 /* Deposit instructions */ 1377 int 1378 depDasm(const struct inst *i, OFS ofs, union insn w) 1379 { 1380 db_printf("%s\t%%r%d,%d,%d,%%r%d", 1381 edDCond(Cond(w)),Rsa(w),31 - Imd5(w),32 - Rsc(w),Rtb(w)); 1382 return (1); 1383 } 1384 1385 1386 /* Variable deposit instructions */ 1387 int 1388 vdepDasm(const struct inst *i, OFS ofs, union insn w) 1389 { 1390 db_printf("%s\t%%r%d,%d,%%r%d", 1391 edDCond(Cond(w)),Rsa(w),32 - Rsc(w),Rtb(w)); 1392 return (1); 1393 } 1394 1395 1396 /* Deposit Immediate instructions */ 1397 int 1398 depiDasm(const struct inst *i, OFS ofs, union insn w) 1399 { 1400 db_printf("%s\t%d,%d,%d,%%r%d", 1401 edDCond(Cond(w)),Ima5(w),31 - Imd5(w),32 - Imc5A(w),Rtb(w)); 1402 return (1); 1403 } 1404 1405 /* Variable Deposit Immediate instructions */ 1406 int 1407 vdepiDasm(const struct inst *i, OFS ofs, union insn w) 1408 { 1409 db_printf("%s\t%d,%d,%%r%d",edDCond(Cond(w)),Ima5(w),32-Imc5A(w),Rtb(w)); 1410 return (1); 1411 } 1412 1413 /*--------------------------------------------------------------------------- 1414 * conditionType$DisassembleCondition - Return a string which contains the 1415 * ascii description of the passed numeric condition. 1416 *---------------------------------------------------------------------------*/ 1417 1418 char * 1419 subDCond(u_int cond) 1420 { 1421 switch(cond) { 1422 case EQZ: return(",="); 1423 case LT: return(",<"); 1424 case LE: return(",<="); 1425 case LLT: return(",<<"); 1426 case LLE: return(",<<="); 1427 case SV: return(",sv"); 1428 case OD: return(",od"); 1429 case NEQZ: return(",<>"); 1430 case GE: return(",>="); 1431 case GT: return(",>"); 1432 case LGE: return(",>>="); 1433 case LGT: return(",>>"); 1434 case NSV: return(",nsv"); 1435 case EV: return(",ev"); 1436 case TR: return(",tr"); 1437 case NEV: return(""); 1438 default: 1439 panic("subDCond: unknown condition"); 1440 } 1441 } 1442 1443 1444 /*--------------------------------------------------------------------------- 1445 * conditionType$DisassembleCondition - Return a string which contains the 1446 * ascii description of the passed numeric condition. 1447 *---------------------------------------------------------------------------*/ 1448 1449 char * 1450 addDCond(u_int cond) 1451 { 1452 switch(cond) { 1453 case EQZ: return(",="); 1454 case LT: return(",<"); 1455 case LE: return(",<="); 1456 case NUV: return(",nuv"); 1457 case ZNV: return(",znv"); 1458 case SV: return(",sv"); 1459 case OD: return(",od"); 1460 case NEQZ: return(",<>"); 1461 case GE: return(",>="); 1462 case GT: return(",>"); 1463 case UV: return(",uv"); 1464 case VNZ: return(",vnz"); 1465 case NSV: return(",nsv"); 1466 case EV: return(",ev"); 1467 case TR: return(",tr"); 1468 case NEV: return(""); 1469 default: 1470 panic("addDCond: unknown condition"); 1471 } 1472 } 1473 1474 char * 1475 unitDCond(u_int cond) 1476 { 1477 switch(cond) { 1478 case SHC: return(",shc"); 1479 case SHZ: return(",shz"); 1480 case SBC: return(",sbc"); 1481 case SBZ: return(",sbz"); 1482 case SDC: return(",sdc"); 1483 case NHC: return(",nhc"); 1484 case NHZ: return(",nhz"); 1485 case NBC: return(",nbc"); 1486 case NBZ: return(",nbz"); 1487 case NDC: return(",ndc"); 1488 case TR: return(",tr"); 1489 case NEV: return(""); 1490 default: 1491 panic("unitDCond: unknown condition"); 1492 } 1493 } 1494 1495 char * 1496 edDCond(u_int cond) 1497 { 1498 switch(cond) { 1499 case XOD: return(",od"); 1500 case XTR: return(",tr"); 1501 case XNE: return(",<>"); 1502 case XLT: return(",<"); 1503 case XEQ: return(",="); 1504 case XGE: return(",>="); 1505 case XEV: return(",ev"); 1506 case NEV: return(""); 1507 default: 1508 panic("edDCond: unknown condition"); 1509 } 1510 } 1511 1512 1513 1514 /****************************************/ 1515 /* Format Specific Disassembly Routines */ 1516 /****************************************/ 1517 1518 1519 /* Load [modify] instructions */ 1520 int 1521 ldDasm(const struct inst *i, OFS ofs, union insn w) 1522 { 1523 int d = Disp(w); 1524 char s[2]; 1525 1526 s[1] = '\0'; 1527 if (d < 0) { 1528 d = -d; 1529 s[0] = '-'; 1530 } else 1531 s[0] = '\0'; 1532 1533 if (Rsb(w) == 0 && Match("ldo")) { 1534 db_printf("ldi\t%s%X,%%r%d",s,d,Rta(w)); 1535 return (1); 1536 } 1537 db_printf("%s\t%s%s%X",i->mnem,(d < 2048? "R'":""), s, d); 1538 if (Dss(w)) 1539 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rta(w)); 1540 else 1541 db_printf("(%%r%d),%%r%d",Rsb(w),Rta(w)); 1542 return (1); 1543 } 1544 1545 /* Store [modify] instructions */ 1546 int 1547 stDasm(const struct inst *i, OFS ofs, union insn w) 1548 { 1549 int d = Disp(w); 1550 char s[2]; 1551 1552 db_printf("\t%%r%d,",Rta(w)); 1553 1554 s[1] = '\0'; 1555 if (d < 0) { 1556 d = -d; 1557 s[0] = '-'; 1558 } else 1559 s[0] = '\0'; 1560 1561 db_printf("%s%s%X", (d < 2048? "R'":""), s, d); 1562 1563 if (Dss(w)) 1564 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 1565 else 1566 db_printf("(%%r%d)",Rsb(w)); 1567 return (1); 1568 } 1569 1570 /* Load indexed instructions */ 1571 int 1572 ldxDasm(const struct inst *i, OFS ofs, union insn w) 1573 { 1574 const char *p; 1575 1576 if (ShortDisp(w)) { 1577 db_printf("s"); 1578 if (Modify(w)) 1579 db_printf(",m%s", ModBefore(w)? "b": "a"); 1580 } else { 1581 db_printf("x"); 1582 if (Modify(w)) 1583 db_printf(",%sm", IndxShft(w)? "s":""); 1584 } 1585 switch (CacheCtrl(w)) { 1586 default: 1587 case NOACTION: p = ""; break; 1588 case STACKREF: p = ",c"; break; 1589 case SEQPASS: p = ",q"; break; 1590 case PREFETCH: p = ",p"; break; 1591 } 1592 if (ShortDisp(w)) 1593 db_printf("%s\t%d", p, Ima5(w)); 1594 else 1595 db_printf("%s\t%%r%d", p, Rsa(w)); 1596 1597 if (Dss(w)) 1598 db_printf("(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1599 else 1600 db_printf("(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1601 return (1); 1602 } 1603 1604 /* Store short displacement instructions */ 1605 int 1606 stsDasm(const struct inst *i, OFS ofs, union insn w) 1607 { 1608 const char *p; 1609 1610 if (Modify(w)) 1611 db_printf(",m%s", ModBefore(w)? "b":"a"); 1612 1613 switch (CacheCtrl(w)) { 1614 default: 1615 case NOACTION: p = ""; break; 1616 case STACKREF: p = ",c"; break; 1617 case SEQPASS: p = ",q"; break; 1618 case PREFETCH: p = ",p"; break; 1619 } 1620 db_printf("%s\t%%r%d,", p, Rta(w)); 1621 if (Dss(w)) 1622 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1623 else 1624 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1625 return (1); 1626 } 1627 1628 /* Store Bytes Instruction */ 1629 int 1630 stbysDasm(const struct inst *i, OFS ofs, union insn w) 1631 { 1632 const char *p; 1633 1634 db_printf(ModBefore(w)? ",e":",b"); 1635 if (Modify(w)) 1636 db_printf(",m"); 1637 switch (CacheCtrl(w)) { 1638 default: 1639 case NOACTION: p = ""; break; 1640 case STACKREF: p = ",f"; break; 1641 case SEQPASS: p = ",r"; break; 1642 case PREFETCH: p = ",z"; break; 1643 } 1644 db_printf("%s\t%%r%d,", p, Rta(w)); 1645 if (Dss(w)) 1646 db_printf("%d(%%sr%d,%%r%d)",Imc5(w),Dss(w),Rsb(w)); 1647 else 1648 db_printf("%d(%%r%d)",Imc5(w),Rsb(w)); 1649 return (1); 1650 } 1651 1652 /* Long Immediate instructions */ 1653 int 1654 limmDasm(const struct inst *i, OFS ofs, union insn w) 1655 { 1656 db_printf("\tL'%X,%%r%d", Im21(w), Rtb(w)); 1657 return (1); 1658 } 1659 1660 1661 /* Branch and Link instruction(s) (Branch, too!!) */ 1662 int 1663 blDasm(const struct inst *i, OFS ofs, union insn w) 1664 { 1665 OFS tgtofs = ofs + 8 + Bdisp(w); 1666 u_int link = Rtb(w); 1667 1668 if (link && !Match("gate")) 1669 db_printf("l"); 1670 if (Nu(w)) 1671 db_printf(",n"); 1672 db_printf("\t"); 1673 1674 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1675 1676 if (link || Match("gate")) 1677 db_printf(",%%r%d",link); 1678 1679 return (1); 1680 } 1681 1682 /* Branch Register instruction */ 1683 int 1684 brDasm(const struct inst *i, OFS ofs, union insn w) 1685 { 1686 db_printf("%s\t%%r%d,%%r%d", Nu(w)?",n":"", Rsa(w), Rtb(w)); 1687 return (1); 1688 } 1689 1690 /* Dispatch instructions */ 1691 int 1692 bvDasm(const struct inst *i, OFS ofs, union insn w) 1693 { 1694 db_printf("%s\t%%r%d(%%r%d)", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1695 return (1); 1696 } 1697 1698 /* Branch External instructions */ 1699 int 1700 beDasm(const struct inst *i, OFS ofs, union insn w) 1701 { 1702 int d = Bdisp(w); 1703 const char *p; 1704 char s[2]; 1705 1706 s[1] = '\0'; 1707 if (d < 0) { 1708 d = -d; 1709 s[0] = '-'; 1710 } else 1711 s[0] = '\0'; 1712 1713 p = Nu(w)? ",n":""; 1714 db_printf("%s\tR'%s%X(%%sr%d,%%r%d)", p, 1715 s, d, Sr(w), Rsb(w)); 1716 return (1); 1717 } 1718 1719 1720 /* Compare/Add and Branch instructions */ 1721 int 1722 cbDasm(const struct inst *i, OFS ofs, union insn w) 1723 { 1724 OFS tgtofs = ofs + 8 + Cbdisp(w); 1725 1726 if (Match("movb")) 1727 db_printf(edDCond(Cond(w))); 1728 else if (Match("addb")) 1729 db_printf(addDCond(Cond(w) << 1)); 1730 else 1731 db_printf(subDCond(Cond(w) << 1)); 1732 db_printf("%s\t%%r%d,%%r%d,", Nu(w)?",n":"", Rsa(w), Rsb(w)); 1733 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1734 return (1); 1735 } 1736 1737 /* Compare/Add and Branch Immediate instructions */ 1738 int 1739 cbiDasm(const struct inst *i, OFS ofs, union insn w) 1740 { 1741 OFS tgtofs = ofs + 8 + Cbdisp(w); 1742 1743 if (Match("movib")) 1744 db_printf(edDCond(Cond(w))); 1745 else if (Match("addib")) 1746 db_printf(addDCond(Cond(w) << 1)); 1747 else 1748 db_printf(subDCond(Cond(w) << 1)); 1749 db_printf("%s\t%d,%%r%d,", Nu(w)? ",n":"", Ima5(w), Rsb(w)); 1750 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1751 return (1); 1752 } 1753 1754 /* Branch on Bit instructions */ 1755 int 1756 bbDasm(const struct inst *i, OFS ofs, union insn w) 1757 { 1758 OFS tgtofs = ofs + 8 + Cbdisp(w); 1759 const char *p; 1760 1761 db_printf(edDCond(Cond(w))); 1762 p = Nu(w)? ",n":""; 1763 if (Match("bvb")) 1764 db_printf("%s\t%%r%d,", p, Rta(w)); 1765 else 1766 db_printf("%s\t%%r%d,%d,", p, Rsa(w), Imb5(w)); 1767 db_printsym((db_addr_t)tgtofs, DB_STGY_ANY, db_printf); 1768 return (1); 1769 } 1770 1771 /* Arithmetic instructions */ 1772 int 1773 ariDasm(const struct inst *i, OFS ofs, union insn w) 1774 { 1775 if (Match("or") && Rsb(w) == 0 && Cond4(w) == NEV) { 1776 if (Rsa(w) == 0 && Rtc(w) == 0) 1777 db_printf("nop"); 1778 else 1779 db_printf("copy\t%%r%d,%%r%d",Rsa(w),Rtc(w)); 1780 } else 1781 db_printf("%s%s\t%%r%d,%%r%d,%%r%d", i->mnem, 1782 subDCond(Cond4(w)), Rsa(w),Rsb(w),Rtc(w)); 1783 return(1); 1784 } 1785 1786 /* System control operations */ 1787 int 1788 scDasm(const struct inst *i, OFS ofs, union insn w) 1789 { 1790 if (Match("mtctl")) { 1791 if (Rtb(w) == 11) 1792 db_printf("mtsar\t%%r%d",Rsa(w)); 1793 else 1794 db_printf("mtctl\t%%r%d,%%cr%d",Rsa(w),Rtb(w)); 1795 return (1); 1796 } 1797 db_printf(i->mnem); 1798 if (Match("ssm") || Match("rsm")) 1799 db_printf("\t%d,%%r%d",Ima5A(w),Rtc(w)); 1800 else if (Match("mtsm")) db_printf("\t%%r%d",Rsa(w)); 1801 else if (Match("ldprid")) db_printf("\t%%r%d",Rtc(w)); 1802 else if (Match("mtsp")) db_printf("\t%%r%d,%%sr%d",Rsa(w),Sr(w)); 1803 else if (Match("mfsp")) db_printf("\t%%sr%d,%%r%d",Sr(w),Rtc(w)); 1804 else if (Match("mfctl")) db_printf("\t%%cr%d,%%r%d",Rsb(w),Rtc(w)); 1805 else if (Match("ldsid")) { 1806 if (Dss(w)) 1807 db_printf("\t(%%sr%d,%%r%d),%%r%d",Dss(w),Rsb(w),Rtc(w)); 1808 else 1809 db_printf("\t(%%r%d),%%r%d",Rsb(w),Rtc(w)); 1810 } else { 1811 db_printf("?????"); 1812 return (0); 1813 } 1814 return (1); 1815 } 1816 1817 /* Instruction cache/tlb control instructions */ 1818 int 1819 mmgtDasm(const struct inst *i, OFS ofs, union insn w) 1820 { 1821 if (Match("probe")) { 1822 if (ProbeI(w)) { 1823 if (Dss(w)) 1824 db_printf("i\t(%%sr%d,%%r%d),%d,%%r%d", 1825 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1826 else 1827 db_printf("i\t(%%r%d),%d,%%r%d", 1828 Rsb(w),Rsa(w),Rtc(w)); 1829 } else { 1830 if (Dss(w)) 1831 db_printf("\t(%%sr%d,%%r%d),%%r%d,%%r%d", 1832 Dss(w),Rsb(w),Rsa(w),Rtc(w)); 1833 else 1834 db_printf("\t(%%r%d),%%r%d,%%r%d", 1835 Rsb(w),Rsa(w),Rtc(w)); 1836 } 1837 } 1838 else if (Match("lha") || Match("lpa")) { 1839 if (Modify(w)) 1840 db_printf(",m"); 1841 if (Dss(w)) 1842 db_printf("\t%%r%d(%%sr%d,%%r%d),%%r%d", 1843 Rsa(w),Dss(w),Rsb(w),Rtc(w)); 1844 else 1845 db_printf("\t%%r%d(%%r%d),%%r%d",Rsa(w),Rsb(w),Rtc(w)); 1846 } 1847 else if (Match("pdtlb") || Match("pdc") || Match("fdc")) { 1848 if (Modify(w)) db_printf(",m"); 1849 if (Dss(w)) 1850 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1851 else 1852 db_printf("\t%%r%d(%%r%d)",Rsa(w),Rsb(w)); 1853 } 1854 else if (Match("pitlb") || Match("fic")) { 1855 if (Modify(w)) 1856 db_printf(",m"); 1857 db_printf("\t%%r%d(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1858 } 1859 else if (Match("idtlb")) { 1860 if (Dss(w)) 1861 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Dss(w),Rsb(w)); 1862 else 1863 db_printf("\t%%r%d,(%%r%d)",Rsa(w),Rsb(w)); 1864 } 1865 else if (Match("iitlb")) 1866 db_printf("\t%%r%d,(%%sr%d,%%r%d)",Rsa(w),Sr(w),Rsb(w)); 1867 else { 1868 db_printf("?????"); 1869 return (0); 1870 } 1871 return(1); 1872 } 1873 1874 /* break instruction */ 1875 int 1876 brkDasm(const struct inst *i, OFS ofs, union insn w) 1877 { 1878 db_printf("\t%d,%d",Bi1(w),Bi2(w)); 1879 return (1); 1880 } 1881 1882 int 1883 floatDasm(const struct inst *i, OFS ofs, union insn w) 1884 { 1885 u_int op1, r1, fmt, t; 1886 u_int op2, r2, dfmt; 1887 char *p; 1888 1889 op1 = CoprExt1(w); 1890 op2 = CoprExt2(w); 1891 fmt = (op1 >> 2) & 3; /* get precision of source */ 1892 1893 #define ST(r) ((fmt & 1)? fdreg[(r)]:fsreg[(r)]) 1894 /* 1895 * get first (or only) source register 1896 * (independent of class) 1897 */ 1898 r1 = (op1 >> 11) & 0x3e; 1899 if ((fmt & 1) == 0 && (Uid(w) & 2)) 1900 r1++; 1901 1902 if (op1 & 2) { /* class 2 or 3 */ 1903 /* 1904 * get second source register 1905 */ 1906 r2 = (op1 >> 6) & 0x3e; 1907 if (fmt == 2) 1908 r2++; 1909 1910 if ((op1 & 1) == 0) { /* class 2 */ 1911 /* Opclass 2: 2 sources, no destination */ 1912 switch((op1 >> 4) & 7) { 1913 case 0: 1914 p = "cmp"; 1915 break; 1916 default: 1917 db_printf(fcoprUndef); 1918 return(0); 1919 } 1920 db_printf("%s,%s",p,fmtStrTbl[fmt]); 1921 db_printf(",%s\t%%f%s,%%f%s", 1922 condStrTbl[op2], ST(r1), ST(r2)); 1923 return (1); 1924 } 1925 /* 1926 * get target register (class 3) 1927 */ 1928 t = (op2 << 1); 1929 if ((fmt & 1) == 0 && (Uid(w) & 1)) 1930 t++; 1931 /* Opclass 3: 2 sources, 1 destination */ 1932 switch((op1 >> 4) & 7) { 1933 case 0: p = "add"; break; 1934 case 1: p = "sub"; break; 1935 case 2: p = (Fpi(w)) ? "mpyi" : "mpy"; break; 1936 case 3: p = "div"; break; 1937 case 4: p = "rem"; break; 1938 default: db_printf(fcoprUndef); return (0); 1939 } 1940 db_printf("%s,%s", p, fmtStrTbl[fmt]); 1941 db_printf("\t%%f%s,%%f%s,%%f%s",ST(r1),ST(r2),ST(t)); 1942 } else if (op1 & 1) { /* class 1 */ 1943 dfmt = (op1 >> 4) & 3; 1944 #define DT(r) ((dfmt & 1)? fdreg[(r)]:fsreg[(r)]) 1945 1946 /* 1947 * get target register 1948 */ 1949 t = (op2 << 1); 1950 if ((dfmt & 1) == 0 && (Uid(w) & 1)) 1951 t++; 1952 /* Opclass 1: 1 source, 1 destination conversions */ 1953 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 1954 #if 0 1955 switch((op1 >> 6) & 3) { 1956 default: 1957 case 0: p = "ff"; break; 1958 case 1: p = "xf"; break; 1959 case 2: p = "fx"; break; 1960 case 3: p = "fxt"; break; 1961 } 1962 #endif 1963 db_printf("%s,%s", p, fmtStrTbl[fmt]); 1964 db_printf(",%s\t%%f%s,%%f%s",fmtStrTbl[dfmt],ST(r1),DT(t)); 1965 } else { /* class 0 */ 1966 /* 1967 * get target register 1968 */ 1969 t = (op2 << 1); 1970 if ((fmt & 1) == 0 && (Uid(w) & 1)) 1971 t++; 1972 /* Opclass 0: 1 source, 1 destination */ 1973 switch((op1 >> 4) & 7) { 1974 case 1: p = "rsqrt"; break; 1975 case 2: p = "cpy"; break; 1976 case 3: p = "abs"; break; 1977 case 4: p = "sqrt"; break; 1978 case 5: p = "rnd"; break; 1979 default: db_printf(fcoprUndef); return (0); 1980 } 1981 db_printf("%s,%s",p,fmtStrTbl[fmt]); 1982 db_printf("\t%%f%s,%%f%s",ST(r1),ST(t)); 1983 } 1984 return (1); 1985 } 1986 1987 int 1988 fcoprDasm(union insn w, u_int op1, u_int op2) 1989 { 1990 u_int r1, r2, t, fmt, dfmt; 1991 char *p; 1992 1993 if (AstNu(w) && op1 == ((1<<4) | 2)) { 1994 if (op2 == 0 || op2 == 1 || op2 == 2) { 1995 db_printf("ftest"); 1996 if (op2 == 1) 1997 db_printf(",acc"); 1998 else if (op2 == 2) 1999 db_printf(",rej"); 2000 return (1); 2001 } 2002 return (0); 2003 } else if (0 == op1 && 0 == op2) { 2004 db_printf("fcopr identify"); 2005 return (1); 2006 } 2007 switch(op1 & 3) { 2008 case 0: 2009 /* Opclass 0: 1 source, 1 destination */ 2010 r1 = (op1 >> 12) & 0x1f; t = op2; fmt = (op1 >> 2) & 3; 2011 switch((op1 >> 4) & 7) { 2012 case 1: p = "rsqrt"; break; 2013 case 2: p = "cpy"; break; 2014 case 3: p = "abs"; break; 2015 case 4: p = "sqrt"; break; 2016 case 5: p = "rnd"; break; 2017 default: db_printf(fcoprUndef); return(0); 2018 } 2019 db_printf("f%s,%s\t%%fr%d,%%fr%d", p, fmtStrTbl[fmt], r1, t); 2020 break; 2021 case 1: 2022 /* Opclass 1: 1 source, 1 destination conversions */ 2023 r1 = (op1 >> 12) & 0x1f; t = op2; 2024 fmt = (op1 >> 2) & 3; dfmt = (op1 >> 4) & 3; 2025 p = &"ff\0\0xf\0\0fx\0\0fxt\0"[((op1) >> 4) & 0x0c]; 2026 #if 0 2027 switch((op1 >> 6) & 3) { 2028 case 0: p = "ff"; break; 2029 case 1: p = "xf"; break; 2030 case 2: p = "fx"; break; 2031 case 3: p = "fxt"; break; 2032 } 2033 #endif 2034 db_printf("fcnv%s,%s,%s\t%%fr%d,%%fr%d", 2035 p, fmtStrTbl[fmt], fmtStrTbl[dfmt], r1, t); 2036 break; 2037 case 2: 2038 /* Opclass 2: 2 sources, no destination */ 2039 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; 2040 fmt = (op1 >> 2) & 3; 2041 switch((op1 >> 4) & 7) { 2042 case 0: p = "fcmp"; break; 2043 default: db_printf(fcoprUndef); return (0); 2044 } 2045 db_printf("%s,%s,%s\t%%fr%d,%%fr%d", 2046 p,fmtStrTbl[fmt],condStrTbl[op2],r1,r2); 2047 break; 2048 case 3: 2049 /* Opclass 3: 2 sources, 1 destination */ 2050 r1 = (op1 >> 12) & 0x1f; r2 = (op1 >> 7) & 0x1f; t = op2; 2051 fmt = (op1 >> 2) & 3; 2052 switch((op1 >> 4) & 7) { 2053 case 0: p = "add"; break; 2054 case 1: p = "sub"; break; 2055 case 2: p = "mpy"; break; 2056 case 3: p = "div"; break; 2057 case 4: p = "rem"; break; 2058 default: db_printf(fcoprUndef); return (0); 2059 } 2060 db_printf("f%s,%s\t%%fr%d,%%fr%d,%%fr%d", 2061 p, fmtStrTbl[fmt], r1, r2, t); 2062 break; 2063 default: 2064 db_printf(fcoprUndef); 2065 return(0); 2066 } 2067 return (1); 2068 } 2069 2070 int 2071 coprDasm(const struct inst *i, OFS ofs, union insn w) 2072 { 2073 u_int uid = Uid(w); 2074 int load = 0; 2075 char *pfx = uid > 1 ? "c" : "f"; 2076 int dreg = 0; 2077 2078 if (Match("copr")) { 2079 if (uid) { 2080 db_printf("copr,%d,0x%x",uid,CoprExt(w)); 2081 if (AstNu(w)) 2082 db_printf(",n"); 2083 return (1); 2084 } 2085 return fcoprDasm(w, CoprExt1(w),CoprExt2(w)); 2086 } 2087 if (Match("cldd")) { 2088 dreg = 1; 2089 load = 1; 2090 db_printf("%sldd",pfx); 2091 } else if (Match("cldw")) { 2092 load = 1; 2093 db_printf("%sldw",pfx); 2094 } else if (Match("cstd")) { 2095 dreg = 1; 2096 db_printf("%sstd",pfx); 2097 } else if (Match("cstw")) 2098 db_printf("%sstw",pfx); 2099 else { 2100 db_printf("copr???"); 2101 return (0); 2102 } 2103 if (ShortDisp(w)) { 2104 db_printf("s"); 2105 if (AstNu(w)) 2106 db_printf(",m%s", ModBefore(w)?"b":"a"); 2107 } 2108 else { 2109 db_printf("x"); 2110 if (AstNu(w)) 2111 db_printf(",%sm", IndxShft(w)?"s":""); 2112 else if (IndxShft(w)) 2113 db_printf(",s"); 2114 } 2115 switch (CacheCtrl(w)) { 2116 case NOACTION: break; 2117 case STACKREF: db_printf(",c"); break; 2118 case SEQPASS: db_printf(",q"); break; 2119 case PREFETCH: db_printf(",p"); break; 2120 } 2121 if (load) { 2122 const char *p; 2123 2124 if (dreg) 2125 p = fdreg[(Rtc(w)<<1)+(uid&1)]; 2126 else 2127 p = fsreg[(Rtc(w)<<1)+(uid&1)]; 2128 2129 if (ShortDisp(w)) 2130 db_printf("\t%d",Ima5(w)); 2131 else 2132 db_printf("\t%%r%d",Rsa(w)); 2133 if (Dss(w)) 2134 db_printf("(%%sr%d,%%r%d),%%f%s", Dss(w),Rsb(w), p); 2135 else 2136 db_printf("(%%r%d),%%f%s",Rsb(w), p); 2137 } else { 2138 const char *p; 2139 2140 if (dreg) 2141 p = fdreg[(Rsc(w)<<1)+(uid&1)]; 2142 else 2143 p = fsreg[(Rsc(w)<<1)+(uid&1)]; 2144 2145 if (ShortDisp(w)) 2146 db_printf("\t%%f%s,%d", p, Ima5(w)); 2147 else 2148 db_printf("\t%%f%s,%%r%d", p, Rta(w)); 2149 if (Dss(w)) 2150 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2151 else 2152 db_printf("(%%r%d)",Rsb(w)); 2153 } 2154 return (1); 2155 } 2156 2157 int 2158 lpkDasm(const struct inst *i, OFS ofs, union insn w) 2159 { 2160 /* 2161 * Floating point STore Quad 2162 * Short or Indexed 2163 */ 2164 if (ShortDisp(w)) { 2165 if (Modify(w)) 2166 db_printf(",m%s", ModBefore(w)?"b":"a"); 2167 } else { 2168 if (Modify(w)) 2169 db_printf(",%sm", IndxShft(w)? "s":""); 2170 else if (IndxShft(w)) 2171 db_printf(",s"); 2172 } 2173 switch (CacheCtrl(w)) { 2174 case NOACTION: break; 2175 case STACKREF: db_printf(",c"); break; 2176 case SEQPASS: db_printf(",q"); break; 2177 case PREFETCH: db_printf(",p"); break; 2178 } 2179 if (ShortDisp(w)) 2180 db_printf("\t%%fr%d,%d",Rsc(w),Ima5(w)); 2181 else 2182 db_printf("\t%%fr%d,%%r%d",Rsc(w),Rta(w)); 2183 if (Dss(w)) 2184 db_printf("(%%sr%d,%%r%d)",Dss(w),Rsb(w)); 2185 else 2186 db_printf("(%%r%d)",Rsb(w)); 2187 return (1); 2188 } 2189 2190 int 2191 diagDasm(const struct inst *i, OFS ofs, union insn w) 2192 { 2193 if (0x0b0 == BitfR(w,19,8,_b198)) /* mtcpu */ 2194 db_printf("mtcpu\t%%r%d,%%dr%d", Rsa(w), Rtb(w)); 2195 else if (0x0d0 == BitfR(w,19,8,_b198)) /* mfcpu */ 2196 db_printf("mfcpu\t%%dr%d,%%r%d", Rsb(w), Rta(w)); 2197 else { 2198 db_printf(i->mnem); 2199 if (Match("diag")) 2200 db_printf("\t0x%X",w.w & 0x03ffffff); 2201 else { 2202 db_printf("?????"); 2203 return (0); 2204 } 2205 } 2206 return (1); 2207 } 2208 2209 int 2210 fmpysubDasm(const struct inst *i, OFS ofs, union insn w) 2211 { 2212 if (SinglePrec(w)) 2213 db_printf("SUB,SGL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2214 fsreg[Ms1(w)], fsreg[Ms2(w)], fsreg[Mt(w)], 2215 fsreg[As(w)], fsreg[Ad(w)]); 2216 else 2217 db_printf("SUB,DBL\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2218 fdreg[Ms1(w)], fdreg[Ms2(w)], fdreg[Mt(w)], 2219 fdreg[As(w)], fdreg[Ad(w)]); 2220 return (1); 2221 } 2222 2223 int 2224 fmpyaddDasm(const struct inst *i, OFS ofs, union insn w) 2225 { 2226 const char 2227 *ms1 = SinglePrec(w) ? fsreg[Ms1(w)] : fdreg[Ms1(w)], 2228 *ms2 = SinglePrec(w) ? fsreg[Ms2(w)] : fdreg[Ms2(w)], 2229 *mt = SinglePrec(w) ? fsreg[Mt(w)] : fdreg[Mt(w)], 2230 *as = SinglePrec(w) ? fsreg[As(w)] : fdreg[As(w)], 2231 *ad = SinglePrec(w) ? fsreg[Ad(w)] : fdreg[Ad(w)]; 2232 2233 if (Rsd(w) == 0) 2234 db_printf("\t%%fcfxt,%s,%%f%s,%%f%s,%%f%s", 2235 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt); 2236 else 2237 db_printf("add%s\t%%f%s,%%f%s,%%f%s,%%f%s,%%f%s", 2238 ((SinglePrec(w)) ? "sgl" : "dbl"), ms1, ms2, mt, as, ad); 2239 2240 return (1); 2241 } 2242 2243 vaddr_t 2244 db_disasm(vaddr_t loc, boolean_t flag) 2245 { 2246 const struct inst *i; 2247 const struct majoropcode *m; 2248 u_int ext; 2249 union insn instruct; 2250 OFS ofs = 0; 2251 2252 iExInit(); 2253 2254 if (USERMODE(loc)) { 2255 if (copyin((caddr_t)(loc &~ HPPA_PC_PRIV_MASK), 2256 &instruct, sizeof(instruct))) 2257 instruct.w = 0; 2258 } else 2259 instruct.w = *(int *)loc; 2260 2261 m = &majopcs[Opcode(instruct)]; 2262 ext = OpExt(instruct.w, m); 2263 if (ext <= m->maxsubop) { 2264 /* special hack for majopcs table layout */ 2265 if (m->maxsubop == 1) 2266 i = (const struct inst *)m->subops; 2267 else 2268 i = m->subops[ext]; 2269 2270 if (i->dasmfcn != coprDasm && i->dasmfcn != diagDasm && 2271 i->dasmfcn != ariDasm && i->dasmfcn != scDasm && 2272 i->dasmfcn != ldDasm) 2273 db_printf(i->mnem); 2274 if (i->dasmfcn) 2275 (*i->dasmfcn)(i, ofs, instruct); 2276 else if (i->mnem[0] == '?') 2277 db_printf(illeg.mnem); 2278 } else 2279 db_printf(illeg.mnem); 2280 2281 db_printf("\n"); 2282 return (loc + sizeof(instruct)); 2283 } 2284
Indexes created Sun Sep 28 12:09:53 GMT 2025