fpu.c revision 1.19
1 /* $NetBSD: fpu.c,v 1.19 2009/11/21 15:36:33 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * FPU handling for NetBSD/hppa. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.19 2009/11/21 15:36:33 rmind Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/proc.h> 42 #include <sys/signalvar.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/cpufunc.h> 47 #include <machine/frame.h> 48 #include <machine/reg.h> 49 #include <machine/pmap.h> 50 51 #include <hppa/hppa/machdep.h> 52 53 #include "../spmath/float.h" 54 #include "../spmath/fpudispatch.h" 55 56 /* Some macros representing opcodes. */ 57 #define OPCODE_NOP 0x08000240 58 #define OPCODE_COPR_0_0 0x30000000 59 60 /* Some macros representing fields in load/store opcodes. */ 61 #define OPCODE_CMPLT_S 0x00002000 62 #define OPCODE_CMPLT_M 0x00000020 63 #define OPCODE_CMPLT_SM (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 64 #define OPCODE_CMPLT_MB OPCODE_CMPLT_M 65 #define OPCODE_CMPLT_MA (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 66 #define OPCODE_CMPLT (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 67 #define OPCODE_DOUBLE 0x08000000 68 #define OPCODE_STORE 0x00000200 69 #define OPCODE_INDEXED 0x00001000 70 71 /* This is nonzero iff we're using a hardware FPU. */ 72 int fpu_present; 73 74 /* If we have any FPU, this is its version. */ 75 u_int fpu_version; 76 77 /* The number of times we have had to switch the FPU context. */ 78 u_int fpu_csw; 79 80 /* The U-space physical address of the proc in the FPU, or zero. */ 81 paddr_t fpu_cur_uspace; 82 83 /* In locore.S, this swaps states in and out of the FPU. */ 84 void hppa_fpu_swap(struct pcb *, struct pcb *); 85 86 #ifdef FPEMUL 87 /* 88 * Given a trapframe and a general register number, the 89 * FRAME_REG macro returns a pointer to that general 90 * register. The _frame_reg_positions array is a lookup 91 * table, since the general registers aren't in order 92 * in a trapframe. 93 * 94 * NB: this more or less assumes that all members of 95 * struct trapframe are u_ints. 96 */ 97 #define FRAME_REG(f, reg, r0) \ 98 ((reg) == 0 ? (&r0) : ((&(f)->tf_t1) + _frame_reg_positions[reg])) 99 #define _FRAME_POSITION(f) \ 100 ((&((struct trapframe *) 0)->f) - (&((struct trapframe *) 0)->tf_t1)) 101 const int _frame_reg_positions[32] = { 102 -1, /* r0 */ 103 _FRAME_POSITION(tf_r1), 104 _FRAME_POSITION(tf_rp), /* r2 */ 105 _FRAME_POSITION(tf_r3), 106 _FRAME_POSITION(tf_r4), 107 _FRAME_POSITION(tf_r5), 108 _FRAME_POSITION(tf_r6), 109 _FRAME_POSITION(tf_r7), 110 _FRAME_POSITION(tf_r8), 111 _FRAME_POSITION(tf_r9), 112 _FRAME_POSITION(tf_r10), 113 _FRAME_POSITION(tf_r11), 114 _FRAME_POSITION(tf_r12), 115 _FRAME_POSITION(tf_r13), 116 _FRAME_POSITION(tf_r14), 117 _FRAME_POSITION(tf_r15), 118 _FRAME_POSITION(tf_r16), 119 _FRAME_POSITION(tf_r17), 120 _FRAME_POSITION(tf_r18), 121 _FRAME_POSITION(tf_t4), /* r19 */ 122 _FRAME_POSITION(tf_t3), /* r20 */ 123 _FRAME_POSITION(tf_t2), /* r21 */ 124 _FRAME_POSITION(tf_t1), /* r22 */ 125 _FRAME_POSITION(tf_arg3), /* r23 */ 126 _FRAME_POSITION(tf_arg2), /* r24 */ 127 _FRAME_POSITION(tf_arg1), /* r25 */ 128 _FRAME_POSITION(tf_arg0), /* r26 */ 129 _FRAME_POSITION(tf_dp), /* r27 */ 130 _FRAME_POSITION(tf_ret0), /* r28 */ 131 _FRAME_POSITION(tf_ret1), /* r29 */ 132 _FRAME_POSITION(tf_sp), /* r30 */ 133 _FRAME_POSITION(tf_r31), 134 }; 135 #endif /* FPEMUL */ 136 137 /* 138 * Bootstraps the FPU. 139 */ 140 void 141 hppa_fpu_bootstrap(u_int ccr_enable) 142 { 143 uint32_t junk[2]; 144 uint32_t vers[2]; 145 extern u_int hppa_fpu_nop0; 146 extern u_int hppa_fpu_nop1; 147 148 /* See if we have a present and functioning hardware FPU. */ 149 fpu_present = (ccr_enable & HPPA_FPUS) == HPPA_FPUS; 150 151 /* Initialize the FPU and get its version. */ 152 if (fpu_present) { 153 154 /* 155 * To somewhat optimize the emulation 156 * assist trap handling and context 157 * switching (to save them from having 158 * to always load and check fpu_present), 159 * there are two instructions in locore.S 160 * that are replaced with nops when 161 * there is a hardware FPU. 162 */ 163 hppa_fpu_nop0 = OPCODE_NOP; 164 hppa_fpu_nop1 = OPCODE_NOP; 165 fcacheall(); 166 167 /* 168 * We track what process has the FPU, 169 * and how many times we have to swap 170 * in and out. 171 */ 172 173 /* 174 * The PA-RISC 1.1 Architecture manual is 175 * pretty clear that the copr,0,0 must be 176 * wrapped in double word stores of fr0, 177 * otherwise its operation is undefined. 178 */ 179 __asm volatile( 180 " ldo %0, %%r22 \n" 181 " fstds %%fr0, 0(%%r22) \n" 182 " ldo %1, %%r22 \n" 183 " copr,0,0 \n" 184 " fstds %%fr0, 0(%%r22) \n" 185 : "=m" (junk), "=m" (vers) : : "r22"); 186 187 /* 188 * Now mark that no process has the FPU, 189 * and disable it, so the first time it 190 * gets used the process' state gets 191 * swapped in. 192 */ 193 fpu_csw = 0; 194 fpu_cur_uspace = 0; 195 mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR); 196 } 197 #ifdef FPEMUL 198 else 199 /* 200 * XXX This is a hack - to avoid 201 * having to set up the emulator so 202 * it can work for one instruction for 203 * proc0, we dispatch the copr,0,0 opcode 204 * into the emulator directly. 205 */ 206 decode_0c(OPCODE_COPR_0_0, 0, 0, vers); 207 #endif /* FPEMUL */ 208 fpu_version = vers[0]; 209 } 210 211 /* 212 * If the given LWP has its state in the FPU, 213 * flush that state out into the LWP's PCB. 214 */ 215 void 216 hppa_fpu_flush(struct lwp *l) 217 { 218 struct trapframe *tf = l->l_md.md_regs; 219 struct pcb *pcb = lwp_getpcb(l); 220 221 /* 222 * If we have a hardware FPU, and this process' 223 * state is currently in it, swap it out. 224 */ 225 226 if (!fpu_present || fpu_cur_uspace == 0 || 227 fpu_cur_uspace != tf->tf_cr30) { 228 return; 229 } 230 231 hppa_fpu_swap(pcb, NULL); 232 fpu_cur_uspace = 0; 233 } 234 235 #ifdef FPEMUL 236 237 /* 238 * This emulates a coprocessor load/store instruction. 239 */ 240 static int hppa_fpu_ls(struct trapframe *, struct lwp *); 241 static int 242 hppa_fpu_ls(struct trapframe *frame, struct lwp *l) 243 { 244 struct pcb *pcb = lwp_getpcb(l); 245 u_int inst, inst_b, inst_x, inst_s, inst_t; 246 int log2size; 247 u_int *base; 248 u_int offset, index, im5; 249 void *fpreg; 250 u_int r0 = 0; 251 int error; 252 253 /* 254 * Get the instruction that we're emulating, 255 * and break it down. Using HP bit notation, 256 * b is a five-bit field starting at bit 10, 257 * x is a five-bit field starting at bit 15, 258 * s is a two-bit field starting at bit 17, 259 * and t is a five-bit field starting at bit 31. 260 */ 261 inst = frame->tf_iir; 262 __asm volatile( 263 " extru %4, 10, 5, %1 \n" 264 " extru %4, 15, 5, %2 \n" 265 " extru %4, 17, 2, %3 \n" 266 " extru %4, 31, 5, %4 \n" 267 : "=r" (inst_b), "=r" (inst_x), "=r" (inst_s), "=r" (inst_t) 268 : "r" (inst)); 269 270 /* 271 * The space must be the user's space, else we 272 * segfault. 273 */ 274 if (inst_s != pcb->pcb_space) 275 return (EFAULT); 276 277 /* See whether or not this is a doubleword load/store. */ 278 log2size = (inst & OPCODE_DOUBLE) ? 3 : 2; 279 280 /* Get the floating point register. */ 281 fpreg = ((char *)pcb->pcb_fpregs) + (inst_t << log2size); 282 283 /* Get the base register. */ 284 base = FRAME_REG(frame, inst_b, r0); 285 286 /* Dispatch on whether or not this is an indexed load/store. */ 287 if (inst & OPCODE_INDEXED) { 288 289 /* Get the index register value. */ 290 index = *FRAME_REG(frame, inst_x, r0); 291 292 /* Dispatch on the completer. */ 293 switch (inst & OPCODE_CMPLT) { 294 case OPCODE_CMPLT_S: 295 offset = *base + (index << log2size); 296 break; 297 case OPCODE_CMPLT_M: 298 offset = *base; 299 *base = *base + index; 300 break; 301 case OPCODE_CMPLT_SM: 302 offset = *base; 303 *base = *base + (index << log2size); 304 break; 305 default: 306 offset = *base + index; 307 break; 308 } 309 } else { 310 311 /* Do a low_sign_ext(x, 5). */ 312 im5 = inst_x >> 1; 313 if (inst_x & 1) 314 im5 |= 0xfffffff0; 315 316 /* Dispatch on the completer. */ 317 switch (inst & OPCODE_CMPLT) { 318 case OPCODE_CMPLT_MB: 319 offset = *base + im5; 320 *base = *base + im5; 321 break; 322 case OPCODE_CMPLT_MA: 323 offset = *base; 324 *base = *base + im5; 325 break; 326 default: 327 offset = *base + im5; 328 break; 329 } 330 } 331 332 /* 333 * The offset we calculated must be the same as the 334 * offset in the IOR. 335 */ 336 KASSERT(offset == frame->tf_ior); 337 338 /* Perform the load or store. */ 339 error = (inst & OPCODE_STORE) ? 340 copyout(fpreg, (void *) offset, 1 << log2size) : 341 copyin((const void *) offset, fpreg, 1 << log2size); 342 fdcache(HPPA_SID_KERNEL, (vaddr_t)fpreg, sizeof(pcb->pcb_fpregs)); 343 return error; 344 } 345 346 /* 347 * This is called to emulate an instruction. 348 */ 349 void 350 hppa_fpu_emulate(struct trapframe *frame, struct lwp *l, u_int inst) 351 { 352 struct pcb *pcb = lwp_getpcb(l); 353 u_int opcode, class, sub; 354 u_int *fpregs; 355 int exception; 356 ksiginfo_t ksi; 357 358 /* 359 * If the process' state is in any hardware FPU, 360 * flush it out - we need to operate on it. 361 */ 362 hppa_fpu_flush(l); 363 364 /* 365 * Get the instruction that we're emulating, 366 * and break it down. Using HP bit notation, 367 * the class is a two-bit field starting at 368 * bit 22, the opcode is a 6-bit field starting 369 * at bit 5, and sub for a class 1 instruction 370 * is a two bit field starting at bit 16, else 371 * it is a three bit field starting at bit 18. 372 */ 373 #if 0 374 __asm volatile( 375 " extru %3, 22, 2, %1 \n" 376 " extru %3, 5, 6, %0 \n" 377 " extru %3, 18, 3, %2 \n" 378 " comib,<> 1, %1, 0 \n" 379 " extru %3, 16, 2, %2 \n" 380 : "=r" (opcode), "=r" (class), "=r" (sub) 381 : "r" (inst)); 382 #else 383 opcode = (inst >> (31 - 5)) & 0x3f; 384 class = (inst >> (31 - 22)) & 0x3; 385 if (class == 1) { 386 sub = (inst >> (31 - 16)) & 3; 387 } else { 388 sub = (inst >> (31 - 18)) & 7; 389 } 390 #endif 391 392 /* Get this LWP's FPU registers. */ 393 fpregs = (u_int *)pcb->pcb_fpregs; 394 395 /* Dispatch on the opcode. */ 396 switch (opcode) { 397 case 0x09: 398 case 0x0b: 399 if (hppa_fpu_ls(frame, l) != 0) { 400 KSI_INIT_TRAP(&ksi); 401 ksi.ksi_signo = SIGSEGV; 402 ksi.ksi_code = SEGV_MAPERR; 403 ksi.ksi_trap = T_DTLBMISS; 404 ksi.ksi_addr = (void *)frame->tf_iioq_head; 405 trapsignal(l, &ksi); 406 } 407 return; 408 case 0x0c: 409 exception = decode_0c(inst, class, sub, fpregs); 410 break; 411 case 0x0e: 412 exception = decode_0e(inst, class, sub, fpregs); 413 break; 414 case 0x06: 415 exception = decode_06(inst, fpregs); 416 break; 417 case 0x26: 418 exception = decode_26(inst, fpregs); 419 break; 420 default: 421 exception = UNIMPLEMENTEDEXCEPTION; 422 break; 423 } 424 425 if (exception) { 426 KSI_INIT_TRAP(&ksi); 427 if (exception & UNIMPLEMENTEDEXCEPTION) { 428 ksi.ksi_signo = SIGILL; 429 ksi.ksi_code = ILL_COPROC; 430 } else { 431 ksi.ksi_signo = SIGFPE; 432 if (exception & INVALIDEXCEPTION) { 433 ksi.ksi_code = FPE_FLTINV; 434 } else if (exception & DIVISIONBYZEROEXCEPTION) { 435 ksi.ksi_code = FPE_FLTDIV; 436 } else if (exception & OVERFLOWEXCEPTION) { 437 ksi.ksi_code = FPE_FLTOVF; 438 } else if (exception & UNDERFLOWEXCEPTION) { 439 ksi.ksi_code = FPE_FLTUND; 440 } else if (exception & INEXACTEXCEPTION) { 441 ksi.ksi_code = FPE_FLTRES; 442 } 443 } 444 ksi.ksi_trap = T_EMULATION; 445 ksi.ksi_addr = (void *)frame->tf_iioq_head; 446 trapsignal(l, &ksi); 447 } 448 fdcache(HPPA_SID_KERNEL, (vaddr_t)fpregs, sizeof(pcb->pcb_fpregs)); 449 } 450 451 #endif /* FPEMUL */ 452
Indexes created Tue Sep 30 07:10:03 GMT 2025