fpu.c revision 1.20
1 /* $NetBSD: fpu.c,v 1.20 2010/03/16 16:20:19 skrll Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * FPU handling for NetBSD/hppa. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.20 2010/03/16 16:20:19 skrll Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/proc.h> 42 #include <sys/signalvar.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/cpufunc.h> 47 #include <machine/frame.h> 48 #include <machine/reg.h> 49 #include <machine/pmap.h> 50 51 #include <hppa/hppa/machdep.h> 52 53 #include "../spmath/float.h" 54 #include "../spmath/fpudispatch.h" 55 56 /* Some macros representing opcodes. */ 57 #define OPCODE_NOP 0x08000240 58 #define OPCODE_COPR_0_0 0x30000000 59 60 /* Some macros representing fields in load/store opcodes. */ 61 #define OPCODE_CMPLT_S 0x00002000 62 #define OPCODE_CMPLT_M 0x00000020 63 #define OPCODE_CMPLT_SM (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 64 #define OPCODE_CMPLT_MB OPCODE_CMPLT_M 65 #define OPCODE_CMPLT_MA (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 66 #define OPCODE_CMPLT (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 67 #define OPCODE_DOUBLE 0x08000000 68 #define OPCODE_STORE 0x00000200 69 #define OPCODE_INDEXED 0x00001000 70 71 /* This is nonzero iff we're using a hardware FPU. */ 72 int fpu_present; 73 74 /* If we have any FPU, this is its version. */ 75 u_int fpu_version; 76 77 /* The number of times we have had to switch the FPU context. */ 78 u_int fpu_csw; 79 80 /* The U-space physical address of the proc in the FPU, or zero. */ 81 paddr_t fpu_cur_uspace; 82 83 /* In locore.S, this swaps states in and out of the FPU. */ 84 void hppa_fpu_swapout(struct pcb *); 85 void hppa_fpu_swap(struct fpreg *, struct fpreg *); 86 87 #ifdef FPEMUL 88 /* 89 * Given a trapframe and a general register number, the 90 * FRAME_REG macro returns a pointer to that general 91 * register. The _frame_reg_positions array is a lookup 92 * table, since the general registers aren't in order 93 * in a trapframe. 94 * 95 * NB: this more or less assumes that all members of 96 * struct trapframe are u_ints. 97 */ 98 #define FRAME_REG(f, reg, r0) \ 99 ((reg) == 0 ? (&r0) : ((&(f)->tf_t1) + _frame_reg_positions[reg])) 100 #define _FRAME_POSITION(f) \ 101 ((&((struct trapframe *) 0)->f) - (&((struct trapframe *) 0)->tf_t1)) 102 const int _frame_reg_positions[32] = { 103 -1, /* r0 */ 104 _FRAME_POSITION(tf_r1), 105 _FRAME_POSITION(tf_rp), /* r2 */ 106 _FRAME_POSITION(tf_r3), 107 _FRAME_POSITION(tf_r4), 108 _FRAME_POSITION(tf_r5), 109 _FRAME_POSITION(tf_r6), 110 _FRAME_POSITION(tf_r7), 111 _FRAME_POSITION(tf_r8), 112 _FRAME_POSITION(tf_r9), 113 _FRAME_POSITION(tf_r10), 114 _FRAME_POSITION(tf_r11), 115 _FRAME_POSITION(tf_r12), 116 _FRAME_POSITION(tf_r13), 117 _FRAME_POSITION(tf_r14), 118 _FRAME_POSITION(tf_r15), 119 _FRAME_POSITION(tf_r16), 120 _FRAME_POSITION(tf_r17), 121 _FRAME_POSITION(tf_r18), 122 _FRAME_POSITION(tf_t4), /* r19 */ 123 _FRAME_POSITION(tf_t3), /* r20 */ 124 _FRAME_POSITION(tf_t2), /* r21 */ 125 _FRAME_POSITION(tf_t1), /* r22 */ 126 _FRAME_POSITION(tf_arg3), /* r23 */ 127 _FRAME_POSITION(tf_arg2), /* r24 */ 128 _FRAME_POSITION(tf_arg1), /* r25 */ 129 _FRAME_POSITION(tf_arg0), /* r26 */ 130 _FRAME_POSITION(tf_dp), /* r27 */ 131 _FRAME_POSITION(tf_ret0), /* r28 */ 132 _FRAME_POSITION(tf_ret1), /* r29 */ 133 _FRAME_POSITION(tf_sp), /* r30 */ 134 _FRAME_POSITION(tf_r31), 135 }; 136 #endif /* FPEMUL */ 137 138 /* 139 * Bootstraps the FPU. 140 */ 141 void 142 hppa_fpu_bootstrap(u_int ccr_enable) 143 { 144 uint32_t junk[2]; 145 uint32_t vers[2]; 146 extern u_int hppa_fpu_nop0; 147 extern u_int hppa_fpu_nop1; 148 149 /* See if we have a present and functioning hardware FPU. */ 150 fpu_present = (ccr_enable & HPPA_FPUS) == HPPA_FPUS; 151 152 /* Initialize the FPU and get its version. */ 153 if (fpu_present) { 154 155 /* 156 * To somewhat optimize the emulation 157 * assist trap handling and context 158 * switching (to save them from having 159 * to always load and check fpu_present), 160 * there are two instructions in locore.S 161 * that are replaced with nops when 162 * there is a hardware FPU. 163 */ 164 hppa_fpu_nop0 = OPCODE_NOP; 165 hppa_fpu_nop1 = OPCODE_NOP; 166 fcacheall(); 167 168 /* 169 * We track what process has the FPU, 170 * and how many times we have to swap 171 * in and out. 172 */ 173 174 /* 175 * The PA-RISC 1.1 Architecture manual is 176 * pretty clear that the copr,0,0 must be 177 * wrapped in double word stores of fr0, 178 * otherwise its operation is undefined. 179 */ 180 __asm volatile( 181 " ldo %0, %%r22 \n" 182 " fstds %%fr0, 0(%%r22) \n" 183 " ldo %1, %%r22 \n" 184 " copr,0,0 \n" 185 " fstds %%fr0, 0(%%r22) \n" 186 : "=m" (junk), "=m" (vers) : : "r22"); 187 188 /* 189 * Now mark that no process has the FPU, 190 * and disable it, so the first time it 191 * gets used the process' state gets 192 * swapped in. 193 */ 194 fpu_csw = 0; 195 fpu_cur_uspace = 0; 196 mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR); 197 } 198 #ifdef FPEMUL 199 else 200 /* 201 * XXX This is a hack - to avoid 202 * having to set up the emulator so 203 * it can work for one instruction for 204 * proc0, we dispatch the copr,0,0 opcode 205 * into the emulator directly. 206 */ 207 decode_0c(OPCODE_COPR_0_0, 0, 0, vers); 208 #endif /* FPEMUL */ 209 fpu_version = vers[0]; 210 } 211 212 /* 213 * If the given LWP has its state in the FPU, 214 * flush that state out into the LWP's PCB. 215 */ 216 void 217 hppa_fpu_flush(struct lwp *l) 218 { 219 struct trapframe *tf = l->l_md.md_regs; 220 struct pcb *pcb = lwp_getpcb(l); 221 222 /* 223 * If we have a hardware FPU, and this process' 224 * state is currently in it, swap it out. 225 */ 226 227 if (!fpu_present || fpu_cur_uspace == 0 || 228 fpu_cur_uspace != tf->tf_cr30) { 229 return; 230 } 231 232 hppa_fpu_swapout(pcb); 233 fpu_cur_uspace = 0; 234 } 235 236 #ifdef FPEMUL 237 238 /* 239 * This emulates a coprocessor load/store instruction. 240 */ 241 static int hppa_fpu_ls(struct trapframe *, struct lwp *); 242 static int 243 hppa_fpu_ls(struct trapframe *frame, struct lwp *l) 244 { 245 struct pcb *pcb = lwp_getpcb(l); 246 u_int inst, inst_b, inst_x, inst_s, inst_t; 247 int log2size; 248 u_int *base; 249 u_int offset, index, im5; 250 void *fpreg; 251 u_int r0 = 0; 252 int error; 253 254 /* 255 * Get the instruction that we're emulating, 256 * and break it down. Using HP bit notation, 257 * b is a five-bit field starting at bit 10, 258 * x is a five-bit field starting at bit 15, 259 * s is a two-bit field starting at bit 17, 260 * and t is a five-bit field starting at bit 31. 261 */ 262 inst = frame->tf_iir; 263 __asm volatile( 264 " extru %4, 10, 5, %1 \n" 265 " extru %4, 15, 5, %2 \n" 266 " extru %4, 17, 2, %3 \n" 267 " extru %4, 31, 5, %4 \n" 268 : "=r" (inst_b), "=r" (inst_x), "=r" (inst_s), "=r" (inst_t) 269 : "r" (inst)); 270 271 /* 272 * The space must be the user's space, else we 273 * segfault. 274 */ 275 if (inst_s != pcb->pcb_space) 276 return (EFAULT); 277 278 /* See whether or not this is a doubleword load/store. */ 279 log2size = (inst & OPCODE_DOUBLE) ? 3 : 2; 280 281 /* Get the floating point register. */ 282 fpreg = ((char *)pcb->pcb_fpregs) + (inst_t << log2size); 283 284 /* Get the base register. */ 285 base = FRAME_REG(frame, inst_b, r0); 286 287 /* Dispatch on whether or not this is an indexed load/store. */ 288 if (inst & OPCODE_INDEXED) { 289 290 /* Get the index register value. */ 291 index = *FRAME_REG(frame, inst_x, r0); 292 293 /* Dispatch on the completer. */ 294 switch (inst & OPCODE_CMPLT) { 295 case OPCODE_CMPLT_S: 296 offset = *base + (index << log2size); 297 break; 298 case OPCODE_CMPLT_M: 299 offset = *base; 300 *base = *base + index; 301 break; 302 case OPCODE_CMPLT_SM: 303 offset = *base; 304 *base = *base + (index << log2size); 305 break; 306 default: 307 offset = *base + index; 308 break; 309 } 310 } else { 311 312 /* Do a low_sign_ext(x, 5). */ 313 im5 = inst_x >> 1; 314 if (inst_x & 1) 315 im5 |= 0xfffffff0; 316 317 /* Dispatch on the completer. */ 318 switch (inst & OPCODE_CMPLT) { 319 case OPCODE_CMPLT_MB: 320 offset = *base + im5; 321 *base = *base + im5; 322 break; 323 case OPCODE_CMPLT_MA: 324 offset = *base; 325 *base = *base + im5; 326 break; 327 default: 328 offset = *base + im5; 329 break; 330 } 331 } 332 333 /* 334 * The offset we calculated must be the same as the 335 * offset in the IOR. 336 */ 337 KASSERT(offset == frame->tf_ior); 338 339 /* Perform the load or store. */ 340 error = (inst & OPCODE_STORE) ? 341 copyout(fpreg, (void *) offset, 1 << log2size) : 342 copyin((const void *) offset, fpreg, 1 << log2size); 343 return error; 344 } 345 346 /* 347 * This is called to emulate an instruction. 348 */ 349 void 350 hppa_fpu_emulate(struct trapframe *frame, struct lwp *l, u_int inst) 351 { 352 struct pcb *pcb = lwp_getpcb(l); 353 u_int opcode, class, sub; 354 u_int *fpregs; 355 int exception; 356 ksiginfo_t ksi; 357 358 /* 359 * If the process' state is in any hardware FPU, 360 * flush it out - we need to operate on it. 361 */ 362 hppa_fpu_flush(l); 363 364 /* 365 * Get the instruction that we're emulating, 366 * and break it down. Using HP bit notation, 367 * the class is a two-bit field starting at 368 * bit 22, the opcode is a 6-bit field starting 369 * at bit 5, and sub for a class 1 instruction 370 * is a two bit field starting at bit 16, else 371 * it is a three bit field starting at bit 18. 372 */ 373 #if 0 374 __asm volatile( 375 " extru %3, 22, 2, %1 \n" 376 " extru %3, 5, 6, %0 \n" 377 " extru %3, 18, 3, %2 \n" 378 " comib,<> 1, %1, 0 \n" 379 " extru %3, 16, 2, %2 \n" 380 : "=r" (opcode), "=r" (class), "=r" (sub) 381 : "r" (inst)); 382 #else 383 opcode = (inst >> (31 - 5)) & 0x3f; 384 class = (inst >> (31 - 22)) & 0x3; 385 if (class == 1) { 386 sub = (inst >> (31 - 16)) & 3; 387 } else { 388 sub = (inst >> (31 - 18)) & 7; 389 } 390 #endif 391 392 /* Get this LWP's FPU registers. */ 393 fpregs = (u_int *)pcb->pcb_fpregs; 394 395 /* Dispatch on the opcode. */ 396 switch (opcode) { 397 case 0x09: 398 case 0x0b: 399 if (hppa_fpu_ls(frame, l) != 0) { 400 KSI_INIT_TRAP(&ksi); 401 ksi.ksi_signo = SIGSEGV; 402 ksi.ksi_code = SEGV_MAPERR; 403 ksi.ksi_trap = T_DTLBMISS; 404 ksi.ksi_addr = (void *)frame->tf_iioq_head; 405 trapsignal(l, &ksi); 406 } 407 return; 408 case 0x0c: 409 exception = decode_0c(inst, class, sub, fpregs); 410 break; 411 case 0x0e: 412 exception = decode_0e(inst, class, sub, fpregs); 413 break; 414 case 0x06: 415 exception = decode_06(inst, fpregs); 416 break; 417 case 0x26: 418 exception = decode_26(inst, fpregs); 419 break; 420 default: 421 exception = UNIMPLEMENTEDEXCEPTION; 422 break; 423 } 424 425 if (exception) { 426 KSI_INIT_TRAP(&ksi); 427 if (exception & UNIMPLEMENTEDEXCEPTION) { 428 ksi.ksi_signo = SIGILL; 429 ksi.ksi_code = ILL_COPROC; 430 } else { 431 ksi.ksi_signo = SIGFPE; 432 if (exception & INVALIDEXCEPTION) { 433 ksi.ksi_code = FPE_FLTINV; 434 } else if (exception & DIVISIONBYZEROEXCEPTION) { 435 ksi.ksi_code = FPE_FLTDIV; 436 } else if (exception & OVERFLOWEXCEPTION) { 437 ksi.ksi_code = FPE_FLTOVF; 438 } else if (exception & UNDERFLOWEXCEPTION) { 439 ksi.ksi_code = FPE_FLTUND; 440 } else if (exception & INEXACTEXCEPTION) { 441 ksi.ksi_code = FPE_FLTRES; 442 } 443 } 444 ksi.ksi_trap = T_EMULATION; 445 ksi.ksi_addr = (void *)frame->tf_iioq_head; 446 trapsignal(l, &ksi); 447 } 448 } 449 450 #endif /* FPEMUL */ 451
Indexes created Tue Sep 30 17:09:57 GMT 2025