fpu.c revision 1.22
1 /* $NetBSD: fpu.c,v 1.22 2011/01/14 02:06:26 rmind Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * FPU handling for NetBSD/hppa. 34 */ 35 36 #include <sys/cdefs.h> 37 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.22 2011/01/14 02:06:26 rmind Exp $"); 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/proc.h> 42 #include <sys/signalvar.h> 43 44 #include <uvm/uvm_extern.h> 45 46 #include <machine/cpufunc.h> 47 #include <machine/frame.h> 48 #include <machine/reg.h> 49 #include <machine/pcb.h> 50 #include <machine/pmap.h> 51 52 #include <hppa/hppa/machdep.h> 53 54 #include "../spmath/float.h" 55 #include "../spmath/fpudispatch.h" 56 57 /* Some macros representing opcodes. */ 58 #define OPCODE_NOP 0x08000240 59 #define OPCODE_COPR_0_0 0x30000000 60 61 /* Some macros representing fields in load/store opcodes. */ 62 #define OPCODE_CMPLT_S 0x00002000 63 #define OPCODE_CMPLT_M 0x00000020 64 #define OPCODE_CMPLT_SM (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 65 #define OPCODE_CMPLT_MB OPCODE_CMPLT_M 66 #define OPCODE_CMPLT_MA (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 67 #define OPCODE_CMPLT (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 68 #define OPCODE_DOUBLE 0x08000000 69 #define OPCODE_STORE 0x00000200 70 #define OPCODE_INDEXED 0x00001000 71 72 /* This is nonzero iff we're using a hardware FPU. */ 73 int fpu_present; 74 75 /* If we have any FPU, this is its version. */ 76 u_int fpu_version; 77 78 /* The number of times we have had to switch the FPU context. */ 79 u_int fpu_csw; 80 81 /* The U-space physical address of the proc in the FPU, or zero. */ 82 paddr_t fpu_cur_uspace; 83 84 /* In locore.S, this swaps states in and out of the FPU. */ 85 void hppa_fpu_swapout(struct pcb *); 86 void hppa_fpu_swap(struct fpreg *, struct fpreg *); 87 88 #ifdef FPEMUL 89 /* 90 * Given a trapframe and a general register number, the 91 * FRAME_REG macro returns a pointer to that general 92 * register. The _frame_reg_positions array is a lookup 93 * table, since the general registers aren't in order 94 * in a trapframe. 95 * 96 * NB: this more or less assumes that all members of 97 * struct trapframe are u_ints. 98 */ 99 #define FRAME_REG(f, reg, r0) \ 100 ((reg) == 0 ? (&r0) : ((&(f)->tf_t1) + _frame_reg_positions[reg])) 101 #define _FRAME_POSITION(f) \ 102 ((&((struct trapframe *) 0)->f) - (&((struct trapframe *) 0)->tf_t1)) 103 const int _frame_reg_positions[32] = { 104 -1, /* r0 */ 105 _FRAME_POSITION(tf_r1), 106 _FRAME_POSITION(tf_rp), /* r2 */ 107 _FRAME_POSITION(tf_r3), 108 _FRAME_POSITION(tf_r4), 109 _FRAME_POSITION(tf_r5), 110 _FRAME_POSITION(tf_r6), 111 _FRAME_POSITION(tf_r7), 112 _FRAME_POSITION(tf_r8), 113 _FRAME_POSITION(tf_r9), 114 _FRAME_POSITION(tf_r10), 115 _FRAME_POSITION(tf_r11), 116 _FRAME_POSITION(tf_r12), 117 _FRAME_POSITION(tf_r13), 118 _FRAME_POSITION(tf_r14), 119 _FRAME_POSITION(tf_r15), 120 _FRAME_POSITION(tf_r16), 121 _FRAME_POSITION(tf_r17), 122 _FRAME_POSITION(tf_r18), 123 _FRAME_POSITION(tf_t4), /* r19 */ 124 _FRAME_POSITION(tf_t3), /* r20 */ 125 _FRAME_POSITION(tf_t2), /* r21 */ 126 _FRAME_POSITION(tf_t1), /* r22 */ 127 _FRAME_POSITION(tf_arg3), /* r23 */ 128 _FRAME_POSITION(tf_arg2), /* r24 */ 129 _FRAME_POSITION(tf_arg1), /* r25 */ 130 _FRAME_POSITION(tf_arg0), /* r26 */ 131 _FRAME_POSITION(tf_dp), /* r27 */ 132 _FRAME_POSITION(tf_ret0), /* r28 */ 133 _FRAME_POSITION(tf_ret1), /* r29 */ 134 _FRAME_POSITION(tf_sp), /* r30 */ 135 _FRAME_POSITION(tf_r31), 136 }; 137 #endif /* FPEMUL */ 138 139 /* 140 * Bootstraps the FPU. 141 */ 142 void 143 hppa_fpu_bootstrap(u_int ccr_enable) 144 { 145 uint32_t junk[2]; 146 uint32_t vers[2]; 147 extern u_int hppa_fpu_nop0; 148 extern u_int hppa_fpu_nop1; 149 150 /* See if we have a present and functioning hardware FPU. */ 151 fpu_present = (ccr_enable & HPPA_FPUS) == HPPA_FPUS; 152 153 /* Initialize the FPU and get its version. */ 154 if (fpu_present) { 155 156 /* 157 * To somewhat optimize the emulation 158 * assist trap handling and context 159 * switching (to save them from having 160 * to always load and check fpu_present), 161 * there are two instructions in locore.S 162 * that are replaced with nops when 163 * there is a hardware FPU. 164 */ 165 hppa_fpu_nop0 = OPCODE_NOP; 166 hppa_fpu_nop1 = OPCODE_NOP; 167 fcacheall(); 168 169 /* 170 * We track what process has the FPU, 171 * and how many times we have to swap 172 * in and out. 173 */ 174 175 /* 176 * The PA-RISC 1.1 Architecture manual is 177 * pretty clear that the copr,0,0 must be 178 * wrapped in double word stores of fr0, 179 * otherwise its operation is undefined. 180 */ 181 __asm volatile( 182 " ldo %0, %%r22 \n" 183 " fstds %%fr0, 0(%%r22) \n" 184 " ldo %1, %%r22 \n" 185 " copr,0,0 \n" 186 " fstds %%fr0, 0(%%r22) \n" 187 : "=m" (junk), "=m" (vers) : : "r22"); 188 189 /* 190 * Now mark that no process has the FPU, 191 * and disable it, so the first time it 192 * gets used the process' state gets 193 * swapped in. 194 */ 195 fpu_csw = 0; 196 fpu_cur_uspace = 0; 197 mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR); 198 } 199 #ifdef FPEMUL 200 else 201 /* 202 * XXX This is a hack - to avoid 203 * having to set up the emulator so 204 * it can work for one instruction for 205 * proc0, we dispatch the copr,0,0 opcode 206 * into the emulator directly. 207 */ 208 decode_0c(OPCODE_COPR_0_0, 0, 0, vers); 209 #endif /* FPEMUL */ 210 fpu_version = vers[0]; 211 } 212 213 /* 214 * If the given LWP has its state in the FPU, 215 * flush that state out into the LWP's PCB. 216 */ 217 void 218 hppa_fpu_flush(struct lwp *l) 219 { 220 struct trapframe *tf = l->l_md.md_regs; 221 struct pcb *pcb = lwp_getpcb(l); 222 223 /* 224 * If we have a hardware FPU, and this process' 225 * state is currently in it, swap it out. 226 */ 227 228 if (!fpu_present || fpu_cur_uspace == 0 || 229 fpu_cur_uspace != tf->tf_cr30) { 230 return; 231 } 232 233 hppa_fpu_swapout(pcb); 234 fpu_cur_uspace = 0; 235 } 236 237 #ifdef FPEMUL 238 239 /* 240 * This emulates a coprocessor load/store instruction. 241 */ 242 static int hppa_fpu_ls(struct trapframe *, struct lwp *); 243 static int 244 hppa_fpu_ls(struct trapframe *frame, struct lwp *l) 245 { 246 struct pcb *pcb = lwp_getpcb(l); 247 u_int inst, inst_b, inst_x, inst_s, inst_t; 248 int log2size; 249 u_int *base; 250 u_int offset, index, im5; 251 void *fpreg; 252 u_int r0 = 0; 253 int error; 254 255 /* 256 * Get the instruction that we're emulating, 257 * and break it down. Using HP bit notation, 258 * b is a five-bit field starting at bit 10, 259 * x is a five-bit field starting at bit 15, 260 * s is a two-bit field starting at bit 17, 261 * and t is a five-bit field starting at bit 31. 262 */ 263 inst = frame->tf_iir; 264 __asm volatile( 265 " extru %4, 10, 5, %1 \n" 266 " extru %4, 15, 5, %2 \n" 267 " extru %4, 17, 2, %3 \n" 268 " extru %4, 31, 5, %4 \n" 269 : "=r" (inst_b), "=r" (inst_x), "=r" (inst_s), "=r" (inst_t) 270 : "r" (inst)); 271 272 /* 273 * The space must be the user's space, else we 274 * segfault. 275 */ 276 if (inst_s != pcb->pcb_space) 277 return EFAULT; 278 279 /* See whether or not this is a doubleword load/store. */ 280 log2size = (inst & OPCODE_DOUBLE) ? 3 : 2; 281 282 /* Get the floating point register. */ 283 fpreg = ((char *)pcb->pcb_fpregs) + (inst_t << log2size); 284 285 /* Get the base register. */ 286 base = FRAME_REG(frame, inst_b, r0); 287 288 /* Dispatch on whether or not this is an indexed load/store. */ 289 if (inst & OPCODE_INDEXED) { 290 291 /* Get the index register value. */ 292 index = *FRAME_REG(frame, inst_x, r0); 293 294 /* Dispatch on the completer. */ 295 switch (inst & OPCODE_CMPLT) { 296 case OPCODE_CMPLT_S: 297 offset = *base + (index << log2size); 298 break; 299 case OPCODE_CMPLT_M: 300 offset = *base; 301 *base = *base + index; 302 break; 303 case OPCODE_CMPLT_SM: 304 offset = *base; 305 *base = *base + (index << log2size); 306 break; 307 default: 308 offset = *base + index; 309 break; 310 } 311 } else { 312 313 /* Do a low_sign_ext(x, 5). */ 314 im5 = inst_x >> 1; 315 if (inst_x & 1) 316 im5 |= 0xfffffff0; 317 318 /* Dispatch on the completer. */ 319 switch (inst & OPCODE_CMPLT) { 320 case OPCODE_CMPLT_MB: 321 offset = *base + im5; 322 *base = *base + im5; 323 break; 324 case OPCODE_CMPLT_MA: 325 offset = *base; 326 *base = *base + im5; 327 break; 328 default: 329 offset = *base + im5; 330 break; 331 } 332 } 333 334 /* 335 * The offset we calculated must be the same as the 336 * offset in the IOR. 337 */ 338 KASSERT(offset == frame->tf_ior); 339 340 /* Perform the load or store. */ 341 error = (inst & OPCODE_STORE) ? 342 copyout(fpreg, (void *) offset, 1 << log2size) : 343 copyin((const void *) offset, fpreg, 1 << log2size); 344 return error; 345 } 346 347 /* 348 * This is called to emulate an instruction. 349 */ 350 void 351 hppa_fpu_emulate(struct trapframe *frame, struct lwp *l, u_int inst) 352 { 353 struct pcb *pcb = lwp_getpcb(l); 354 u_int opcode, class, sub; 355 u_int *fpregs; 356 int exception; 357 ksiginfo_t ksi; 358 359 /* 360 * If the process' state is in any hardware FPU, 361 * flush it out - we need to operate on it. 362 */ 363 hppa_fpu_flush(l); 364 365 /* 366 * Get the instruction that we're emulating, 367 * and break it down. Using HP bit notation, 368 * the class is a two-bit field starting at 369 * bit 22, the opcode is a 6-bit field starting 370 * at bit 5, and sub for a class 1 instruction 371 * is a two bit field starting at bit 16, else 372 * it is a three bit field starting at bit 18. 373 */ 374 #if 0 375 __asm volatile( 376 " extru %3, 22, 2, %1 \n" 377 " extru %3, 5, 6, %0 \n" 378 " extru %3, 18, 3, %2 \n" 379 " comib,<> 1, %1, 0 \n" 380 " extru %3, 16, 2, %2 \n" 381 : "=r" (opcode), "=r" (class), "=r" (sub) 382 : "r" (inst)); 383 #else 384 opcode = (inst >> (31 - 5)) & 0x3f; 385 class = (inst >> (31 - 22)) & 0x3; 386 if (class == 1) { 387 sub = (inst >> (31 - 16)) & 3; 388 } else { 389 sub = (inst >> (31 - 18)) & 7; 390 } 391 #endif 392 393 /* Get this LWP's FPU registers. */ 394 fpregs = (u_int *)pcb->pcb_fpregs; 395 396 /* Dispatch on the opcode. */ 397 switch (opcode) { 398 case 0x09: 399 case 0x0b: 400 if (hppa_fpu_ls(frame, l) != 0) { 401 KSI_INIT_TRAP(&ksi); 402 ksi.ksi_signo = SIGSEGV; 403 ksi.ksi_code = SEGV_MAPERR; 404 ksi.ksi_trap = T_DTLBMISS; 405 ksi.ksi_addr = (void *)frame->tf_iioq_head; 406 trapsignal(l, &ksi); 407 } 408 return; 409 case 0x0c: 410 exception = decode_0c(inst, class, sub, fpregs); 411 break; 412 case 0x0e: 413 exception = decode_0e(inst, class, sub, fpregs); 414 break; 415 case 0x06: 416 exception = decode_06(inst, fpregs); 417 break; 418 case 0x26: 419 exception = decode_26(inst, fpregs); 420 break; 421 default: 422 exception = UNIMPLEMENTEDEXCEPTION; 423 break; 424 } 425 426 if (exception) { 427 KSI_INIT_TRAP(&ksi); 428 if (exception & UNIMPLEMENTEDEXCEPTION) { 429 ksi.ksi_signo = SIGILL; 430 ksi.ksi_code = ILL_COPROC; 431 } else { 432 ksi.ksi_signo = SIGFPE; 433 if (exception & INVALIDEXCEPTION) { 434 ksi.ksi_code = FPE_FLTINV; 435 } else if (exception & DIVISIONBYZEROEXCEPTION) { 436 ksi.ksi_code = FPE_FLTDIV; 437 } else if (exception & OVERFLOWEXCEPTION) { 438 ksi.ksi_code = FPE_FLTOVF; 439 } else if (exception & UNDERFLOWEXCEPTION) { 440 ksi.ksi_code = FPE_FLTUND; 441 } else if (exception & INEXACTEXCEPTION) { 442 ksi.ksi_code = FPE_FLTRES; 443 } 444 } 445 ksi.ksi_trap = T_EMULATION; 446 ksi.ksi_addr = (void *)frame->tf_iioq_head; 447 trapsignal(l, &ksi); 448 } 449 } 450 451 #endif /* FPEMUL */ 452
Indexes created Tue Sep 30 07:10:03 GMT 2025