fpu.c revision 1.5
1 /* $NetBSD: fpu.c,v 1.5 2004/03/26 14:11:01 drochner Exp $ */ 2 3 /* 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matthew Fredette. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * FPU handling for NetBSD/hppa. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: fpu.c,v 1.5 2004/03/26 14:11:01 drochner Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/signalvar.h> 50 #include <sys/user.h> 51 52 #include <machine/cpu.h> 53 #include <machine/cpufunc.h> 54 #include <machine/frame.h> 55 #include <machine/reg.h> 56 57 #include <hppa/hppa/machdep.h> 58 59 #include "../spmath/float.h" 60 #include "../spmath/fpudispatch.h" 61 62 /* Some macros representing opcodes. */ 63 #define OPCODE_NOP 0x08000240 64 #define OPCODE_COPR_0_0 0x30000000 65 66 /* Some macros representing fields in load/store opcodes. */ 67 #define OPCODE_CMPLT_S 0x00002000 68 #define OPCODE_CMPLT_M 0x00000020 69 #define OPCODE_CMPLT_SM (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 70 #define OPCODE_CMPLT_MB OPCODE_CMPLT_M 71 #define OPCODE_CMPLT_MA (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 72 #define OPCODE_CMPLT (OPCODE_CMPLT_S | OPCODE_CMPLT_M) 73 #define OPCODE_DOUBLE 0x08000000 74 #define OPCODE_STORE 0x00000200 75 #define OPCODE_INDEXED 0x00001000 76 77 /* This is nonzero iff we're using a hardware FPU. */ 78 int fpu_present; 79 80 /* If we have any FPU, this is its version. */ 81 u_int fpu_version; 82 83 /* The number of times we have had to switch the FPU context. */ 84 u_int fpu_csw; 85 86 /* The U-space physical address of the proc in the FPU, or zero. */ 87 paddr_t fpu_cur_uspace; 88 89 /* In locore.S, this swaps states in and out of the FPU. */ 90 void hppa_fpu_swap(struct user *, struct user *); 91 92 /* XXX see trap.c */ 93 void hppa_trapsignal_hack(struct lwp *, int, u_long); 94 95 #ifdef FPEMUL 96 /* 97 * Given a trapframe and a general register number, the 98 * FRAME_REG macro returns a pointer to that general 99 * register. The _frame_reg_positions array is a lookup 100 * table, since the general registers aren't in order 101 * in a trapframe. 102 * 103 * NB: this more or less assumes that all members of 104 * struct trapframe are u_ints. 105 */ 106 #define FRAME_REG(f, reg, r0) \ 107 ((reg) == 0 ? (&r0) : ((&(f)->tf_t1) + _frame_reg_positions[reg])) 108 #define _FRAME_POSITION(f) \ 109 ((&((struct trapframe *) 0)->f) - (&((struct trapframe *) 0)->tf_t1)) 110 const int _frame_reg_positions[32] = { 111 -1, /* r0 */ 112 _FRAME_POSITION(tf_r1), 113 _FRAME_POSITION(tf_rp), /* r2 */ 114 _FRAME_POSITION(tf_r3), 115 _FRAME_POSITION(tf_r4), 116 _FRAME_POSITION(tf_r5), 117 _FRAME_POSITION(tf_r6), 118 _FRAME_POSITION(tf_r7), 119 _FRAME_POSITION(tf_r8), 120 _FRAME_POSITION(tf_r9), 121 _FRAME_POSITION(tf_r10), 122 _FRAME_POSITION(tf_r11), 123 _FRAME_POSITION(tf_r12), 124 _FRAME_POSITION(tf_r13), 125 _FRAME_POSITION(tf_r14), 126 _FRAME_POSITION(tf_r15), 127 _FRAME_POSITION(tf_r16), 128 _FRAME_POSITION(tf_r17), 129 _FRAME_POSITION(tf_r18), 130 _FRAME_POSITION(tf_t4), /* r19 */ 131 _FRAME_POSITION(tf_t3), /* r20 */ 132 _FRAME_POSITION(tf_t2), /* r21 */ 133 _FRAME_POSITION(tf_t1), /* r22 */ 134 _FRAME_POSITION(tf_arg3), /* r23 */ 135 _FRAME_POSITION(tf_arg2), /* r24 */ 136 _FRAME_POSITION(tf_arg1), /* r25 */ 137 _FRAME_POSITION(tf_arg0), /* r26 */ 138 _FRAME_POSITION(tf_dp), /* r27 */ 139 _FRAME_POSITION(tf_ret0), /* r28 */ 140 _FRAME_POSITION(tf_ret1), /* r29 */ 141 _FRAME_POSITION(tf_sp), /* r30 */ 142 _FRAME_POSITION(tf_r31), 143 }; 144 #endif /* FPEMUL */ 145 146 /* 147 * Bootstraps the FPU. 148 */ 149 void 150 hppa_fpu_bootstrap(u_int ccr_enable) 151 { 152 u_int32_t junk[2]; 153 u_int32_t version[2]; 154 extern u_int hppa_fpu_nop0; 155 extern u_int hppa_fpu_nop1; 156 157 /* See if we have a present and functioning hardware FPU. */ 158 fpu_present = (ccr_enable & HPPA_FPUS) == HPPA_FPUS; 159 160 /* Initialize the FPU and get its version. */ 161 if (fpu_present) { 162 163 /* 164 * To somewhat optimize the emulation 165 * assist trap handling and context 166 * switching (to save them from having 167 * to always load and check fpu_present), 168 * there are two instructions in locore.S 169 * that are replaced with nops when 170 * there is a hardware FPU. 171 */ 172 hppa_fpu_nop0 = OPCODE_NOP; 173 hppa_fpu_nop1 = OPCODE_NOP; 174 fcacheall(); 175 176 /* 177 * We track what process has the FPU, 178 * and how many times we have to swap 179 * in and out. 180 */ 181 182 /* 183 * The PA-RISC 1.1 Architecture manual is 184 * pretty clear that the copr,0,0 must be 185 * wrapped in double word stores of fr0, 186 * otherwise its operation is undefined. 187 */ 188 __asm __volatile( 189 " ldo %0, %%r22 \n" 190 " fstds %%fr0, 0(%%r22) \n" 191 " ldo %1, %%r22 \n" 192 " copr,0,0 \n" 193 " fstds %%fr0, 0(%%r22) \n" 194 : "=m" (junk), "=m" (version) : : "r22"); 195 196 /* 197 * Now mark that no process has the FPU, 198 * and disable it, so the first time it 199 * gets used the process' state gets 200 * swapped in. 201 */ 202 fpu_csw = 0; 203 fpu_cur_uspace = 0; 204 mtctl(ccr_enable & (CCR_MASK ^ HPPA_FPUS), CR_CCR); 205 } 206 #ifdef FPEMUL 207 else 208 /* 209 * XXX This is a hack - to avoid 210 * having to set up the emulator so 211 * it can work for one instruction for 212 * proc0, we dispatch the copr,0,0 opcode 213 * into the emulator directly. 214 */ 215 decode_0c(OPCODE_COPR_0_0, 0, 0, version); 216 #endif /* FPEMUL */ 217 fpu_version = version[0]; 218 } 219 220 /* 221 * If the given LWP has its state in the FPU, 222 * flush that state out into the LWP's PCB. 223 */ 224 void 225 hppa_fpu_flush(struct lwp *l) 226 { 227 struct trapframe *tf = l->l_md.md_regs; 228 229 /* 230 * If we have a hardware FPU, and this process' 231 * state is currently in it, swap it out. 232 */ 233 234 if (fpu_present && 235 fpu_cur_uspace != 0 && 236 fpu_cur_uspace == tf->tf_cr30) 237 hppa_fpu_swap(l->l_addr, NULL); 238 } 239 240 #ifdef FPEMUL 241 242 /* 243 * This emulates a coprocessor load/store instruction. 244 */ 245 static int hppa_fpu_ls(struct trapframe *, struct lwp *); 246 static int 247 hppa_fpu_ls(struct trapframe *frame, struct lwp *l) 248 { 249 u_int inst, inst_b, inst_x, inst_s, inst_t; 250 int log2size; 251 u_int *base; 252 u_int offset, index, im5; 253 void *fpreg; 254 u_int r0 = 0; 255 256 /* 257 * Get the instruction that we're emulating, 258 * and break it down. Using HP bit notation, 259 * b is a five-bit field starting at bit 10, 260 * x is a five-bit field starting at bit 15, 261 * s is a two-bit field starting at bit 17, 262 * and t is a two-bit field starting at bit 31. 263 */ 264 inst = frame->tf_iir; 265 __asm __volatile( 266 " extru %4, 10, 5, %1 \n" 267 " extru %4, 15, 5, %2 \n" 268 " extru %4, 17, 2, %3 \n" 269 " extru %4, 31, 5, %4 \n" 270 : "=r" (inst_b), "=r" (inst_x), "=r" (inst_s), "=r" (inst_t) 271 : "r" (inst)); 272 273 /* 274 * The space must be the user's space, else we 275 * segfault. 276 */ 277 if (inst_s != l->l_addr->u_pcb.pcb_space) 278 return (EFAULT); 279 280 /* See whether or not this is a doubleword load/store. */ 281 log2size = (inst & OPCODE_DOUBLE) ? 3 : 2; 282 283 /* Get the floating point register. */ 284 fpreg = ((caddr_t)l->l_addr->u_pcb.pcb_fpregs) + (inst_t << log2size); 285 286 /* Get the base register. */ 287 base = FRAME_REG(frame, inst_b, r0); 288 289 /* Dispatch on whether or not this is an indexed load/store. */ 290 if (inst & OPCODE_INDEXED) { 291 292 /* Get the index register value. */ 293 index = *FRAME_REG(frame, inst_x, r0); 294 295 /* Dispatch on the completer. */ 296 switch (inst & OPCODE_CMPLT) { 297 case OPCODE_CMPLT_S: 298 offset = *base + (index << log2size); 299 break; 300 case OPCODE_CMPLT_M: 301 offset = *base; 302 *base = *base + index; 303 break; 304 case OPCODE_CMPLT_SM: 305 offset = *base; 306 *base = *base + (index << log2size); 307 break; 308 default: 309 offset = *base + index; 310 break; 311 } 312 } else { 313 314 /* Do a low_sign_ext(x, 5). */ 315 im5 = inst_x >> 1; 316 if (inst_x & 1) 317 im5 |= 0xfffffff0; 318 319 /* Dispatch on the completer. */ 320 switch (inst & OPCODE_CMPLT) { 321 case OPCODE_CMPLT_MB: 322 offset = *base + im5; 323 *base = *base + im5; 324 break; 325 case OPCODE_CMPLT_MA: 326 offset = *base; 327 *base = *base + im5; 328 break; 329 default: 330 offset = *base + im5; 331 break; 332 } 333 } 334 335 /* 336 * The offset we calculated must be the same as the 337 * offset in the IOR. 338 */ 339 KASSERT(offset == frame->tf_ior); 340 341 /* Perform the load or store. */ 342 return (inst & OPCODE_STORE) ? 343 copyout(fpreg, (void *) offset, 1 << log2size) : 344 copyin((const void *) offset, fpreg, 1 << log2size); 345 } 346 347 /* 348 * This is called to emulate an instruction. 349 */ 350 void 351 hppa_fpu_emulate(struct trapframe *frame, struct lwp *l) 352 { 353 u_int inst, opcode, class, sub; 354 u_int *fpregs; 355 int exception; 356 357 /* 358 * If the process' state is in any hardware FPU, 359 * flush it out - we need to operate on it. 360 */ 361 hppa_fpu_flush(l); 362 363 /* 364 * Get the instruction that we're emulating, 365 * and break it down. Using HP bit notation, 366 * the class is a two-bit field starting at 367 * bit 22, the opcode is a 6-bit field starting 368 * at bit 5, and sub for a class 1 instruction 369 * is a two bit field starting at bit 16, else 370 * it is a three bit field starting at bit 18. 371 */ 372 inst = frame->tf_iir; 373 __asm __volatile( 374 " extru %3, 22, 2, %1 \n" 375 " extru %3, 5, 6, %0 \n" 376 " extru %3, 18, 3, %2 \n" 377 " comib,<> 1, %1, 0 \n" 378 " extru %3, 16, 2, %2 \n" 379 : "=r" (opcode), "=r" (class), "=r" (sub) 380 : "r" (inst)); 381 382 /* Get this LWP's FPU registers. */ 383 fpregs = (u_int *) l->l_addr->u_pcb.pcb_fpregs; 384 385 /* Dispatch on the opcode. */ 386 switch (opcode) { 387 case 0x09: 388 case 0x0b: 389 if (hppa_fpu_ls(frame, l) != 0) 390 hppa_trapsignal_hack(l, SIGSEGV, frame->tf_iioq_head); 391 return; 392 case 0x0c: 393 exception = decode_0c(inst, class, sub, fpregs); 394 break; 395 case 0x0e: 396 exception = decode_0e(inst, class, sub, fpregs); 397 break; 398 case 0x06: 399 exception = decode_06(inst, fpregs); 400 break; 401 case 0x26: 402 exception = decode_26(inst, fpregs); 403 break; 404 default: 405 exception = UNIMPLEMENTEDEXCEPTION; 406 break; 407 } 408 409 if (exception) 410 hppa_trapsignal_hack(l, (exception & UNIMPLEMENTEDEXCEPTION) ? 411 SIGILL : SIGFPE, frame->tf_iioq_head); 412 } 413 414 #endif /* FPEMUL */ 415
Indexes created Mon Sep 29 21:09:56 GMT 2025