asm.h revision 1.1
1 /* $NetBSD: asm.h,v 1.1 2002/06/05 01:04:21 fredette Exp $ */ 2 3 /* $OpenBSD: asm.h,v 1.12 2001/03/29 02:15:57 mickey Exp $ */ 4 5 /* 6 * Copyright (c) 1990,1991,1994 The University of Utah and 7 * the Computer Systems Laboratory (CSL). All rights reserved. 8 * 9 * Permission to use, copy, modify and distribute this software is hereby 10 * granted provided that (1) source code retains these copyright, permission, 11 * and disclaimer notices, and (2) redistributions including binaries 12 * reproduce the notices in supporting documentation, and (3) all advertising 13 * materials mentioning features or use of this software display the following 14 * acknowledgement: ``This product includes software developed by the 15 * Computer Systems Laboratory at the University of Utah.'' 16 * 17 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 18 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 19 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 20 * 21 * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 22 * improvements that they make and grant CSL redistribution rights. 23 * 24 * Utah $Hdr: asm.h 1.8 94/12/14$ 25 */ 26 27 #ifndef _HPPA_ASM_H_ 28 #define _HPPA_ASM_H_ 29 30 /* 31 * hppa assembler definitions 32 */ 33 34 /* 35 * Hardware General Registers 36 */ 37 r0 .reg %r0 38 r1 .reg %r1 39 r2 .reg %r2 40 r3 .reg %r3 41 r4 .reg %r4 42 r5 .reg %r5 43 r6 .reg %r6 44 r7 .reg %r7 45 r8 .reg %r8 46 r9 .reg %r9 47 r10 .reg %r10 48 r11 .reg %r11 49 r12 .reg %r12 50 r13 .reg %r13 51 r14 .reg %r14 52 r15 .reg %r15 53 r16 .reg %r16 54 r17 .reg %r17 55 r18 .reg %r18 56 r19 .reg %r19 57 r20 .reg %r20 58 r21 .reg %r21 59 r22 .reg %r22 60 r23 .reg %r23 61 r24 .reg %r24 62 r25 .reg %r25 63 r26 .reg %r26 64 r27 .reg %r27 65 r28 .reg %r28 66 r29 .reg %r29 67 r30 .reg %r30 68 r31 .reg %r31 69 70 /* 71 * Hardware Space Registers 72 */ 73 sr0 .reg %sr0 74 sr1 .reg %sr1 75 sr2 .reg %sr2 76 sr3 .reg %sr3 77 sr4 .reg %sr4 78 sr5 .reg %sr5 79 sr6 .reg %sr6 80 sr7 .reg %sr7 81 82 /* 83 * Hardware Floating Point Registers 84 */ 85 fr0 .reg %fr0 86 fr1 .reg %fr1 87 fr2 .reg %fr2 88 fr3 .reg %fr3 89 fr4 .reg %fr4 90 fr5 .reg %fr5 91 fr6 .reg %fr6 92 fr7 .reg %fr7 93 fr8 .reg %fr8 94 fr9 .reg %fr9 95 fr10 .reg %fr10 96 fr11 .reg %fr11 97 fr12 .reg %fr12 98 fr13 .reg %fr13 99 fr14 .reg %fr14 100 fr15 .reg %fr15 101 fr16 .reg %fr16 102 fr17 .reg %fr17 103 fr18 .reg %fr18 104 fr19 .reg %fr19 105 fr20 .reg %fr20 106 fr21 .reg %fr21 107 fr22 .reg %fr22 108 fr23 .reg %fr23 109 fr24 .reg %fr24 110 fr25 .reg %fr25 111 fr26 .reg %fr26 112 fr27 .reg %fr27 113 fr28 .reg %fr28 114 fr29 .reg %fr29 115 fr30 .reg %fr30 116 fr31 .reg %fr31 117 118 /* 119 * Hardware Control Registers 120 */ 121 cr0 .reg %cr0 122 cr8 .reg %cr8 123 cr9 .reg %cr9 124 cr10 .reg %cr10 125 cr11 .reg %cr11 126 cr12 .reg %cr12 127 cr13 .reg %cr13 128 cr14 .reg %cr14 129 cr15 .reg %cr15 130 cr16 .reg %cr16 131 cr17 .reg %cr17 132 cr18 .reg %cr18 133 cr19 .reg %cr19 134 cr20 .reg %cr20 135 cr21 .reg %cr21 136 cr22 .reg %cr22 137 cr23 .reg %cr23 138 cr24 .reg %cr24 139 cr25 .reg %cr25 140 cr26 .reg %cr26 141 cr27 .reg %cr27 142 cr28 .reg %cr28 143 cr29 .reg %cr29 144 cr30 .reg %cr30 145 cr31 .reg %cr31 146 147 rctr .reg %cr0 148 pidr1 .reg %cr8 149 pidr2 .reg %cr9 150 ccr .reg %cr10 151 sar .reg %cr11 152 pidr3 .reg %cr12 153 pidr4 .reg %cr13 154 iva .reg %cr14 155 eiem .reg %cr15 156 itmr .reg %cr16 157 pcsq .reg %cr17 158 pcoq .reg %cr18 159 iir .reg %cr19 160 isr .reg %cr20 161 ior .reg %cr21 162 ipsw .reg %cr22 163 eirr .reg %cr23 164 hptmask .reg %cr24 165 tr0 .reg %cr24 166 vtop .reg %cr25 167 tr1 .reg %cr25 168 tr2 .reg %cr26 169 tr3 .reg %cr27 170 tr4 .reg %cr28 171 tr5 .reg %cr29 172 tr6 .reg %cr30 173 tr7 .reg %cr31 174 175 /* 176 * Calling Convention 177 */ 178 rp .reg %r2 179 arg3 .reg %r23 180 arg2 .reg %r24 181 arg1 .reg %r25 182 arg0 .reg %r26 183 dp .reg %r27 184 ret0 .reg %r28 185 ret1 .reg %r29 186 sl .reg %r29 187 sp .reg %r30 188 189 /* 190 * Temporary registers 191 */ 192 t1 .reg %r22 193 t2 .reg %r21 194 t3 .reg %r20 195 t4 .reg %r19 196 197 /* 198 * Temporary space registers 199 */ 200 ts1 .reg %sr2 201 202 /* 203 * Space Registers - SW Conventions 204 */ 205 sret .reg %sr1 ; return value 206 sarg .reg %sr1 ; argument 207 208 /* 209 * Floating Point Registers - SW Conventions 210 */ 211 farg0 .reg %fr5 212 farg1 .reg %fr6 213 farg2 .reg %fr7 214 farg3 .reg %fr8 215 fret .reg %fr4 216 217 /* 218 * Temporary floating point registers 219 */ 220 tf1 .reg %fr11 221 tf2 .reg %fr10 222 tf3 .reg %fr9 223 tf4 .reg %fr8 224 225 #ifdef __STDC__ 226 #define __CONCAT(a,b) a ## b 227 #else 228 #define __CONCAT(a,b) a/**/b 229 #endif 230 231 #ifdef PROF 232 #define _PROF_PROLOGUE !\ 233 stw rp, HPPA_FRAME_CRP(sr0,sp) !\ 234 ldil L%_mcount,r1 !\ 235 ble R%_mcount(sr0,r1) !\ 236 ldo HPPA_FRAME_SIZE(sp),sp !\ 237 ldw HPPA_FRAME_CRP(sr0,sp),rp 238 #else 239 #define _PROF_PROLOGUE 240 #endif 241 242 #define LEAF_ENTRY(x) ! .text ! .align 4 !\ 243 .export x, entry ! .label x ! .proc !\ 244 .callinfo frame=0,no_calls,save_rp !\ 245 .entry ! _PROF_PROLOGUE 246 247 #define ENTRY(x,n) ! .text ! .align 4 !\ 248 .export x, entry ! .label x ! .proc !\ 249 .callinfo frame=n,calls, save_rp, save_sp !\ 250 .entry ! _PROF_PROLOGUE 251 252 #define ALTENTRY(x) ! .export x, entry ! .label x 253 #define EXIT(x) ! .exit ! .procend 254 255 #define RCSID(x) .text ! \ 256 .asciz x ! \ 257 .align 4 258 259 #define WEAK_ALIAS(alias,sym) \ 260 .weak alias ! \ 261 alias = sym 262 263 /* XXX unimplemented */ 264 #define WARN_REFERENCES(sym, msg) 265 266 #endif /* _HPPA_ASM_H_ */ 267
Indexes created Tue Sep 23 22:09:46 GMT 2025