cpu.h revision 1.12
1 /* $NetBSD: cpu.h,v 1.12 2021/11/02 11:26:04 ryo Exp $ */ 2 3 /* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */ 4 5 /* 6 * Copyright (c) 2000-2004 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 /* 31 * Copyright (c) 1988-1994, The University of Utah and 32 * the Computer Systems Laboratory at the University of Utah (CSL). 33 * All rights reserved. 34 * 35 * Permission to use, copy, modify and distribute this software is hereby 36 * granted provided that (1) source code retains these copyright, permission, 37 * and disclaimer notices, and (2) redistributions including binaries 38 * reproduce the notices in supporting documentation, and (3) all advertising 39 * materials mentioning features or use of this software display the following 40 * acknowledgement: ``This product includes software developed by the 41 * Computer Systems Laboratory at the University of Utah.'' 42 * 43 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 44 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 45 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 48 * improvements that they make and grant CSL redistribution rights. 49 * 50 * Utah $Hdr: cpu.h 1.19 94/12/16$ 51 */ 52 53 #ifndef _MACHINE_CPU_H_ 54 #define _MACHINE_CPU_H_ 55 56 #ifdef _KERNEL_OPT 57 #include "opt_cputype.h" 58 #include "opt_gprof.h" 59 #include "opt_multiprocessor.h" 60 #endif 61 62 #include <machine/trap.h> 63 #include <machine/frame.h> 64 #include <machine/reg.h> 65 #include <machine/intrdefs.h> 66 67 #ifndef __ASSEMBLER__ 68 #include <machine/intr.h> 69 #endif 70 71 #ifndef _LOCORE 72 73 /* types */ 74 enum hppa_cpu_type { 75 hpc_unknown, 76 hpcx, /* PA7000 (x) PA 1.0 */ 77 hpcxs, /* PA7000 (s) PA 1.1a */ 78 hpcxt, /* PA7100 (t) PA 1.1b */ 79 hpcxl, /* PA7100LC (l) PA 1.1c */ 80 hpcxtp, /* PA7200 (t') PA 1.1d */ 81 hpcxl2, /* PA7300LC (l2) PA 1.1e */ 82 hpcxu, /* PA8000 (u) PA 2.0 */ 83 hpcxup, /* PA8200 (u+) PA 2.0 */ 84 hpcxw, /* PA8500 (w) PA 2.0 */ 85 hpcxwp, /* PA8600 (w+) PA 2.0 */ 86 hpcxw2, /* PA8700 (piranha) PA 2.0 */ 87 mako /* PA8800 (mako) PA 2.0 */ 88 }; 89 90 #ifdef _KERNEL 91 /* 92 * A CPU description. 93 */ 94 struct hppa_cpu_info { 95 /* The official name of the chip. */ 96 const char *hci_chip_name; 97 98 /* The nickname for the chip. */ 99 const char *hci_chip_nickname; 100 101 /* The type and PA-RISC specification of the chip. */ 102 const char hci_chip_type[8]; 103 enum hppa_cpu_type hci_cputype; 104 int hci_cpuversion; 105 int hci_features; /* CPU types and features */ 106 #define HPPA_FTRS_TLBU 0x00000001 107 #define HPPA_FTRS_BTLBU 0x00000002 108 #define HPPA_FTRS_HVT 0x00000004 109 #define HPPA_FTRS_W32B 0x00000008 110 111 const char *hci_chip_spec; 112 113 int (*desidhash)(void); 114 const u_int *itlbh, *dtlbh, *itlbnah, *dtlbnah, *tlbdh; 115 int (*dbtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); 116 int (*ibtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); 117 int (*btlbprg)(int); 118 int (*hptinit)(vaddr_t, vsize_t); 119 }; 120 121 extern const struct hppa_cpu_info *hppa_cpu_info; 122 extern int cpu_modelno; 123 extern int cpu_revision; 124 #endif 125 #endif 126 127 /* 128 * COPR/SFUs 129 */ 130 #define HPPA_FPUS 0xc0 131 #define HPPA_PMSFUS 0x20 /* ??? */ 132 133 /* 134 * Exported definitions unique to hppa/PA-RISC cpu support. 135 */ 136 137 /* 138 * COPR/SFUs 139 */ 140 #define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11) 141 #define HPPA_FPU_OP(w) ((w) >> 26) 142 #define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */ 143 #define HPPA_FPU_ILL 0x80 /* software-only */ 144 #define HPPA_FPU_I 0x01 145 #define HPPA_FPU_U 0x02 146 #define HPPA_FPU_O 0x04 147 #define HPPA_FPU_Z 0x08 148 #define HPPA_FPU_V 0x10 149 #define HPPA_FPU_D 0x20 150 #define HPPA_FPU_T 0x40 151 #define HPPA_FPU_XMASK 0x7f 152 #define HPPA_FPU_T_POS 25 153 #define HPPA_FPU_RM 0x00000600 154 #define HPPA_FPU_CQ 0x00fff800 155 #define HPPA_FPU_C 0x04000000 156 #define HPPA_FPU_FLSH 27 157 #define HPPA_FPU_INIT (0) 158 #define HPPA_FPU_FORK(s) ((s) & ~((uint64_t)(HPPA_FPU_XMASK) << 32)) 159 160 /* 161 * definitions of cpu-dependent requirements 162 * referenced in generic code 163 */ 164 #if defined(HP8000_CPU) || defined(HP8200_CPU) || \ 165 defined(HP8500_CPU) || defined(HP8600_CPU) 166 167 /* PA2.0 aliases */ 168 #define HPPA_PGALIAS 0x00400000 169 #define HPPA_PGAMASK 0xffc00000 /* PA bits 0-9 not used in index */ 170 #define HPPA_PGAOFF 0x003fffff 171 172 #else 173 174 /* PA1.x aliases */ 175 #define HPPA_PGALIAS 0x00100000 176 #define HPPA_PGAMASK 0xfff00000 /* PA bits 0-11 not used in index */ 177 #define HPPA_PGAOFF 0x000fffff 178 179 #endif 180 181 #define HPPA_SPAMASK 0xf0f0f000 /* PA bits 0-3,8-11,16-19 not used */ 182 183 #define HPPA_IOSPACE 0xf0000000 184 #define HPPA_IOLEN 0x10000000 185 #define HPPA_PDC_LOW 0xef000000 186 #define HPPA_PDC_HIGH 0xf1000000 187 #define HPPA_IOBCAST 0xfffc0000 188 #define HPPA_LBCAST 0xfffc0000 189 #define HPPA_GBCAST 0xfffe0000 190 #define HPPA_FPA 0xfff80000 191 #define HPPA_FLEX_DATA 0xfff80001 192 #define HPPA_DMA_ENABLE 0x00000001 193 #define HPPA_SPA_ENABLE 0x00000020 194 #define HPPA_NMODSPBUS 64 195 196 #ifdef MULTIPROCESSOR 197 198 #define GET_CURCPU(r) mfctl CR_CURCPU, r 199 #define GET_CURCPU_SPACE(s, r) GET_CURCPU(r) 200 #define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r 201 #define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r 202 203 #define SET_CURLWP(r,t) mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) 204 205 #else /* MULTIPROCESSOR */ 206 207 #define GET_CURCPU(r) mfctl CR_CURLWP, r ! ldw L_CPU(r), r 208 #define GET_CURCPU_SPACE(s, r) mfctl CR_CURLWP, r ! ldw L_CPU(s, r), r 209 #define GET_CURLWP(r) mfctl CR_CURLWP, r 210 #define GET_CURLWP_SPACE(s, r) GET_CURLWP(r) 211 212 #define SET_CURLWP(r,t) mtctl r, CR_CURLWP 213 214 #endif /* MULTIPROCESSOR */ 215 216 #ifndef _LOCORE 217 #ifdef _KERNEL 218 219 /* 220 * External definitions unique to PA-RISC cpu support. 221 * These are the "public" declarations - those needed in 222 * machine-independent source code. The "private" ones 223 * are in machdep.h. 224 * 225 * Note that the name of this file is NOT meant to imply 226 * that it has anything to do with PA-RISC CPU stuff. 227 * The name "cpu" is historical, and used in the common 228 * code to identify machine-dependent functions, etc. 229 */ 230 231 /* clockframe describes the system before we took an interrupt. */ 232 struct clockframe { 233 int cf_flags; 234 int cf_spl; 235 u_int cf_pc; 236 }; 237 #define CLKF_PC(framep) ((framep)->cf_pc) 238 #define CLKF_INTR(framep) ((framep)->cf_flags & TFF_INTR) 239 #define CLKF_USERMODE(framep) ((framep)->cf_flags & T_USER) 240 241 int clock_intr(void *); 242 243 /* 244 * LWP_PC: the program counter for the given lwp. 245 */ 246 #define LWP_PC(l) ((l)->l_md.md_regs->tf_iioq_head) 247 248 #define cpu_signotify(l) (setsoftast(l)) 249 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast(l)) 250 251 #endif /* _KERNEL */ 252 253 #ifndef __ASSEMBLER__ 254 #if defined(_KERNEL) || defined(_KMEMUSER) 255 256 #include <sys/cpu_data.h> 257 #include <sys/evcnt.h> 258 259 /* 260 * Note that the alignment of ci_trap_save is important since we want to keep 261 * it within a single cache line. As a result, it must be kept as the first 262 * entry within the cpu_info struct. 263 */ 264 struct cpu_info { 265 /* Keep this first to simplify the trap handlers */ 266 register_t ci_trapsave[16];/* the "phys" part of frame */ 267 268 struct cpu_data ci_data; /* MI per-cpu data */ 269 270 #ifndef _KMEMUSER 271 hppa_hpa_t ci_hpa; 272 register_t ci_psw; /* Processor Status Word. */ 273 paddr_t ci_fpu_state; /* LWP FPU state address, or zero. */ 274 u_long ci_itmr; 275 276 int ci_cpuid; /* CPU index (see cpus[] array) */ 277 int ci_mtx_count; 278 int ci_mtx_oldspl; 279 int ci_want_resched; 280 281 volatile int ci_cpl; 282 volatile int ci_ipending; /* The pending interrupts. */ 283 u_int ci_intr_depth; /* Nonzero iff running an interrupt. */ 284 u_int ci_ishared; 285 u_int ci_eiem; 286 287 u_int ci_imask[NIPL]; 288 289 struct hppa_interrupt_register ci_ir; 290 struct hppa_interrupt_bit ci_ib[HPPA_INTERRUPT_BITS]; 291 292 struct lwp *ci_onproc; /* current user LWP / kthread */ 293 #if defined(MULTIPROCESSOR) 294 struct lwp *ci_curlwp; /* CPU owner */ 295 paddr_t ci_stack; /* stack for spin up */ 296 volatile int ci_flags; /* CPU status flags */ 297 #define CPUF_PRIMARY 0x0001 /* ... is monarch/primary */ 298 #define CPUF_RUNNING 0x0002 /* ... is running. */ 299 300 volatile u_long ci_ipi; /* IPIs pending */ 301 302 struct cpu_softc *ci_softc; 303 #endif 304 #if defined(GPROF) && defined(MULTIPROCESSOR) 305 struct gmonparam *ci_gmon; /* MI per-cpu GPROF */ 306 #endif 307 #endif /* !_KMEMUSER */ 308 } __aligned(64); 309 310 #endif /* _KERNEL || _KMEMUSER */ 311 #endif /* __ASSEMBLER__ */ 312 313 #if defined(_KERNEL) 314 315 /* 316 * definitions of cpu-dependent requirements 317 * referenced in generic code 318 */ 319 320 void cpu_proc_fork(struct proc *, struct proc *); 321 322 struct lwp *hppa_curlwp(void); 323 struct cpu_info *hppa_curcpu(void); 324 325 #if defined(_MODULE) 326 #define curcpu() hppa_curcpu() 327 #define curlwp hppa_curlwp() 328 #endif 329 330 #if defined(MULTIPROCESSOR) || defined(_MODULE) 331 /* Number of CPUs in the system */ 332 extern int hppa_ncpu; 333 334 #define HPPA_MAXCPUS 4 335 336 #define cpu_number() (curcpu()->ci_cpuid) 337 338 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 339 #define CPU_INFO_ITERATOR int 340 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = &cpus[0]; cii < hppa_ncpu; cii++, ci++ 341 342 void cpu_boot_secondary_processors(void); 343 344 #if !defined(_MODULE) 345 static __inline __always_inline struct cpu_info * 346 _hppa_curcpu(void) 347 { 348 struct cpu_info *ci; 349 350 __asm volatile("mfctl %1, %0" : "=r" (ci): "i" (CR_CURCPU)); 351 352 return ci; 353 } 354 355 #define curcpu() _hppa_curcpu() 356 #endif 357 358 #else /* MULTIPROCESSOR */ 359 360 #define HPPA_MAXCPUS 1 361 #define curcpu() (&cpus[0]) 362 #define cpu_number() 0 363 364 static __inline struct lwp * 365 _hppa_curlwp(void) 366 { 367 struct lwp *l; 368 369 __asm volatile("mfctl %1, %0" : "=r" (l): "i" (CR_CURLWP)); 370 371 return l; 372 } 373 374 #define curlwp _hppa_curlwp() 375 376 #endif /* MULTIPROCESSOR */ 377 378 extern struct cpu_info cpus[HPPA_MAXCPUS]; 379 380 #define DELAY(x) delay(x) 381 382 static __inline paddr_t 383 kvtop(const void *va) 384 { 385 paddr_t pa; 386 387 __asm volatile ("lpa %%r0(%1), %0" : "=r" (pa) : "r" (va)); 388 return pa; 389 } 390 391 extern int (*cpu_desidhash)(void); 392 393 static __inline bool 394 hppa_cpu_ispa20_p(void) 395 { 396 397 return (hppa_cpu_info->hci_features & HPPA_FTRS_W32B) != 0; 398 } 399 400 static __inline bool 401 hppa_cpu_hastlbu_p(void) 402 { 403 404 return (hppa_cpu_info->hci_features & HPPA_FTRS_TLBU) != 0; 405 } 406 407 void delay(u_int); 408 void hppa_init(paddr_t, void *); 409 void trap(int, struct trapframe *); 410 void hppa_ras(struct lwp *); 411 int spcopy(pa_space_t, const void *, pa_space_t, void *, size_t); 412 int spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t, 413 size_t *); 414 int copy_on_fault(void); 415 void lwp_trampoline(void); 416 int cpu_dumpsize(void); 417 int cpu_dump(void); 418 419 #ifdef MULTIPROCESSOR 420 void cpu_boot_secondary_processors(void); 421 void cpu_hw_init(void); 422 void cpu_hatch(void); 423 #endif 424 #endif /* _KERNEL */ 425 426 /* 427 * Boot arguments stuff 428 */ 429 430 #define BOOTARG_LEN (PAGE_SIZE) 431 #define BOOTARG_OFF (0x10000) 432 433 /* 434 * CTL_MACHDEP definitions. 435 */ 436 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 437 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 438 #define CPU_LCD_BLINK 3 /* int: twiddle heartbeat LED/LCD */ 439 440 #ifdef _KERNEL 441 #include <sys/queue.h> 442 443 struct blink_lcd { 444 void (*bl_func)(void *, int); 445 void *bl_arg; 446 SLIST_ENTRY(blink_lcd) bl_next; 447 }; 448 449 extern void blink_lcd_register(struct blink_lcd *); 450 #endif /* _KERNEL */ 451 #endif /* !_LOCORE */ 452 453 #endif /* _MACHINE_CPU_H_ */ 454
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