cpu.h revision 1.5.4.1
1 /* $NetBSD: cpu.h,v 1.5.4.1 2023/07/31 13:44:16 martin Exp $ */ 2 3 /* $OpenBSD: cpu.h,v 1.55 2008/07/23 17:39:35 kettenis Exp $ */ 4 5 /* 6 * Copyright (c) 2000-2004 Michael Shalayeff 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 27 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 /* 31 * Copyright (c) 1988-1994, The University of Utah and 32 * the Computer Systems Laboratory at the University of Utah (CSL). 33 * All rights reserved. 34 * 35 * Permission to use, copy, modify and distribute this software is hereby 36 * granted provided that (1) source code retains these copyright, permission, 37 * and disclaimer notices, and (2) redistributions including binaries 38 * reproduce the notices in supporting documentation, and (3) all advertising 39 * materials mentioning features or use of this software display the following 40 * acknowledgement: ``This product includes software developed by the 41 * Computer Systems Laboratory at the University of Utah.'' 42 * 43 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS 44 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF 45 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 46 * 47 * CSL requests users of this software to return to csl-dist (at) cs.utah.edu any 48 * improvements that they make and grant CSL redistribution rights. 49 * 50 * Utah $Hdr: cpu.h 1.19 94/12/16$ 51 */ 52 53 #ifndef _MACHINE_CPU_H_ 54 #define _MACHINE_CPU_H_ 55 56 #ifdef _KERNEL_OPT 57 #include "opt_cputype.h" 58 #include "opt_multiprocessor.h" 59 #endif 60 61 #include <machine/trap.h> 62 #include <machine/frame.h> 63 #include <machine/reg.h> 64 #include <machine/intrdefs.h> 65 66 #ifndef __ASSEMBLER__ 67 #include <machine/intr.h> 68 #endif 69 70 #ifndef _LOCORE 71 72 /* types */ 73 enum hppa_cpu_type { 74 hpc_unknown, 75 hpcx, /* PA7000 (x) PA 1.0 */ 76 hpcxs, /* PA7000 (s) PA 1.1a */ 77 hpcxt, /* PA7100 (t) PA 1.1b */ 78 hpcxl, /* PA7100LC (l) PA 1.1c */ 79 hpcxtp, /* PA7200 (t') PA 1.1d */ 80 hpcxl2, /* PA7300LC (l2) PA 1.1e */ 81 hpcxu, /* PA8000 (u) PA 2.0 */ 82 hpcxup, /* PA8200 (u+) PA 2.0 */ 83 hpcxw, /* PA8500 (w) PA 2.0 */ 84 hpcxwp, /* PA8600 (w+) PA 2.0 */ 85 hpcxw2, /* PA8700 (piranha) PA 2.0 */ 86 mako /* PA8800 (mako) PA 2.0 */ 87 }; 88 89 #ifdef _KERNEL 90 /* 91 * A CPU description. 92 */ 93 struct hppa_cpu_info { 94 /* The official name of the chip. */ 95 const char *hci_chip_name; 96 97 /* The nickname for the chip. */ 98 const char *hci_chip_nickname; 99 100 /* The type and PA-RISC specification of the chip. */ 101 const char hci_chip_type[8]; 102 enum hppa_cpu_type hci_cputype; 103 int hci_cpuversion; 104 int hci_features; /* CPU types and features */ 105 #define HPPA_FTRS_TLBU 0x00000001 106 #define HPPA_FTRS_BTLBU 0x00000002 107 #define HPPA_FTRS_HVT 0x00000004 108 #define HPPA_FTRS_W32B 0x00000008 109 110 const char *hci_chip_spec; 111 112 int (*desidhash)(void); 113 const u_int *itlbh, *dtlbh, *itlbnah, *dtlbnah, *tlbdh; 114 int (*dbtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); 115 int (*ibtlbins)(int, pa_space_t, vaddr_t, paddr_t, vsize_t, u_int); 116 int (*btlbprg)(int); 117 int (*hptinit)(vaddr_t, vsize_t); 118 }; 119 120 extern const struct hppa_cpu_info *hppa_cpu_info; 121 extern int cpu_modelno; 122 extern int cpu_revision; 123 #endif 124 #endif 125 126 /* 127 * COPR/SFUs 128 */ 129 #define HPPA_FPUS 0xc0 130 #define HPPA_PMSFUS 0x20 /* ??? */ 131 132 /* 133 * Exported definitions unique to hppa/PA-RISC cpu support. 134 */ 135 136 /* 137 * COPR/SFUs 138 */ 139 #define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11) 140 #define HPPA_FPU_OP(w) ((w) >> 26) 141 #define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */ 142 #define HPPA_FPU_ILL 0x80 /* software-only */ 143 #define HPPA_FPU_I 0x01 144 #define HPPA_FPU_U 0x02 145 #define HPPA_FPU_O 0x04 146 #define HPPA_FPU_Z 0x08 147 #define HPPA_FPU_V 0x10 148 #define HPPA_FPU_D 0x20 149 #define HPPA_FPU_T 0x40 150 #define HPPA_FPU_XMASK 0x7f 151 #define HPPA_FPU_T_POS 25 152 #define HPPA_FPU_RM 0x00000600 153 #define HPPA_FPU_CQ 0x00fff800 154 #define HPPA_FPU_C 0x04000000 155 #define HPPA_FPU_FLSH 27 156 #define HPPA_FPU_INIT (0) 157 #define HPPA_FPU_FORK(s) ((s) & ~((uint64_t)(HPPA_FPU_XMASK) << 32)) 158 159 /* 160 * definitions of cpu-dependent requirements 161 * referenced in generic code 162 */ 163 #if defined(HP8000_CPU) || defined(HP8200_CPU) || \ 164 defined(HP8500_CPU) || defined(HP8600_CPU) 165 166 /* PA2.0 aliases */ 167 #define HPPA_PGALIAS 0x00400000 168 #define HPPA_PGAMASK 0xffc00000 /* PA bits 0-9 not used in index */ 169 #define HPPA_PGAOFF 0x003fffff 170 171 #else 172 173 /* PA1.x aliases */ 174 #define HPPA_PGALIAS 0x00100000 175 #define HPPA_PGAMASK 0xfff00000 /* PA bits 0-11 not used in index */ 176 #define HPPA_PGAOFF 0x000fffff 177 178 #endif 179 180 #define HPPA_SPAMASK 0xf0f0f000 /* PA bits 0-3,8-11,16-19 not used */ 181 182 #define HPPA_IOSPACE 0xf0000000 183 #define HPPA_IOLEN 0x10000000 184 #define HPPA_PDC_LOW 0xef000000 185 #define HPPA_PDC_HIGH 0xf1000000 186 #define HPPA_IOBCAST 0xfffc0000 187 #define HPPA_LBCAST 0xfffc0000 188 #define HPPA_GBCAST 0xfffe0000 189 #define HPPA_FPA 0xfff80000 190 #define HPPA_FLEX_DATA 0xfff80001 191 #define HPPA_DMA_ENABLE 0x00000001 192 #define HPPA_SPA_ENABLE 0x00000020 193 #define HPPA_NMODSPBUS 64 194 195 #ifdef MULTIPROCESSOR 196 197 #define GET_CURCPU(r) mfctl CR_CURCPU, r 198 #define GET_CURCPU_SPACE(s, r) GET_CURCPU(r) 199 #define GET_CURLWP(r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(r), r 200 #define GET_CURLWP_SPACE(s, r) mfctl CR_CURCPU, r ! ldw CI_CURLWP(s, r), r 201 202 /* 203 * Issue barriers to coordinate mutex_exit on this CPU with 204 * mutex_vector_enter on another CPU. 205 * 206 * 1. Any prior mutex_exit by oldlwp must be visible to other 207 * CPUs before we set ci_curlwp := newlwp on this one, 208 * requiring a store-before-store barrier. 209 * 210 * 2. ci_curlwp := newlwp must be visible on all other CPUs 211 * before any subsequent mutex_exit by newlwp can even test 212 * whether there might be waiters, requiring a 213 * store-before-load barrier. 214 * 215 * See kern_mutex.c for details -- this is necessary for 216 * adaptive mutexes to detect whether the lwp is on the CPU in 217 * order to safely block without requiring atomic r/m/w in 218 * mutex_exit. 219 */ 220 #define SET_CURLWP(r,t) \ 221 sync ! mfctl CR_CURCPU, t ! stw r, CI_CURLWP(t) ! sync 222 223 #else /* MULTIPROCESSOR */ 224 225 #define GET_CURCPU(r) mfctl CR_CURLWP, r ! ldw L_CPU(r), r 226 #define GET_CURCPU_SPACE(s, r) mfctl CR_CURLWP, r ! ldw L_CPU(s, r), r 227 #define GET_CURLWP(r) mfctl CR_CURLWP, r 228 #define GET_CURLWP_SPACE(s, r) GET_CURLWP(r) 229 230 #define SET_CURLWP(r,t) mtctl r, CR_CURLWP 231 232 #endif /* MULTIPROCESSOR */ 233 234 #ifndef _LOCORE 235 #ifdef _KERNEL 236 237 /* 238 * External definitions unique to PA-RISC cpu support. 239 * These are the "public" declarations - those needed in 240 * machine-independent source code. The "private" ones 241 * are in machdep.h. 242 * 243 * Note that the name of this file is NOT meant to imply 244 * that it has anything to do with PA-RISC CPU stuff. 245 * The name "cpu" is historical, and used in the common 246 * code to identify machine-dependent functions, etc. 247 */ 248 249 /* clockframe describes the system before we took an interrupt. */ 250 struct clockframe { 251 int cf_flags; 252 int cf_spl; 253 u_int cf_pc; 254 }; 255 #define CLKF_PC(framep) ((framep)->cf_pc) 256 #define CLKF_INTR(framep) ((framep)->cf_flags & TFF_INTR) 257 #define CLKF_USERMODE(framep) ((framep)->cf_flags & T_USER) 258 259 int clock_intr(void *); 260 261 /* 262 * LWP_PC: the program counter for the given lwp. 263 */ 264 #define LWP_PC(l) ((l)->l_md.md_regs->tf_iioq_head) 265 266 #define cpu_signotify(l) (setsoftast(l)) 267 #define cpu_need_proftick(l) ((l)->l_pflag |= LP_OWEUPC, setsoftast(l)) 268 269 #endif /* _KERNEL */ 270 271 #ifndef __ASSEMBLER__ 272 #if defined(_KERNEL) || defined(_KMEMUSER) 273 274 #include <sys/cpu_data.h> 275 #include <sys/evcnt.h> 276 277 /* 278 * Note that the alignment of ci_trap_save is important since we want to keep 279 * it within a single cache line. As a result, it must be kept as the first 280 * entry within the cpu_info struct. 281 */ 282 struct cpu_info { 283 /* Keep this first to simplify the trap handlers */ 284 register_t ci_trapsave[16];/* the "phys" part of frame */ 285 286 struct cpu_data ci_data; /* MI per-cpu data */ 287 288 #ifndef _KMEMUSER 289 hppa_hpa_t ci_hpa; 290 register_t ci_psw; /* Processor Status Word. */ 291 paddr_t ci_fpu_state; /* LWP FPU state address, or zero. */ 292 u_long ci_itmr; 293 294 int ci_cpuid; /* CPU index (see cpus[] array) */ 295 int ci_mtx_count; 296 int ci_mtx_oldspl; 297 int ci_want_resched; 298 299 volatile int ci_cpl; 300 volatile int ci_ipending; /* The pending interrupts. */ 301 u_int ci_intr_depth; /* Nonzero iff running an interrupt. */ 302 u_int ci_ishared; 303 u_int ci_eiem; 304 305 u_int ci_imask[NIPL]; 306 307 struct hppa_interrupt_register ci_ir; 308 struct hppa_interrupt_bit ci_ib[HPPA_INTERRUPT_BITS]; 309 310 #if defined(MULTIPROCESSOR) 311 struct lwp *ci_curlwp; /* CPU owner */ 312 paddr_t ci_stack; /* stack for spin up */ 313 volatile int ci_flags; /* CPU status flags */ 314 #define CPUF_PRIMARY 0x0001 /* ... is monarch/primary */ 315 #define CPUF_RUNNING 0x0002 /* ... is running. */ 316 317 volatile u_long ci_ipi; /* IPIs pending */ 318 319 struct cpu_softc *ci_softc; 320 #endif 321 322 #endif /* !_KMEMUSER */ 323 } __aligned(64); 324 325 #endif /* _KERNEL || _KMEMUSER */ 326 #endif /* __ASSEMBLER__ */ 327 328 #if defined(_KERNEL) 329 330 /* 331 * definitions of cpu-dependent requirements 332 * referenced in generic code 333 */ 334 335 void cpu_proc_fork(struct proc *, struct proc *); 336 337 #ifdef MULTIPROCESSOR 338 339 /* Number of CPUs in the system */ 340 extern int hppa_ncpu; 341 342 #define HPPA_MAXCPUS 4 343 #define cpu_number() (curcpu()->ci_cpuid) 344 345 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0) 346 #define CPU_INFO_ITERATOR int 347 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = &cpus[0]; cii < hppa_ncpu; cii++, ci++ 348 349 void cpu_boot_secondary_processors(void); 350 351 static __inline struct cpu_info * 352 hppa_curcpu(void) 353 { 354 struct cpu_info *ci; 355 356 __asm volatile("mfctl %1, %0" : "=r" (ci): "i" (CR_CURCPU)); 357 358 return ci; 359 } 360 361 #define curcpu() hppa_curcpu() 362 363 #else /* MULTIPROCESSOR */ 364 365 #define HPPA_MAXCPUS 1 366 #define curcpu() (&cpus[0]) 367 #define cpu_number() 0 368 369 static __inline struct lwp * 370 hppa_curlwp(void) 371 { 372 struct lwp *l; 373 374 __asm volatile("mfctl %1, %0" : "=r" (l): "i" (CR_CURLWP)); 375 376 return l; 377 } 378 379 #define curlwp hppa_curlwp() 380 381 #endif /* MULTIPROCESSOR */ 382 383 extern struct cpu_info cpus[HPPA_MAXCPUS]; 384 385 #define DELAY(x) delay(x) 386 387 static __inline paddr_t 388 kvtop(const void *va) 389 { 390 paddr_t pa; 391 392 __asm volatile ("lpa %%r0(%1), %0" : "=r" (pa) : "r" (va)); 393 return pa; 394 } 395 396 extern int (*cpu_desidhash)(void); 397 398 static __inline bool 399 hppa_cpu_ispa20_p(void) 400 { 401 402 return (hppa_cpu_info->hci_features & HPPA_FTRS_W32B) != 0; 403 } 404 405 static __inline bool 406 hppa_cpu_hastlbu_p(void) 407 { 408 409 return (hppa_cpu_info->hci_features & HPPA_FTRS_TLBU) != 0; 410 } 411 412 void delay(u_int); 413 void hppa_init(paddr_t, void *); 414 void trap(int, struct trapframe *); 415 void hppa_ras(struct lwp *); 416 int spcopy(pa_space_t, const void *, pa_space_t, void *, size_t); 417 int spstrcpy(pa_space_t, const void *, pa_space_t, void *, size_t, 418 size_t *); 419 int copy_on_fault(void); 420 void lwp_trampoline(void); 421 int cpu_dumpsize(void); 422 int cpu_dump(void); 423 424 #ifdef MULTIPROCESSOR 425 void cpu_boot_secondary_processors(void); 426 void cpu_hw_init(void); 427 void cpu_hatch(void); 428 #endif 429 #endif /* _KERNEL */ 430 431 /* 432 * Boot arguments stuff 433 */ 434 435 #define BOOTARG_LEN (PAGE_SIZE) 436 #define BOOTARG_OFF (0x10000) 437 438 /* 439 * CTL_MACHDEP definitions. 440 */ 441 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 442 #define CPU_BOOTED_KERNEL 2 /* string: booted kernel name */ 443 #define CPU_LCD_BLINK 3 /* int: twiddle heartbeat LED/LCD */ 444 445 #ifdef _KERNEL 446 #include <sys/queue.h> 447 448 struct blink_lcd { 449 void (*bl_func)(void *, int); 450 void *bl_arg; 451 SLIST_ENTRY(blink_lcd) bl_next; 452 }; 453 454 extern void blink_lcd_register(struct blink_lcd *); 455 #endif /* _KERNEL */ 456 #endif /* !_LOCORE */ 457 458 #endif /* _MACHINE_CPU_H_ */ 459
Indexes created Sat Oct 18 23:09:54 GMT 2025