intr.h revision 1.1
1 /* $NetBSD: intr.h,v 1.1 2014/02/24 07:23:43 skrll Exp $ */ 2 /* $OpenBSD: intr.h,v 1.26 2009/12/29 13:11:40 jsing Exp $ */ 3 4 /*- 5 * Copyright (c) 1998, 2001, 2002 The NetBSD Foundation, Inc. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to The NetBSD Foundation 9 * by Charles M. Hannum, and by Jason R. Thorpe, and by Matthew Fredette. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _HPPA_INTR_H_ 34 #define _HPPA_INTR_H_ 35 36 #include <machine/psl.h> 37 #include <machine/intrdefs.h> 38 39 #include <sys/evcnt.h> 40 41 #ifndef _LOCORE 42 43 #ifdef _KERNEL 44 45 struct cpu_info; 46 47 /* 48 * The maximum number of bits in a cpl value/spl mask, the maximum number of 49 * bits in an interrupt request register, and the maximum number of interrupt 50 * registers. 51 */ 52 #define HPPA_INTERRUPT_BITS (32) 53 #define CPU_NINTS HPPA_INTERRUPT_BITS /* Use this one */ 54 55 /* 56 * This describes one HPPA interrupt register. 57 */ 58 struct hppa_interrupt_register { 59 bool ir_iscpu; 60 const char *ir_name; /* name for this intr reg */ 61 struct cpu_info *ir_ci; /* cpu this intr reg */ 62 63 /* 64 * The virtual address of the mask, request and level 65 * registers. 66 */ 67 volatile int *ir_mask; 68 volatile int *ir_req; 69 volatile int *ir_level; 70 71 /* 72 * This array has one entry for each bit in the interrupt request 73 * register. 74 * 75 * If the 24 most significant bits are set, the low 8 bits are the 76 * index of the hppa_interrupt_register that this interrupt bit leads 77 * to, with zero meaning that the interrupt bit is unused. 78 * 79 * Otherwise these bits correspond to hppa_interrupt_bits. That is, 80 * these bits are ORed to ipending_new in hppa_intr_ipending() when 81 * an interrupt happens. 82 * 83 * Note that this array is indexed by HP bit number, *not* by "normal" 84 * bit number. In other words, the least significant bit in the inter- 85 * rupt register corresponds to array index 31. 86 */ 87 88 unsigned int ir_bits_map[HPPA_INTERRUPT_BITS]; 89 90 #define IR_BIT_MASK 0xffffff00 91 #define IR_BIT_REG(x) (IR_BIT_MASK | (x)) 92 #define IR_BIT_UNUSED IR_BIT_REG(0) 93 #define IR_BIT_USED_P(x) (((x) & IR_BIT_MASK) != IR_BIT_MASK) 94 #define IR_BIT_NESTED_P(x) (((x) & IR_BIT_MASK) == IR_BIT_MASK) 95 96 int ir_bits; /* mask of allocatable bit numbers */ 97 int ir_rbits; /* mask of reserved (for lasi/asp) bit numbers */ 98 }; 99 100 struct hppa_interrupt_bit { 101 102 /* 103 * The interrupt register this bit is in. Some handlers, e.g 104 * apic_intr, don't make use of an hppa_interrupt_register, but are 105 * nested. 106 */ 107 struct hppa_interrupt_register *ib_reg; 108 109 /* 110 * The priority level associated with this bit, e.g, IPL_BIO, IPL_NET, 111 * etc. 112 */ 113 int ib_ipl; 114 115 /* 116 * The spl mask for this bit. This starts out as the spl bit assigned 117 * to this particular interrupt, and later gets fleshed out by the mask 118 * calculator to be the full mask that we need to raise spl to when we 119 * get this interrupt. 120 */ 121 int ib_spl; 122 123 /* The interrupt name. */ 124 char ib_name[16]; 125 126 /* The interrupt event count. */ 127 struct evcnt ib_evcnt; 128 129 /* 130 * The interrupt handler and argument for this bit. If the argument is 131 * NULL, the handler gets the trapframe. 132 */ 133 int (*ib_handler)(void *); 134 void *ib_arg; 135 136 }; 137 138 void hppa_intr_bootstrap(void); 139 void hppa_intr_initialise(struct cpu_info *); 140 void hppa_interrupt_register_establish(struct cpu_info *, 141 struct hppa_interrupt_register *); 142 void * hppa_intr_establish(int, int (*)(void *), void *, 143 struct hppa_interrupt_register *, int); 144 int hppa_intr_allocate_bit(struct hppa_interrupt_register *, int); 145 void hppa_intr_enable(void); 146 147 /* splraise()/spllower() are in locore.S */ 148 int splraise(int); 149 void spllower(int); 150 151 /* 152 * Miscellaneous 153 */ 154 #define spl0() spllower(0) 155 #define splx(x) spllower(x) 156 157 typedef int ipl_t; 158 typedef struct { 159 ipl_t _ipl; 160 } ipl_cookie_t; 161 162 static inline ipl_cookie_t 163 makeiplcookie(ipl_t ipl) 164 { 165 166 return (ipl_cookie_t){._ipl = ipl}; 167 } 168 169 static inline int 170 splraiseipl(ipl_cookie_t icookie) 171 { 172 173 return splraise(icookie._ipl); 174 } 175 176 #include <sys/spl.h> 177 #endif 178 179 #define setsoftast(l) ((l)->l_md.md_astpending = 1) 180 181 #ifdef MULTIPROCESSOR 182 183 struct cpu_info; 184 185 void hppa_ipi_init(struct cpu_info *); 186 int hppa_ipi_intr(void *arg); 187 int hppa_ipi_send(struct cpu_info *, u_long); 188 int hppa_ipi_broadcast(u_long); 189 #endif 190 191 #endif /* !_LOCORE */ 192 193 #endif /* !_HPPA_INTR_H_ */ 194
Indexes created Wed Sep 24 05:09:52 GMT 2025