cpu.h revision 1.130
1 /* $NetBSD: cpu.h,v 1.130 2006/12/08 15:05:18 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _I386_CPU_H_ 38 #define _I386_CPU_H_ 39 40 #ifdef _KERNEL 41 #if defined(_KERNEL_OPT) 42 #include "opt_enhanced_speedstep.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_math_emulate.h" 45 #include "opt_user_ldt.h" 46 #include "opt_vm86.h" 47 #endif 48 49 /* 50 * Definitions unique to i386 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/segments.h> 54 #include <machine/tss.h> 55 #include <machine/intrdefs.h> 56 #include <x86/cacheinfo.h> 57 58 #include <sys/device.h> 59 #include <sys/lock.h> /* will also get LOCKDEBUG */ 60 #include <sys/cpu_data.h> 61 #include <sys/cc_microtime.h> 62 63 #include <lib/libkern/libkern.h> /* offsetof */ 64 65 struct intrsource; 66 struct pmap; 67 68 /* 69 * a bunch of this belongs in cpuvar.h; move it later.. 70 */ 71 72 struct cpu_info { 73 struct device *ci_dev; /* pointer to our device */ 74 struct cpu_info *ci_self; /* self-pointer */ 75 void *ci_tlog_base; /* Trap log base */ 76 int32_t ci_tlog_offset; /* Trap log current offset */ 77 struct cpu_info *ci_next; /* next cpu */ 78 79 /* 80 * Public members. 81 */ 82 struct lwp *ci_curlwp; /* current owner of the processor */ 83 struct simplelock ci_slock; /* lock on this data structure */ 84 cpuid_t ci_cpuid; /* our CPU ID */ 85 u_int ci_apicid; /* our APIC ID */ 86 struct cpu_data ci_data; /* MI per-cpu data */ 87 struct cc_microtime_state ci_cc;/* cc_microtime state */ 88 89 /* 90 * Private members. 91 */ 92 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 93 int ci_fpsaving; /* save in progress */ 94 95 volatile uint32_t ci_tlb_ipi_mask; 96 97 struct pmap *ci_pmap; /* current pmap */ 98 int ci_want_pmapload; /* pmap_load() is needed */ 99 int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 100 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 101 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 102 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 103 104 struct pcb *ci_curpcb; /* VA of current HW PCB */ 105 struct pcb *ci_idle_pcb; /* VA of current PCB */ 106 int ci_idle_tss_sel; /* TSS selector of idle PCB */ 107 108 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 109 uint32_t ci_ipending; 110 int ci_ilevel; 111 int ci_idepth; 112 uint32_t ci_imask[NIPL]; 113 uint32_t ci_iunmask[NIPL]; 114 void * ci_intrstack; 115 116 paddr_t ci_idle_pcb_paddr; /* PA of idle PCB */ 117 uint32_t ci_flags; /* flags; see below */ 118 uint32_t ci_ipis; /* interprocessor interrupts pending */ 119 int sc_apic_version; /* local APIC version */ 120 121 int32_t ci_cpuid_level; 122 uint32_t ci_signature; /* X86 cpuid type */ 123 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 124 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 125 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 126 uint32_t ci_cpu_class; /* CPU class */ 127 uint32_t ci_brand_id; /* Intel brand id */ 128 uint32_t ci_vendor[4]; /* vendor string */ 129 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 130 uint64_t ci_tsc_freq; /* cpu cycles/second */ 131 132 struct cpu_functions *ci_func; /* start/stop functions */ 133 void (*cpu_setup)(struct cpu_info *); 134 /* proc-dependant init */ 135 void (*ci_info)(struct cpu_info *); 136 137 int ci_want_resched; 138 int ci_astpending; 139 struct trapframe *ci_ddb_regs; 140 141 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 142 struct x86_cache_info ci_cinfo[CAI_COUNT]; 143 144 union descriptor *ci_gdt; 145 146 struct i386tss ci_doubleflt_tss; 147 struct i386tss ci_ddbipi_tss; 148 149 char *ci_doubleflt_stack; 150 char *ci_ddbipi_stack; 151 152 struct evcnt ci_ipi_events[X86_NIPI]; 153 }; 154 155 /* 156 * Processor flag notes: The "primary" CPU has certain MI-defined 157 * roles (mostly relating to hardclock handling); we distinguish 158 * betwen the processor which booted us, and the processor currently 159 * holding the "primary" role just to give us the flexibility later to 160 * change primaries should we be sufficiently twisted. 161 */ 162 163 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 164 #define CPUF_AP 0x0002 /* CPU is an AP */ 165 #define CPUF_SP 0x0004 /* CPU is only processor */ 166 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 167 168 #define CPUF_APIC_CD 0x0010 /* CPU has apic configured */ 169 170 #define CPUF_PRESENT 0x1000 /* CPU is present */ 171 #define CPUF_RUNNING 0x2000 /* CPU is running */ 172 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 173 #define CPUF_GO 0x8000 /* CPU should start running */ 174 175 /* 176 * We statically allocate the CPU info for the primary CPU (or, 177 * the only CPU on uniprocessors), and the primary CPU is the 178 * first CPU on the CPU info list. 179 */ 180 extern struct cpu_info cpu_info_primary; 181 extern struct cpu_info *cpu_info_list; 182 183 #define CPU_INFO_ITERATOR int 184 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 185 ci != NULL; ci = ci->ci_next 186 187 #if defined(MULTIPROCESSOR) 188 189 #define X86_MAXPROCS 32 /* because we use a bitmask */ 190 191 #define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci)) 192 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 193 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 194 195 static struct cpu_info *curcpu(void); 196 197 __inline static struct cpu_info * __attribute__((__unused__)) 198 curcpu() 199 { 200 struct cpu_info *ci; 201 202 __asm volatile("movl %%fs:%1, %0" : 203 "=r" (ci) : 204 "m" 205 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self))); 206 return ci; 207 } 208 209 #define cpu_number() (curcpu()->ci_cpuid) 210 211 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 212 213 #define aston(p) ((p)->p_md.md_astpending = 1) 214 215 extern struct cpu_info *cpu_info[X86_MAXPROCS]; 216 217 void cpu_boot_secondary_processors(void); 218 void cpu_init_idle_pcbs(void); 219 220 /* 221 * Preempt the current process if in interrupt from user mode, 222 * or after the current trap/syscall if in system mode. 223 */ 224 extern void need_resched(struct cpu_info *); 225 226 #else /* !MULTIPROCESSOR */ 227 228 #define X86_MAXPROCS 1 229 #define curcpu() (&cpu_info_primary) 230 231 /* 232 * definitions of cpu-dependent requirements 233 * referenced in generic code 234 */ 235 #define cpu_number() 0 236 #define CPU_IS_PRIMARY(ci) 1 237 238 /* 239 * Preempt the current process if in interrupt from user mode, 240 * or after the current trap/syscall if in system mode. 241 */ 242 #define need_resched(ci) \ 243 do { \ 244 struct cpu_info *__ci = (ci); \ 245 __ci->ci_want_resched = 1; \ 246 if (__ci->ci_curlwp != NULL) \ 247 aston(__ci->ci_curlwp->l_proc); \ 248 } while (/*CONSTCOND*/0) 249 250 #define aston(p) ((p)->p_md.md_astpending = 1) 251 252 #endif /* MULTIPROCESSOR */ 253 254 extern uint32_t cpus_attached; 255 256 #define curpcb curcpu()->ci_curpcb 257 #define curlwp curcpu()->ci_curlwp 258 259 /* 260 * Arguments to hardclock, softclock and statclock 261 * encapsulate the previous machine state in an opaque 262 * clockframe; for now, use generic intrframe. 263 * 264 * Note: Since spllowersoftclock() does not actually unmask the currently 265 * running (hardclock) interrupt, CLKF_BASEPRI() *must* always be 0; otherwise 266 * we could stall hardclock ticks if another interrupt takes too long. 267 */ 268 struct clockframe { 269 struct intrframe cf_if; 270 }; 271 272 #define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags) 273 #define CLKF_BASEPRI(frame) (0) 274 #define CLKF_PC(frame) ((frame)->cf_if.if_eip) 275 #define CLKF_INTR(frame) (curcpu()->ci_idepth > 0) 276 277 /* 278 * This is used during profiling to integrate system time. It can safely 279 * assume that the process is resident. 280 */ 281 #define LWP_PC(l) ((l)->l_md.md_regs->tf_eip) 282 283 /* 284 * Give a profiling tick to the current process when the user profiling 285 * buffer pages are invalid. On the i386, request an ast to send us 286 * through trap(), marking the proc as needing a profiling tick. 287 */ 288 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, aston(p)) 289 290 /* 291 * Notify the current process (p) that it has a signal pending, 292 * process as soon as possible. 293 */ 294 #define signotify(p) aston(p) 295 296 /* 297 * We need a machine-independent name for this. 298 */ 299 extern void (*delay_func)(int); 300 struct timeval; 301 302 #define DELAY(x) (*delay_func)(x) 303 #define delay(x) (*delay_func)(x) 304 305 /* 306 * pull in #defines for kinds of processors 307 */ 308 #include <machine/cputypes.h> 309 310 struct cpu_nocpuid_nameclass { 311 int cpu_vendor; 312 const char *cpu_vendorname; 313 const char *cpu_name; 314 int cpu_class; 315 void (*cpu_setup)(struct cpu_info *); 316 void (*cpu_cacheinfo)(struct cpu_info *); 317 void (*cpu_info)(struct cpu_info *); 318 }; 319 320 321 struct cpu_cpuid_nameclass { 322 const char *cpu_id; 323 int cpu_vendor; 324 const char *cpu_vendorname; 325 struct cpu_cpuid_family { 326 int cpu_class; 327 const char *cpu_models[CPU_MAXMODEL+2]; 328 void (*cpu_setup)(struct cpu_info *); 329 void (*cpu_probe)(struct cpu_info *); 330 void (*cpu_info)(struct cpu_info *); 331 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 332 }; 333 334 extern int biosbasemem; 335 extern int biosextmem; 336 extern unsigned int cpu_feature; 337 extern unsigned int cpu_feature2; 338 extern int cpu; 339 extern int cpu_class; 340 extern char cpu_brand_string[]; 341 extern const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[]; 342 extern const struct cpu_cpuid_nameclass i386_cpuid_cpus[]; 343 344 extern int i386_use_fxsave; 345 extern int i386_has_sse; 346 extern int i386_has_sse2; 347 348 /* machdep.c */ 349 void dumpconf(void); 350 int cpu_maxproc(void); 351 void cpu_reset(void); 352 void i386_init_pcb_tss_ldt(struct cpu_info *); 353 void i386_proc0_tss_ldt_init(void); 354 355 /* identcpu.c */ 356 #ifdef ENHANCED_SPEEDSTEP 357 extern int bus_clock; 358 #endif 359 extern int tmx86_has_longrun; 360 extern u_int crusoe_longrun; 361 extern u_int crusoe_frequency; 362 extern u_int crusoe_voltage; 363 extern u_int crusoe_percentage; 364 extern u_int tmx86_set_longrun_mode(u_int); 365 void tmx86_get_longrun_status_all(void); 366 u_int tmx86_get_longrun_mode(void); 367 void identifycpu(struct cpu_info *); 368 369 /* vm_machdep.c */ 370 void cpu_proc_fork(struct proc *, struct proc *); 371 372 /* locore.s */ 373 struct region_descriptor; 374 void lgdt(struct region_descriptor *); 375 void fillw(short, void *, size_t); 376 377 struct pcb; 378 void savectx(struct pcb *); 379 void proc_trampoline(void); 380 381 /* clock.c */ 382 void initrtclock(u_long); 383 void startrtclock(void); 384 void i8254_delay(int); 385 void i8254_microtime(struct timeval *); 386 void i8254_initclocks(void); 387 388 /* cpu.c */ 389 390 void cpu_probe_features(struct cpu_info *); 391 392 /* npx.c */ 393 void npxsave_lwp(struct lwp *, int); 394 void npxsave_cpu(struct cpu_info *, int); 395 396 /* vm_machdep.c */ 397 int kvtop(caddr_t); 398 399 #ifdef MATH_EMULATE 400 /* math_emulate.c */ 401 int math_emulate(struct trapframe *, ksiginfo_t *); 402 #endif 403 404 #ifdef USER_LDT 405 /* sys_machdep.h */ 406 int i386_get_ldt(struct lwp *, void *, register_t *); 407 int i386_set_ldt(struct lwp *, void *, register_t *); 408 #endif 409 410 /* isa_machdep.c */ 411 void isa_defaultirq(void); 412 int isa_nmi(void); 413 414 #ifdef VM86 415 /* vm86.c */ 416 void vm86_gpfault(struct lwp *, int); 417 #endif /* VM86 */ 418 419 /* consinit.c */ 420 void kgdb_port_init(void); 421 422 /* bus_machdep.c */ 423 void x86_bus_space_init(void); 424 void x86_bus_space_mallocok(void); 425 426 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 427 428 /* est.c */ 429 void est_init(struct cpu_info *, int); 430 431 #endif /* _KERNEL */ 432 433 /* 434 * CTL_MACHDEP definitions. 435 */ 436 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 437 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 438 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 439 #define CPU_NKPDE 4 /* int: number of kernel PDEs */ 440 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 441 #define CPU_DISKINFO 6 /* struct disklist *: 442 * disk geometry information */ 443 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 444 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 445 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 446 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 447 #define CPU_TMLR_MODE 11 /* int: longrun mode 448 * 0: minimum frequency 449 * 1: economy 450 * 2: performance 451 * 3: maximum frequency 452 */ 453 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 454 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 455 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 456 #define CPU_MAXID 15 /* number of valid machdep ids */ 457 458 #define CTL_MACHDEP_NAMES { \ 459 { 0, 0 }, \ 460 { "console_device", CTLTYPE_STRUCT }, \ 461 { "biosbasemem", CTLTYPE_INT }, \ 462 { "biosextmem", CTLTYPE_INT }, \ 463 { "nkpde", CTLTYPE_INT }, \ 464 { "booted_kernel", CTLTYPE_STRING }, \ 465 { "diskinfo", CTLTYPE_STRUCT }, \ 466 { "fpu_present", CTLTYPE_INT }, \ 467 { "osfxsr", CTLTYPE_INT }, \ 468 { "sse", CTLTYPE_INT }, \ 469 { "sse2", CTLTYPE_INT }, \ 470 { "tm_longrun_mode", CTLTYPE_INT }, \ 471 { "tm_longrun_frequency", CTLTYPE_INT }, \ 472 { "tm_longrun_voltage", CTLTYPE_INT }, \ 473 { "tm_longrun_percentage", CTLTYPE_INT }, \ 474 } 475 476 /* 477 * Structure for CPU_DISKINFO sysctl call. 478 * XXX this should be somewhere else. 479 */ 480 #define MAX_BIOSDISKS 16 481 482 struct disklist { 483 int dl_nbiosdisks; /* number of bios disks */ 484 struct biosdisk_info { 485 int bi_dev; /* BIOS device # (0x80 ..) */ 486 int bi_cyl; /* cylinders on disk */ 487 int bi_head; /* heads per track */ 488 int bi_sec; /* sectors per track */ 489 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 490 #define BIFLAG_INVALID 0x01 491 #define BIFLAG_EXTINT13 0x02 492 int bi_flags; 493 } dl_biosdisks[MAX_BIOSDISKS]; 494 495 int dl_nnativedisks; /* number of native disks */ 496 struct nativedisk_info { 497 char ni_devname[16]; /* native device name */ 498 int ni_nmatches; /* # of matches w/ BIOS */ 499 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 500 } dl_nativedisks[1]; /* actually longer */ 501 }; 502 #endif /* !_I386_CPU_H_ */ 503
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