cpu.h revision 1.140
1 /* $NetBSD: cpu.h,v 1.140 2007/04/16 19:12:18 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _I386_CPU_H_ 38 #define _I386_CPU_H_ 39 40 #ifdef _KERNEL 41 #if defined(_KERNEL_OPT) 42 #include "opt_enhanced_speedstep.h" 43 #include "opt_multiprocessor.h" 44 #include "opt_math_emulate.h" 45 #include "opt_user_ldt.h" 46 #include "opt_vm86.h" 47 #endif 48 49 /* 50 * Definitions unique to i386 cpu support. 51 */ 52 #include <machine/frame.h> 53 #include <machine/segments.h> 54 #include <machine/tss.h> 55 #include <machine/intrdefs.h> 56 #include <x86/cacheinfo.h> 57 #include <x86/via_padlock.h> 58 59 #include <sys/device.h> 60 #include <sys/simplelock.h> /* will also get LOCKDEBUG */ 61 #include <sys/cpu_data.h> 62 #include <sys/cc_microtime.h> 63 64 #include <lib/libkern/libkern.h> /* offsetof */ 65 66 struct intrsource; 67 struct pmap; 68 69 /* 70 * a bunch of this belongs in cpuvar.h; move it later.. 71 */ 72 73 struct cpu_info { 74 struct device *ci_dev; /* pointer to our device */ 75 struct cpu_info *ci_self; /* self-pointer */ 76 void *ci_self150; /* self + 0x150, see lock_stubs.S */ 77 void *ci_tlog_base; /* Trap log base */ 78 int32_t ci_tlog_offset; /* Trap log current offset */ 79 struct cpu_info *ci_next; /* next cpu */ 80 81 /* 82 * Public members. 83 */ 84 struct lwp *ci_curlwp; /* current owner of the processor */ 85 struct simplelock ci_slock; /* lock on this data structure */ 86 cpuid_t ci_cpuid; /* our CPU ID */ 87 u_int ci_apicid; /* our APIC ID */ 88 struct cpu_data ci_data; /* MI per-cpu data */ 89 struct cc_microtime_state ci_cc;/* cc_microtime state */ 90 91 /* 92 * Private members. 93 */ 94 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 95 int ci_fpsaving; /* save in progress */ 96 97 volatile uint32_t ci_tlb_ipi_mask; 98 99 struct pmap *ci_pmap; /* current pmap */ 100 int ci_want_pmapload; /* pmap_load() is needed */ 101 int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 102 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 103 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 104 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 105 106 struct pcb *ci_curpcb; /* VA of current HW PCB */ 107 struct pcb *ci_idle_pcb; /* VA of current PCB */ 108 int ci_idle_tss_sel; /* TSS selector of idle PCB */ 109 110 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 111 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 112 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 113 114 /* The following must be aligned for cmpxchg8b. */ 115 struct { 116 uint32_t ipending; 117 int ilevel; 118 } ci_istate __aligned(8); 119 #define ci_ipending ci_istate.ipending 120 #define ci_ilevel ci_istate.ilevel 121 122 int ci_idepth; 123 uint32_t ci_imask[NIPL]; 124 uint32_t ci_iunmask[NIPL]; 125 void * ci_intrstack; 126 127 paddr_t ci_idle_pcb_paddr; /* PA of idle PCB */ 128 uint32_t ci_flags; /* flags; see below */ 129 uint32_t ci_ipis; /* interprocessor interrupts pending */ 130 int sc_apic_version; /* local APIC version */ 131 132 int32_t ci_cpuid_level; 133 uint32_t ci_signature; /* X86 cpuid type */ 134 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 135 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 136 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 137 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 138 uint32_t ci_cpu_class; /* CPU class */ 139 uint32_t ci_brand_id; /* Intel brand id */ 140 uint32_t ci_vendor[4]; /* vendor string */ 141 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 142 uint64_t ci_tsc_freq; /* cpu cycles/second */ 143 144 const struct cpu_functions *ci_func; /* start/stop functions */ 145 void (*cpu_setup)(struct cpu_info *); 146 /* proc-dependant init */ 147 void (*ci_info)(struct cpu_info *); 148 149 int ci_want_resched; 150 int ci_astpending; 151 struct trapframe *ci_ddb_regs; 152 153 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 154 struct x86_cache_info ci_cinfo[CAI_COUNT]; 155 156 union descriptor *ci_gdt; 157 158 struct i386tss ci_doubleflt_tss; 159 struct i386tss ci_ddbipi_tss; 160 161 char *ci_doubleflt_stack; 162 char *ci_ddbipi_stack; 163 164 struct evcnt ci_ipi_events[X86_NIPI]; 165 166 struct via_padlock ci_vp; /* VIA PadLock private storage */ 167 }; 168 169 /* 170 * Processor flag notes: The "primary" CPU has certain MI-defined 171 * roles (mostly relating to hardclock handling); we distinguish 172 * betwen the processor which booted us, and the processor currently 173 * holding the "primary" role just to give us the flexibility later to 174 * change primaries should we be sufficiently twisted. 175 */ 176 177 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 178 #define CPUF_AP 0x0002 /* CPU is an AP */ 179 #define CPUF_SP 0x0004 /* CPU is only processor */ 180 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 181 182 #define CPUF_APIC_CD 0x0010 /* CPU has apic configured */ 183 184 #define CPUF_PRESENT 0x1000 /* CPU is present */ 185 #define CPUF_RUNNING 0x2000 /* CPU is running */ 186 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 187 #define CPUF_GO 0x8000 /* CPU should start running */ 188 189 /* 190 * We statically allocate the CPU info for the primary CPU (or, 191 * the only CPU on uniprocessors), and the primary CPU is the 192 * first CPU on the CPU info list. 193 */ 194 extern struct cpu_info cpu_info_primary; 195 extern struct cpu_info *cpu_info_list; 196 197 #define CPU_INFO_ITERATOR int 198 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 199 ci != NULL; ci = ci->ci_next 200 201 #if defined(MULTIPROCESSOR) 202 203 #define X86_MAXPROCS 32 /* because we use a bitmask */ 204 205 #define CPU_STARTUP(_ci) ((_ci)->ci_func->start(_ci)) 206 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 207 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 208 209 static struct cpu_info *curcpu(void); 210 211 __inline static struct cpu_info * __attribute__((__unused__)) 212 curcpu() 213 { 214 struct cpu_info *ci; 215 216 __asm volatile("movl %%fs:%1, %0" : 217 "=r" (ci) : 218 "m" 219 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self))); 220 return ci; 221 } 222 223 #define cpu_number() (curcpu()->ci_cpuid) 224 225 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 226 227 #define aston(l) ((l)->l_md.md_astpending = 1) 228 229 extern struct cpu_info *cpu_info[X86_MAXPROCS]; 230 231 void cpu_boot_secondary_processors(void); 232 void cpu_init_idle_pcbs(void); 233 234 #else /* !MULTIPROCESSOR */ 235 236 #define X86_MAXPROCS 1 237 #define curcpu() (&cpu_info_primary) 238 239 /* 240 * definitions of cpu-dependent requirements 241 * referenced in generic code 242 */ 243 #define cpu_number() 0 244 #define CPU_IS_PRIMARY(ci) 1 245 246 #define aston(l) ((l)->l_md.md_astpending = 1) 247 248 #endif /* MULTIPROCESSOR */ 249 250 /* 251 * Preempt the current process if in interrupt from user mode, 252 * or after the current trap/syscall if in system mode. 253 */ 254 extern void cpu_need_resched(struct cpu_info *); 255 256 extern uint32_t cpus_attached; 257 258 #define curpcb curcpu()->ci_curpcb 259 #define curlwp curcpu()->ci_curlwp 260 261 /* 262 * Arguments to hardclock, softclock and statclock 263 * encapsulate the previous machine state in an opaque 264 * clockframe; for now, use generic intrframe. 265 */ 266 struct clockframe { 267 struct intrframe cf_if; 268 }; 269 270 #define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags) 271 #define CLKF_PC(frame) ((frame)->cf_if.if_eip) 272 #define CLKF_INTR(frame) (curcpu()->ci_idepth > 0) 273 274 /* 275 * This is used during profiling to integrate system time. It can safely 276 * assume that the process is resident. 277 */ 278 #define LWP_PC(l) ((l)->l_md.md_regs->tf_eip) 279 280 /* 281 * Give a profiling tick to the current process when the user profiling 282 * buffer pages are invalid. On the i386, request an ast to send us 283 * through trap(), marking the proc as needing a profiling tick. 284 */ 285 extern void cpu_need_proftick(struct lwp *l); 286 287 /* 288 * Notify the LWP l that it has a signal pending, process as soon as 289 * possible. 290 */ 291 extern void cpu_signotify(struct lwp *); 292 293 /* 294 * We need a machine-independent name for this. 295 */ 296 extern void (*delay_func)(int); 297 struct timeval; 298 299 #define DELAY(x) (*delay_func)(x) 300 #define delay(x) (*delay_func)(x) 301 302 /* 303 * pull in #defines for kinds of processors 304 */ 305 #include <machine/cputypes.h> 306 307 struct cpu_nocpuid_nameclass { 308 int cpu_vendor; 309 const char *cpu_vendorname; 310 const char *cpu_name; 311 int cpu_class; 312 void (*cpu_setup)(struct cpu_info *); 313 void (*cpu_cacheinfo)(struct cpu_info *); 314 void (*cpu_info)(struct cpu_info *); 315 }; 316 317 318 struct cpu_cpuid_nameclass { 319 const char *cpu_id; 320 int cpu_vendor; 321 const char *cpu_vendorname; 322 struct cpu_cpuid_family { 323 int cpu_class; 324 const char *cpu_models[CPU_MAXMODEL+2]; 325 void (*cpu_setup)(struct cpu_info *); 326 void (*cpu_probe)(struct cpu_info *); 327 void (*cpu_info)(struct cpu_info *); 328 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 329 }; 330 331 extern int biosbasemem; 332 extern int biosextmem; 333 extern unsigned int cpu_feature; 334 extern unsigned int cpu_feature2; 335 extern unsigned int cpu_feature_padlock; 336 extern int cpu; 337 extern int cpu_class; 338 extern char cpu_brand_string[]; 339 extern const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[]; 340 extern const struct cpu_cpuid_nameclass i386_cpuid_cpus[]; 341 342 extern int i386_use_fxsave; 343 extern int i386_has_sse; 344 extern int i386_has_sse2; 345 346 /* machdep.c */ 347 void dumpconf(void); 348 int cpu_maxproc(void); 349 void cpu_reset(void); 350 void i386_init_pcb_tss_ldt(struct cpu_info *); 351 void i386_proc0_tss_ldt_init(void); 352 353 /* identcpu.c */ 354 #ifdef ENHANCED_SPEEDSTEP 355 extern int bus_clock; 356 #endif 357 extern int tmx86_has_longrun; 358 extern u_int crusoe_longrun; 359 extern u_int crusoe_frequency; 360 extern u_int crusoe_voltage; 361 extern u_int crusoe_percentage; 362 extern u_int tmx86_set_longrun_mode(u_int); 363 void tmx86_get_longrun_status_all(void); 364 u_int tmx86_get_longrun_mode(void); 365 void identifycpu(struct cpu_info *); 366 367 /* vm_machdep.c */ 368 void cpu_proc_fork(struct proc *, struct proc *); 369 370 /* locore.s */ 371 struct region_descriptor; 372 void lgdt(struct region_descriptor *); 373 void fillw(short, void *, size_t); 374 375 struct pcb; 376 void savectx(struct pcb *); 377 void proc_trampoline(void); 378 379 /* clock.c */ 380 void initrtclock(u_long); 381 void startrtclock(void); 382 void i8254_delay(int); 383 void i8254_microtime(struct timeval *); 384 void i8254_initclocks(void); 385 386 /* cpu.c */ 387 388 void cpu_probe_features(struct cpu_info *); 389 390 /* npx.c */ 391 void npxsave_lwp(struct lwp *, int); 392 void npxsave_cpu(struct cpu_info *, int); 393 394 /* vm_machdep.c */ 395 int kvtop(void *); 396 397 #ifdef MATH_EMULATE 398 /* math_emulate.c */ 399 int math_emulate(struct trapframe *, ksiginfo_t *); 400 #endif 401 402 #ifdef USER_LDT 403 /* sys_machdep.h */ 404 int x86_get_ldt(struct lwp *, void *, register_t *); 405 int x86_set_ldt(struct lwp *, void *, register_t *); 406 #endif 407 408 /* isa_machdep.c */ 409 void isa_defaultirq(void); 410 int isa_nmi(void); 411 412 #ifdef VM86 413 /* vm86.c */ 414 void vm86_gpfault(struct lwp *, int); 415 #endif /* VM86 */ 416 417 /* consinit.c */ 418 void kgdb_port_init(void); 419 420 /* bus_machdep.c */ 421 void x86_bus_space_init(void); 422 void x86_bus_space_mallocok(void); 423 424 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 425 426 /* est.c */ 427 void est_init(int); 428 429 #endif /* _KERNEL */ 430 431 /* 432 * CTL_MACHDEP definitions. 433 */ 434 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 435 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 436 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 437 #define CPU_NKPDE 4 /* int: number of kernel PDEs */ 438 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 439 #define CPU_DISKINFO 6 /* struct disklist *: 440 * disk geometry information */ 441 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 442 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 443 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 444 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 445 #define CPU_TMLR_MODE 11 /* int: longrun mode 446 * 0: minimum frequency 447 * 1: economy 448 * 2: performance 449 * 3: maximum frequency 450 */ 451 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 452 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 453 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 454 #define CPU_MAXID 15 /* number of valid machdep ids */ 455 456 #define CTL_MACHDEP_NAMES { \ 457 { 0, 0 }, \ 458 { "console_device", CTLTYPE_STRUCT }, \ 459 { "biosbasemem", CTLTYPE_INT }, \ 460 { "biosextmem", CTLTYPE_INT }, \ 461 { "nkpde", CTLTYPE_INT }, \ 462 { "booted_kernel", CTLTYPE_STRING }, \ 463 { "diskinfo", CTLTYPE_STRUCT }, \ 464 { "fpu_present", CTLTYPE_INT }, \ 465 { "osfxsr", CTLTYPE_INT }, \ 466 { "sse", CTLTYPE_INT }, \ 467 { "sse2", CTLTYPE_INT }, \ 468 { "tm_longrun_mode", CTLTYPE_INT }, \ 469 { "tm_longrun_frequency", CTLTYPE_INT }, \ 470 { "tm_longrun_voltage", CTLTYPE_INT }, \ 471 { "tm_longrun_percentage", CTLTYPE_INT }, \ 472 } 473 474 /* 475 * Structure for CPU_DISKINFO sysctl call. 476 * XXX this should be somewhere else. 477 */ 478 #define MAX_BIOSDISKS 16 479 480 struct disklist { 481 int dl_nbiosdisks; /* number of bios disks */ 482 struct biosdisk_info { 483 int bi_dev; /* BIOS device # (0x80 ..) */ 484 int bi_cyl; /* cylinders on disk */ 485 int bi_head; /* heads per track */ 486 int bi_sec; /* sectors per track */ 487 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 488 #define BIFLAG_INVALID 0x01 489 #define BIFLAG_EXTINT13 0x02 490 int bi_flags; 491 } dl_biosdisks[MAX_BIOSDISKS]; 492 493 int dl_nnativedisks; /* number of native disks */ 494 struct nativedisk_info { 495 char ni_devname[16]; /* native device name */ 496 int ni_nmatches; /* # of matches w/ BIOS */ 497 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 498 } dl_nativedisks[1]; /* actually longer */ 499 }; 500 #endif /* !_I386_CPU_H_ */ 501
Indexes created Thu Sep 25 16:09:42 GMT 2025