cpu.h revision 1.155
1 /* $NetBSD: cpu.h,v 1.155 2008/01/04 15:55:33 yamt Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _I386_CPU_H_ 38 #define _I386_CPU_H_ 39 40 #ifdef _KERNEL 41 #if defined(_KERNEL_OPT) 42 #include "opt_multiprocessor.h" 43 #include "opt_math_emulate.h" 44 #include "opt_user_ldt.h" 45 #include "opt_vm86.h" 46 #endif 47 48 /* 49 * Definitions unique to i386 cpu support. 50 */ 51 #include <machine/frame.h> 52 #include <machine/segments.h> 53 #include <machine/tss.h> 54 #include <machine/intrdefs.h> 55 #include <x86/cacheinfo.h> 56 #include <x86/via_padlock.h> 57 58 #include <sys/device.h> 59 #include <sys/cpu_data.h> 60 #include <sys/cc_microtime.h> 61 62 #include <lib/libkern/libkern.h> /* offsetof */ 63 64 struct intrsource; 65 struct pmap; 66 67 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 68 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 69 70 /* 71 * I/O bitmap offset beyond TSS's segment limit means no bitmaps. 72 * (i.e. any I/O attempt generates an exception.) 73 */ 74 #define IOMAP_INVALOFF 0xffff 75 76 /* 77 * a bunch of this belongs in cpuvar.h; move it later.. 78 */ 79 80 struct cpu_info { 81 struct device *ci_dev; /* pointer to our device */ 82 struct cpu_info *ci_self; /* self-pointer */ 83 void *ci_tlog_base; /* Trap log base */ 84 int32_t ci_tlog_offset; /* Trap log current offset */ 85 86 /* 87 * Will be accessed by other CPUs. 88 */ 89 struct cpu_info *ci_next; /* next cpu */ 90 struct lwp *ci_curlwp; /* current owner of the processor */ 91 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 92 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 93 int ci_fpsaving; /* save in progress */ 94 cpuid_t ci_cpuid; /* our CPU ID */ 95 int ci_cpumask; /* (1 << CPU ID) */ 96 u_int ci_apicid; /* our APIC ID */ 97 uint8_t ci_initapicid; /* our intitial APIC ID */ 98 uint8_t ci_packageid; 99 uint8_t ci_coreid; 100 uint8_t ci_smtid; 101 struct cpu_data ci_data; /* MI per-cpu data */ 102 struct cc_microtime_state ci_cc;/* cc_microtime state */ 103 104 /* 105 * Private members. 106 */ 107 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 108 struct pmap *ci_pmap; /* current pmap */ 109 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 110 int ci_want_pmapload; /* pmap_load() is needed */ 111 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 112 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 113 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 114 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 115 116 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 117 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 118 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 119 120 /* The following must be aligned for cmpxchg8b. */ 121 struct { 122 uint32_t ipending; 123 int ilevel; 124 } ci_istate __aligned(8); 125 #define ci_ipending ci_istate.ipending 126 #define ci_ilevel ci_istate.ilevel 127 128 int ci_idepth; 129 void * ci_intrstack; 130 uint32_t ci_imask[NIPL]; 131 uint32_t ci_iunmask[NIPL]; 132 133 paddr_t ci_idle_pcb_paddr; /* PA of idle PCB */ 134 uint32_t ci_flags; /* flags; see below */ 135 uint32_t ci_ipis; /* interprocessor interrupts pending */ 136 int sc_apic_version; /* local APIC version */ 137 138 int32_t ci_cpuid_level; 139 uint32_t ci_signature; /* X86 cpuid type */ 140 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 141 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 142 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 143 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 144 uint32_t ci_cpu_class; /* CPU class */ 145 uint32_t ci_brand_id; /* Intel brand id */ 146 uint32_t ci_vendor[4]; /* vendor string */ 147 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 148 uint64_t ci_tsc_freq; /* cpu cycles/second */ 149 volatile uint32_t ci_lapic_counter; 150 151 const struct cpu_functions *ci_func; /* start/stop functions */ 152 void (*cpu_setup)(struct cpu_info *); 153 /* proc-dependant init */ 154 void (*ci_info)(struct cpu_info *); 155 156 int ci_want_resched; 157 struct trapframe *ci_ddb_regs; 158 159 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 160 struct x86_cache_info ci_cinfo[CAI_COUNT]; 161 162 union descriptor *ci_gdt; 163 164 struct i386tss ci_doubleflt_tss; 165 struct i386tss ci_ddbipi_tss; 166 167 char *ci_doubleflt_stack; 168 char *ci_ddbipi_stack; 169 170 struct evcnt ci_ipi_events[X86_NIPI]; 171 172 struct via_padlock ci_vp; /* VIA PadLock private storage */ 173 174 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 175 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 176 int ci_tss_sel; /* TSS selector of this cpu */ 177 178 /* 179 * The following two are actually region_descriptors, 180 * but that would pollute the namespace. 181 */ 182 uint32_t ci_suspend_gdt; 183 uint16_t ci_suspend_gdt_padding; 184 uint32_t ci_suspend_idt; 185 uint16_t ci_suspend_idt_padding; 186 187 uint16_t ci_suspend_tr; 188 uint16_t ci_suspend_ldt; 189 uint16_t ci_suspend_fs; 190 uint16_t ci_suspend_gs; 191 uint32_t ci_suspend_ebx; 192 uint32_t ci_suspend_esi; 193 uint32_t ci_suspend_edi; 194 uint32_t ci_suspend_ebp; 195 uint32_t ci_suspend_esp; 196 uint32_t ci_suspend_efl; 197 uint32_t ci_suspend_cr0; 198 uint32_t ci_suspend_cr2; 199 uint32_t ci_suspend_cr3; 200 uint32_t ci_suspend_cr4; 201 }; 202 203 /* 204 * Processor flag notes: The "primary" CPU has certain MI-defined 205 * roles (mostly relating to hardclock handling); we distinguish 206 * betwen the processor which booted us, and the processor currently 207 * holding the "primary" role just to give us the flexibility later to 208 * change primaries should we be sufficiently twisted. 209 */ 210 211 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 212 #define CPUF_AP 0x0002 /* CPU is an AP */ 213 #define CPUF_SP 0x0004 /* CPU is only processor */ 214 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 215 216 #define CPUF_APIC_CD 0x0010 /* CPU has apic configured */ 217 218 #define CPUF_PRESENT 0x1000 /* CPU is present */ 219 #define CPUF_RUNNING 0x2000 /* CPU is running */ 220 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 221 #define CPUF_GO 0x8000 /* CPU should start running */ 222 223 /* 224 * We statically allocate the CPU info for the primary CPU (or, 225 * the only CPU on uniprocessors), and the primary CPU is the 226 * first CPU on the CPU info list. 227 */ 228 extern struct cpu_info cpu_info_primary; 229 extern struct cpu_info *cpu_info_list; 230 231 #define CPU_INFO_ITERATOR int 232 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 233 ci != NULL; ci = ci->ci_next 234 235 #define X86_MAXPROCS 32 /* because we use a bitmask */ 236 237 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 238 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 239 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 240 241 #if defined(__GNUC__) && defined(_KERNEL) 242 static struct cpu_info *x86_curcpu(void); 243 static lwp_t *x86_curlwp(void); 244 245 __inline static struct cpu_info * __unused 246 x86_curcpu(void) 247 { 248 struct cpu_info *ci; 249 250 __asm volatile("movl %%fs:%1, %0" : 251 "=r" (ci) : 252 "m" 253 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self))); 254 return ci; 255 } 256 257 __inline static lwp_t * __unused 258 x86_curlwp(void) 259 { 260 lwp_t *l; 261 262 __asm volatile("movl %%fs:%1, %0" : 263 "=r" (l) : 264 "m" 265 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp))); 266 return l; 267 } 268 #else /* __GNUC__ && _KERNEL */ 269 /* For non-GCC and LKMs */ 270 struct cpu_info *x86_curcpu(void); 271 lwp_t *x86_curlwp(void); 272 #endif /* __GNUC__ && _KERNEL */ 273 274 #define cpu_number() (curcpu()->ci_cpuid) 275 276 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 277 278 #define aston(l) ((l)->l_md.md_astpending = 1) 279 280 extern struct cpu_info *cpu_info[X86_MAXPROCS]; 281 282 void cpu_boot_secondary_processors(void); 283 void cpu_init_idle_lwps(void); 284 285 extern uint32_t cpus_attached; 286 287 #define curcpu() x86_curcpu() 288 #define curlwp x86_curlwp() 289 #define curpcb (&curlwp->l_addr->u_pcb) 290 291 /* 292 * Arguments to hardclock, softclock and statclock 293 * encapsulate the previous machine state in an opaque 294 * clockframe; for now, use generic intrframe. 295 */ 296 struct clockframe { 297 struct intrframe cf_if; 298 }; 299 300 #define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags) 301 #define CLKF_PC(frame) ((frame)->cf_if.if_eip) 302 #define CLKF_INTR(frame) (curcpu()->ci_idepth > 0) 303 304 /* 305 * This is used during profiling to integrate system time. It can safely 306 * assume that the process is resident. 307 */ 308 #define LWP_PC(l) ((l)->l_md.md_regs->tf_eip) 309 310 /* 311 * Give a profiling tick to the current process when the user profiling 312 * buffer pages are invalid. On the i386, request an ast to send us 313 * through trap(), marking the proc as needing a profiling tick. 314 */ 315 extern void cpu_need_proftick(struct lwp *l); 316 317 /* 318 * Notify the LWP l that it has a signal pending, process as soon as 319 * possible. 320 */ 321 extern void cpu_signotify(struct lwp *); 322 323 /* 324 * We need a machine-independent name for this. 325 */ 326 extern void (*delay_func)(unsigned int); 327 struct timeval; 328 329 #define DELAY(x) (*delay_func)(x) 330 #define delay(x) (*delay_func)(x) 331 332 /* 333 * pull in #defines for kinds of processors 334 */ 335 #include <machine/cputypes.h> 336 337 struct cpu_nocpuid_nameclass { 338 int cpu_vendor; 339 const char *cpu_vendorname; 340 const char *cpu_name; 341 int cpu_class; 342 void (*cpu_setup)(struct cpu_info *); 343 void (*cpu_cacheinfo)(struct cpu_info *); 344 void (*cpu_info)(struct cpu_info *); 345 }; 346 347 348 struct cpu_cpuid_nameclass { 349 const char *cpu_id; 350 int cpu_vendor; 351 const char *cpu_vendorname; 352 struct cpu_cpuid_family { 353 int cpu_class; 354 const char *cpu_models[CPU_MAXMODEL+2]; 355 void (*cpu_setup)(struct cpu_info *); 356 void (*cpu_probe)(struct cpu_info *); 357 void (*cpu_info)(struct cpu_info *); 358 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 359 }; 360 361 extern int biosbasemem; 362 extern int biosextmem; 363 extern unsigned int cpu_feature; 364 extern unsigned int cpu_feature2; 365 extern unsigned int cpu_feature_padlock; 366 extern int cpu; 367 extern int cpu_class; 368 extern char cpu_brand_string[]; 369 extern const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[]; 370 extern const struct cpu_cpuid_nameclass i386_cpuid_cpus[]; 371 372 extern int i386_use_fxsave; 373 extern int i386_has_sse; 374 extern int i386_has_sse2; 375 376 /* machdep.c */ 377 void dumpconf(void); 378 void cpu_reset(void); 379 void i386_proc0_tss_ldt_init(void); 380 381 extern int tmx86_has_longrun; 382 extern u_int crusoe_longrun; 383 extern u_int crusoe_frequency; 384 extern u_int crusoe_voltage; 385 extern u_int crusoe_percentage; 386 extern u_int tmx86_set_longrun_mode(u_int); 387 void tmx86_get_longrun_status_all(void); 388 u_int tmx86_get_longrun_mode(void); 389 void identifycpu(struct cpu_info *); 390 391 /* vm_machdep.c */ 392 void cpu_proc_fork(struct proc *, struct proc *); 393 394 /* locore.s */ 395 struct region_descriptor; 396 void lgdt(struct region_descriptor *); 397 void fillw(short, void *, size_t); 398 399 struct pcb; 400 void savectx(struct pcb *); 401 void lwp_trampoline(void); 402 403 /* clock.c */ 404 void initrtclock(u_long); 405 void startrtclock(void); 406 void i8254_delay(unsigned int); 407 void i8254_microtime(struct timeval *); 408 void i8254_initclocks(void); 409 410 /* cpu.c */ 411 412 void cpu_probe_features(struct cpu_info *); 413 414 /* npx.c */ 415 void npxsave_lwp(struct lwp *, int); 416 void npxsave_cpu(struct cpu_info *, int); 417 418 /* vm_machdep.c */ 419 int kvtop(void *); 420 421 #ifdef MATH_EMULATE 422 /* math_emulate.c */ 423 int math_emulate(struct trapframe *, ksiginfo_t *); 424 #endif 425 426 #ifdef USER_LDT 427 /* sys_machdep.h */ 428 int x86_get_ldt(struct lwp *, void *, register_t *); 429 int x86_set_ldt(struct lwp *, void *, register_t *); 430 #endif 431 432 /* isa_machdep.c */ 433 void isa_defaultirq(void); 434 int isa_nmi(void); 435 436 #ifdef VM86 437 /* vm86.c */ 438 void vm86_gpfault(struct lwp *, int); 439 #endif /* VM86 */ 440 441 /* consinit.c */ 442 void kgdb_port_init(void); 443 444 /* bus_machdep.c */ 445 void x86_bus_space_init(void); 446 void x86_bus_space_mallocok(void); 447 448 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 449 450 #endif /* _KERNEL */ 451 452 /* 453 * CTL_MACHDEP definitions. 454 */ 455 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 456 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 457 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 458 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 459 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 460 #define CPU_DISKINFO 6 /* struct disklist *: 461 * disk geometry information */ 462 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 463 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 464 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 465 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 466 #define CPU_TMLR_MODE 11 /* int: longrun mode 467 * 0: minimum frequency 468 * 1: economy 469 * 2: performance 470 * 3: maximum frequency 471 */ 472 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 473 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 474 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 475 #define CPU_MAXID 15 /* number of valid machdep ids */ 476 477 #define CTL_MACHDEP_NAMES { \ 478 { 0, 0 }, \ 479 { "console_device", CTLTYPE_STRUCT }, \ 480 { "biosbasemem", CTLTYPE_INT }, \ 481 { "biosextmem", CTLTYPE_INT }, \ 482 { "booted_kernel", CTLTYPE_STRING }, \ 483 { "diskinfo", CTLTYPE_STRUCT }, \ 484 { "fpu_present", CTLTYPE_INT }, \ 485 { "osfxsr", CTLTYPE_INT }, \ 486 { "sse", CTLTYPE_INT }, \ 487 { "sse2", CTLTYPE_INT }, \ 488 { "tm_longrun_mode", CTLTYPE_INT }, \ 489 { "tm_longrun_frequency", CTLTYPE_INT }, \ 490 { "tm_longrun_voltage", CTLTYPE_INT }, \ 491 { "tm_longrun_percentage", CTLTYPE_INT }, \ 492 } 493 494 /* 495 * Structure for CPU_DISKINFO sysctl call. 496 * XXX this should be somewhere else. 497 */ 498 #define MAX_BIOSDISKS 16 499 500 struct disklist { 501 int dl_nbiosdisks; /* number of bios disks */ 502 struct biosdisk_info { 503 int bi_dev; /* BIOS device # (0x80 ..) */ 504 int bi_cyl; /* cylinders on disk */ 505 int bi_head; /* heads per track */ 506 int bi_sec; /* sectors per track */ 507 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 508 #define BIFLAG_INVALID 0x01 509 #define BIFLAG_EXTINT13 0x02 510 int bi_flags; 511 } dl_biosdisks[MAX_BIOSDISKS]; 512 513 int dl_nnativedisks; /* number of native disks */ 514 struct nativedisk_info { 515 char ni_devname[16]; /* native device name */ 516 int ni_nmatches; /* # of matches w/ BIOS */ 517 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 518 } dl_nativedisks[1]; /* actually longer */ 519 }; 520 #endif /* !_I386_CPU_H_ */ 521
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