cpu.h revision 1.168
1 /* $NetBSD: cpu.h,v 1.168 2008/04/28 22:47:37 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * William Jolitz. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. Neither the name of the University nor the names of its contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * @(#)cpu.h 5.4 (Berkeley) 5/9/91 35 */ 36 37 #ifndef _I386_CPU_H_ 38 #define _I386_CPU_H_ 39 40 #ifdef _KERNEL 41 #if defined(_KERNEL_OPT) 42 #include "opt_multiprocessor.h" 43 #include "opt_user_ldt.h" 44 #include "opt_vm86.h" 45 #include "opt_xen.h" 46 #endif 47 48 /* 49 * Definitions unique to i386 cpu support. 50 */ 51 #include <machine/frame.h> 52 #include <machine/segments.h> 53 #include <machine/tss.h> 54 #include <machine/intrdefs.h> 55 #include <x86/cacheinfo.h> 56 #include <x86/via_padlock.h> 57 58 #include <sys/device.h> 59 #include <sys/cpu_data.h> 60 #include <sys/cc_microtime.h> 61 62 #include <lib/libkern/libkern.h> /* offsetof */ 63 64 struct intrsource; 65 struct pmap; 66 67 #define NIOPORTS 1024 /* # of ports we allow to be mapped */ 68 #define IOMAPSIZE (NIOPORTS / 8) /* I/O bitmap size in bytes */ 69 70 /* 71 * a bunch of this belongs in cpuvar.h; move it later.. 72 */ 73 74 struct cpu_info { 75 struct device *ci_dev; /* pointer to our device */ 76 struct cpu_info *ci_self; /* self-pointer */ 77 78 #ifdef XEN 79 volatile struct vcpu_info *ci_vcpu; 80 #endif 81 82 void *ci_tlog_base; /* Trap log base */ 83 int32_t ci_tlog_offset; /* Trap log current offset */ 84 85 /* 86 * Will be accessed by other CPUs. 87 */ 88 struct cpu_info *ci_next; /* next cpu */ 89 struct lwp *ci_curlwp; /* current owner of the processor */ 90 int ci_fpused; /* XEN: FPU was used by curlwp */ 91 struct pmap_cpu *ci_pmap_cpu; /* per-CPU pmap data */ 92 struct lwp *ci_fpcurlwp; /* current owner of the FPU */ 93 int ci_fpsaving; /* save in progress */ 94 cpuid_t ci_cpuid; /* our CPU ID */ 95 int ci_cpumask; /* (1 << CPU ID) */ 96 u_int ci_apicid; /* our APIC ID */ 97 uint8_t ci_initapicid; /* our intitial APIC ID */ 98 uint8_t ci_packageid; 99 uint8_t ci_coreid; 100 uint8_t ci_smtid; 101 struct cpu_data ci_data; /* MI per-cpu data */ 102 103 /* 104 * Private members. 105 */ 106 struct cc_microtime_state ci_cc __aligned(64);/* cc_microtime state */ 107 struct evcnt ci_tlb_evcnt; /* tlb shootdown counter */ 108 struct pmap *ci_pmap; /* current pmap */ 109 int ci_need_tlbwait; /* need to wait for TLB invalidations */ 110 int ci_want_pmapload; /* pmap_load() is needed */ 111 volatile int ci_tlbstate; /* one of TLBSTATE_ states. see below */ 112 #define TLBSTATE_VALID 0 /* all user tlbs are valid */ 113 #define TLBSTATE_LAZY 1 /* tlbs are valid but won't be kept uptodate */ 114 #define TLBSTATE_STALE 2 /* we might have stale user tlbs */ 115 116 #ifdef XEN 117 struct iplsource *ci_isources[NIPL]; 118 #else 119 struct intrsource *ci_isources[MAX_INTR_SOURCES]; 120 #endif 121 volatile int ci_mtx_count; /* Negative count of spin mutexes */ 122 volatile int ci_mtx_oldspl; /* Old SPL at this ci_idepth */ 123 124 /* The following must be aligned for cmpxchg8b. */ 125 struct { 126 uint32_t ipending; 127 int ilevel; 128 } ci_istate __aligned(8); 129 #define ci_ipending ci_istate.ipending 130 #define ci_ilevel ci_istate.ilevel 131 132 int ci_idepth; 133 void * ci_intrstack; 134 uint32_t ci_imask[NIPL]; 135 uint32_t ci_iunmask[NIPL]; 136 137 uint32_t ci_flags; /* flags; see below */ 138 uint32_t ci_ipis; /* interprocessor interrupts pending */ 139 int sc_apic_version; /* local APIC version */ 140 141 int32_t ci_cpuid_level; 142 uint32_t ci_signature; /* X86 cpuid type */ 143 uint32_t ci_feature_flags;/* X86 %edx CPUID feature bits */ 144 uint32_t ci_feature2_flags;/* X86 %ecx CPUID feature bits */ 145 uint32_t ci_feature3_flags;/* X86 extended feature bits */ 146 uint32_t ci_padlock_flags;/* VIA PadLock feature bits */ 147 uint32_t ci_cpu_class; /* CPU class */ 148 uint32_t ci_brand_id; /* Intel brand id */ 149 uint32_t ci_vendor[4]; /* vendor string */ 150 uint32_t ci_cpu_serial[3]; /* PIII serial number */ 151 uint64_t ci_tsc_freq; /* cpu cycles/second */ 152 volatile uint32_t ci_lapic_counter; 153 154 const struct cpu_functions *ci_func; /* start/stop functions */ 155 void (*cpu_setup)(struct cpu_info *); 156 /* proc-dependant init */ 157 void (*ci_info)(struct cpu_info *); 158 159 struct trapframe *ci_ddb_regs; 160 161 u_int ci_cflush_lsize; /* CFLUSH insn line size */ 162 struct x86_cache_info ci_cinfo[CAI_COUNT]; 163 164 union descriptor *ci_gdt; 165 166 struct i386tss ci_doubleflt_tss; 167 struct i386tss ci_ddbipi_tss; 168 169 char *ci_doubleflt_stack; 170 char *ci_ddbipi_stack; 171 172 struct evcnt ci_ipi_events[X86_NIPI]; 173 174 struct via_padlock ci_vp; /* VIA PadLock private storage */ 175 176 struct i386tss ci_tss; /* Per-cpu TSS; shared among LWPs */ 177 char ci_iomap[IOMAPSIZE]; /* I/O Bitmap */ 178 int ci_tss_sel; /* TSS selector of this cpu */ 179 180 /* 181 * The following two are actually region_descriptors, 182 * but that would pollute the namespace. 183 */ 184 uint32_t ci_suspend_gdt; 185 uint16_t ci_suspend_gdt_padding; 186 uint32_t ci_suspend_idt; 187 uint16_t ci_suspend_idt_padding; 188 189 uint16_t ci_suspend_tr; 190 uint16_t ci_suspend_ldt; 191 uint16_t ci_suspend_fs; 192 uint16_t ci_suspend_gs; 193 uint32_t ci_suspend_ebx; 194 uint32_t ci_suspend_esi; 195 uint32_t ci_suspend_edi; 196 uint32_t ci_suspend_ebp; 197 uint32_t ci_suspend_esp; 198 uint32_t ci_suspend_efl; 199 uint32_t ci_suspend_cr0; 200 uint32_t ci_suspend_cr2; 201 uint32_t ci_suspend_cr3; 202 uint32_t ci_suspend_cr4; 203 204 /* The following must be in a single cache line. */ 205 int ci_want_resched __aligned(64); 206 int ci_padout __aligned(64); 207 }; 208 209 /* 210 * Processor flag notes: The "primary" CPU has certain MI-defined 211 * roles (mostly relating to hardclock handling); we distinguish 212 * betwen the processor which booted us, and the processor currently 213 * holding the "primary" role just to give us the flexibility later to 214 * change primaries should we be sufficiently twisted. 215 */ 216 217 #define CPUF_BSP 0x0001 /* CPU is the original BSP */ 218 #define CPUF_AP 0x0002 /* CPU is an AP */ 219 #define CPUF_SP 0x0004 /* CPU is only processor */ 220 #define CPUF_PRIMARY 0x0008 /* CPU is active primary processor */ 221 222 #define CPUF_APIC_CD 0x0010 /* CPU has apic configured */ 223 224 #define CPUF_PRESENT 0x1000 /* CPU is present */ 225 #define CPUF_RUNNING 0x2000 /* CPU is running */ 226 #define CPUF_PAUSE 0x4000 /* CPU is paused in DDB */ 227 #define CPUF_GO 0x8000 /* CPU should start running */ 228 229 /* 230 * We statically allocate the CPU info for the primary CPU (or, 231 * the only CPU on uniprocessors), and the primary CPU is the 232 * first CPU on the CPU info list. 233 */ 234 extern struct cpu_info cpu_info_primary; 235 extern struct cpu_info *cpu_info_list; 236 237 #define CPU_INFO_ITERATOR int 238 #define CPU_INFO_FOREACH(cii, ci) cii = 0, ci = cpu_info_list; \ 239 ci != NULL; ci = ci->ci_next 240 241 #define X86_MAXPROCS 32 /* because we use a bitmask */ 242 243 #define CPU_STARTUP(_ci, _target) ((_ci)->ci_func->start(_ci, _target)) 244 #define CPU_STOP(_ci) ((_ci)->ci_func->stop(_ci)) 245 #define CPU_START_CLEANUP(_ci) ((_ci)->ci_func->cleanup(_ci)) 246 247 #if defined(__GNUC__) && !defined(_LKM) 248 static struct cpu_info *x86_curcpu(void); 249 static lwp_t *x86_curlwp(void); 250 251 __inline static struct cpu_info * __unused 252 x86_curcpu(void) 253 { 254 struct cpu_info *ci; 255 256 __asm volatile("movl %%fs:%1, %0" : 257 "=r" (ci) : 258 "m" 259 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_self))); 260 return ci; 261 } 262 263 __inline static lwp_t * __unused 264 x86_curlwp(void) 265 { 266 lwp_t *l; 267 268 __asm volatile("movl %%fs:%1, %0" : 269 "=r" (l) : 270 "m" 271 (*(struct cpu_info * const *)offsetof(struct cpu_info, ci_curlwp))); 272 return l; 273 } 274 __inline static void __unused 275 cpu_set_curpri(int pri) 276 { 277 278 __asm volatile( 279 "movl %1, %%fs:%0" : 280 "=m" (*(struct cpu_info *)offsetof(struct cpu_info, ci_schedstate.spc_curpriority)) : 281 "r" (pri) 282 ); 283 } 284 #else /* __GNUC__ && !_LKM */ 285 /* For non-GCC and LKMs */ 286 struct cpu_info *x86_curcpu(void); 287 lwp_t *x86_curlwp(void); 288 void cpu_set_curpri(int); 289 #endif /* __GNUC__ && !_LKM */ 290 291 #define cpu_number() (curcpu()->ci_cpuid) 292 293 #define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY) 294 295 #define aston(l) ((l)->l_md.md_astpending = 1) 296 297 extern struct cpu_info *cpu_info[X86_MAXPROCS]; 298 299 void cpu_boot_secondary_processors(void); 300 void cpu_init_idle_lwps(void); 301 302 extern uint32_t cpus_attached; 303 #ifndef XEN 304 #define curcpu() x86_curcpu() 305 #define curlwp x86_curlwp() 306 #else 307 /* XXX initgdt() calls pmap_kenter_pa() which calls splvm() before %fs is set */ 308 #define curcpu() (&cpu_info_primary) 309 #define curlwp curcpu()->ci_curlwp 310 #endif 311 #define curpcb (&curlwp->l_addr->u_pcb) 312 313 /* 314 * Arguments to hardclock, softclock and statclock 315 * encapsulate the previous machine state in an opaque 316 * clockframe; for now, use generic intrframe. 317 */ 318 struct clockframe { 319 struct intrframe cf_if; 320 }; 321 322 #define CLKF_USERMODE(frame) USERMODE((frame)->cf_if.if_cs, (frame)->cf_if.if_eflags) 323 #define CLKF_PC(frame) ((frame)->cf_if.if_eip) 324 #define CLKF_INTR(frame) (curcpu()->ci_idepth > 0) 325 326 /* 327 * This is used during profiling to integrate system time. It can safely 328 * assume that the process is resident. 329 */ 330 #define LWP_PC(l) ((l)->l_md.md_regs->tf_eip) 331 332 /* 333 * Give a profiling tick to the current process when the user profiling 334 * buffer pages are invalid. On the i386, request an ast to send us 335 * through trap(), marking the proc as needing a profiling tick. 336 */ 337 extern void cpu_need_proftick(struct lwp *l); 338 339 /* 340 * Notify the LWP l that it has a signal pending, process as soon as 341 * possible. 342 */ 343 extern void cpu_signotify(struct lwp *); 344 345 /* 346 * We need a machine-independent name for this. 347 */ 348 extern void (*delay_func)(unsigned int); 349 struct timeval; 350 351 #define DELAY(x) (*delay_func)(x) 352 #define delay(x) (*delay_func)(x) 353 354 /* 355 * pull in #defines for kinds of processors 356 */ 357 #include <machine/cputypes.h> 358 359 struct cpu_nocpuid_nameclass { 360 int cpu_vendor; 361 const char *cpu_vendorname; 362 const char *cpu_name; 363 int cpu_class; 364 void (*cpu_setup)(struct cpu_info *); 365 void (*cpu_cacheinfo)(struct cpu_info *); 366 void (*cpu_info)(struct cpu_info *); 367 }; 368 369 370 struct cpu_cpuid_nameclass { 371 const char *cpu_id; 372 int cpu_vendor; 373 const char *cpu_vendorname; 374 struct cpu_cpuid_family { 375 int cpu_class; 376 const char *cpu_models[CPU_MAXMODEL+2]; 377 void (*cpu_setup)(struct cpu_info *); 378 void (*cpu_probe)(struct cpu_info *); 379 void (*cpu_info)(struct cpu_info *); 380 } cpu_family[CPU_MAXFAMILY - CPU_MINFAMILY + 1]; 381 }; 382 383 extern int biosbasemem; 384 extern int biosextmem; 385 extern unsigned int cpu_feature; 386 extern unsigned int cpu_feature2; 387 extern unsigned int cpu_feature_padlock; 388 extern int cpu; 389 extern int cpu_class; 390 extern char cpu_brand_string[]; 391 extern const struct cpu_nocpuid_nameclass i386_nocpuid_cpus[]; 392 extern const struct cpu_cpuid_nameclass i386_cpuid_cpus[]; 393 394 extern int i386_use_fxsave; 395 extern int i386_has_sse; 396 extern int i386_has_sse2; 397 398 /* machdep.c */ 399 void dumpconf(void); 400 void cpu_reset(void); 401 void i386_proc0_tss_ldt_init(void); 402 403 /* longrun.c */ 404 u_int tmx86_get_longrun_mode(void); 405 void tmx86_get_longrun_status(u_int *, u_int *, u_int *); 406 void tmx86_init_longrun(void); 407 408 /* identcpu.c */ 409 void identifycpu(struct cpu_info *); 410 411 /* vm_machdep.c */ 412 void cpu_proc_fork(struct proc *, struct proc *); 413 414 /* locore.s */ 415 struct region_descriptor; 416 void lgdt(struct region_descriptor *); 417 #ifdef XEN 418 void lgdt_finish(void); 419 void i386_switch_context(lwp_t *); 420 #endif 421 void fillw(short, void *, size_t); 422 423 struct pcb; 424 void savectx(struct pcb *); 425 void lwp_trampoline(void); 426 #ifdef XEN 427 void startrtclock(void); 428 void xen_delay(unsigned int); 429 void xen_initclocks(void); 430 #else 431 /* clock.c */ 432 void initrtclock(u_long); 433 void startrtclock(void); 434 void i8254_delay(unsigned int); 435 void i8254_microtime(struct timeval *); 436 void i8254_initclocks(void); 437 #endif 438 439 /* cpu.c */ 440 441 void cpu_probe_features(struct cpu_info *); 442 443 /* npx.c */ 444 void npxsave_lwp(struct lwp *, bool); 445 void npxsave_cpu(bool); 446 447 /* vm_machdep.c */ 448 int kvtop(void *); 449 450 #ifdef USER_LDT 451 /* sys_machdep.h */ 452 int x86_get_ldt(struct lwp *, void *, register_t *); 453 int x86_set_ldt(struct lwp *, void *, register_t *); 454 #endif 455 456 /* isa_machdep.c */ 457 void isa_defaultirq(void); 458 int isa_nmi(void); 459 460 #ifdef VM86 461 /* vm86.c */ 462 void vm86_gpfault(struct lwp *, int); 463 #endif /* VM86 */ 464 465 /* consinit.c */ 466 void kgdb_port_init(void); 467 468 /* bus_machdep.c */ 469 void x86_bus_space_init(void); 470 void x86_bus_space_mallocok(void); 471 472 #include <machine/psl.h> /* Must be after struct cpu_info declaration */ 473 474 #endif /* _KERNEL */ 475 476 /* 477 * CTL_MACHDEP definitions. 478 */ 479 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 480 #define CPU_BIOSBASEMEM 2 /* int: bios-reported base mem (K) */ 481 #define CPU_BIOSEXTMEM 3 /* int: bios-reported ext. mem (K) */ 482 /* CPU_NKPDE 4 obsolete: int: number of kernel PDEs */ 483 #define CPU_BOOTED_KERNEL 5 /* string: booted kernel name */ 484 #define CPU_DISKINFO 6 /* struct disklist *: 485 * disk geometry information */ 486 #define CPU_FPU_PRESENT 7 /* int: FPU is present */ 487 #define CPU_OSFXSR 8 /* int: OS uses FXSAVE/FXRSTOR */ 488 #define CPU_SSE 9 /* int: OS/CPU supports SSE */ 489 #define CPU_SSE2 10 /* int: OS/CPU supports SSE2 */ 490 #define CPU_TMLR_MODE 11 /* int: longrun mode 491 * 0: minimum frequency 492 * 1: economy 493 * 2: performance 494 * 3: maximum frequency 495 */ 496 #define CPU_TMLR_FREQUENCY 12 /* int: current frequency */ 497 #define CPU_TMLR_VOLTAGE 13 /* int: curret voltage */ 498 #define CPU_TMLR_PERCENTAGE 14 /* int: current clock percentage */ 499 #define CPU_MAXID 15 /* number of valid machdep ids */ 500 501 /* 502 * Structure for CPU_DISKINFO sysctl call. 503 * XXX this should be somewhere else. 504 */ 505 #define MAX_BIOSDISKS 16 506 507 struct disklist { 508 int dl_nbiosdisks; /* number of bios disks */ 509 struct biosdisk_info { 510 int bi_dev; /* BIOS device # (0x80 ..) */ 511 int bi_cyl; /* cylinders on disk */ 512 int bi_head; /* heads per track */ 513 int bi_sec; /* sectors per track */ 514 uint64_t bi_lbasecs; /* total sec. (iff ext13) */ 515 #define BIFLAG_INVALID 0x01 516 #define BIFLAG_EXTINT13 0x02 517 int bi_flags; 518 } dl_biosdisks[MAX_BIOSDISKS]; 519 520 int dl_nnativedisks; /* number of native disks */ 521 struct nativedisk_info { 522 char ni_devname[16]; /* native device name */ 523 int ni_nmatches; /* # of matches w/ BIOS */ 524 int ni_biosmatches[MAX_BIOSDISKS]; /* indices in dl_biosdisks */ 525 } dl_nativedisks[1]; /* actually longer */ 526 }; 527 #endif /* !_I386_CPU_H_ */ 528
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