intr.h revision 1.12.10.14
1 /* $NetBSD: intr.h,v 1.12.10.14 2001/05/23 03:13:39 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Charles M. Hannum, and by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #ifndef _I386_INTR_H_ 40 #define _I386_INTR_H_ 41 42 /* 43 * Interrupt priority levels. 44 * 45 * There are tty, network and disk drivers that use free() at interrupt 46 * time, so imp > (tty | net | bio). 47 * 48 * Since run queues may be manipulated by both the statclock and tty, 49 * network, and disk drivers, clock > imp. 50 * 51 * IPL_HIGH must block everything that can manipulate a run queue. 52 * 53 * We need serial drivers to run at the absolute highest priority to 54 * avoid overruns, so serial > high. 55 */ 56 #define IPL_NONE 0x00 /* nothing */ 57 #define IPL_SOFTCLOCK 0x50 /* timeouts */ 58 #define IPL_SOFTNET 0x60 /* protocol stacks */ 59 #define IPL_BIO 0x70 /* block I/O */ 60 #define IPL_NET 0x80 /* network */ 61 #define IPL_SOFTSERIAL 0x90 /* serial */ 62 #define IPL_TTY 0xa0 /* terminal */ 63 #define IPL_IMP 0xb0 /* memory allocation */ 64 #define IPL_AUDIO 0xc0 /* audio */ 65 #define IPL_CLOCK 0xd0 /* clock */ 66 #define IPL_HIGH 0xd0 /* everything */ 67 #define IPL_SERIAL 0xe0 /* serial */ 68 #define IPL_IPI 0xe0 /* inter-processor interrupts */ 69 #define NIPL 16 70 71 /* Interrupt sharing types. */ 72 #define IST_NONE 0 /* none */ 73 #define IST_PULSE 1 /* pulsed */ 74 #define IST_EDGE 2 /* edge-triggered */ 75 #define IST_LEVEL 3 /* level-triggered */ 76 77 /* Soft interrupt masks. */ 78 #define SIR_CLOCK 31 79 #define SIR_NET 30 80 #define SIR_SERIAL 29 81 82 /* Hack for CLKF_INTR(). */ 83 #define IPL_TAGINTR 28 84 85 #ifndef _LOCORE 86 87 extern volatile u_int32_t lapic_tpr; 88 volatile u_int32_t ipending; 89 90 int imasks[NIPL]; 91 int iunmask[NIPL]; 92 93 #define CPSHIFT 4 94 #define IMASK(level) imasks[(level)>>CPSHIFT] 95 #define IUNMASK(level) iunmask[(level)>>CPSHIFT] 96 97 extern void Xspllower __P((void)); 98 99 static __inline int splraise __P((int)); 100 static __inline void spllower __P((int)); 101 static __inline void softintr __P((int)); 102 103 /* 104 * Add a mask to cpl, and return the old value of cpl. 105 */ 106 static __inline int 107 splraise(ncpl) 108 register int ncpl; 109 { 110 register int ocpl = lapic_tpr; 111 112 if (ncpl > ocpl) 113 lapic_tpr = ncpl; 114 return (ocpl); 115 } 116 117 /* 118 * Restore a value to cpl (unmasking interrupts). If any unmasked 119 * interrupts are pending, call Xspllower() to process them. 120 */ 121 static __inline void 122 spllower(ncpl) 123 register int ncpl; 124 { 125 register int cmask; 126 127 lapic_tpr = ncpl; 128 cmask = IUNMASK(ncpl); 129 if (ipending & cmask) 130 Xspllower(); 131 } 132 133 /* 134 * Hardware interrupt masks 135 */ 136 #define splbio() splraise(IPL_BIO) 137 #define splnet() splraise(IPL_NET) 138 #define spltty() splraise(IPL_TTY) 139 #define splaudio() splraise(IPL_AUDIO) 140 #define splclock() splraise(IPL_CLOCK) 141 #define splstatclock() splclock() 142 #define splserial() splraise(IPL_SERIAL) 143 #define splipi() splraise(IPL_IPI) 144 145 #define spllpt() spltty() 146 147 #define SPL_ASSERT_ATMOST(x) KDASSERT(lapic_tpr <= (x)) 148 149 /* 150 * Software interrupt masks 151 * 152 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 153 * clock to softclock before it calls softclock(). 154 */ 155 #define spllowersoftclock() spllower(IPL_SOFTCLOCK) 156 157 #define splsoftclock() splraise(IPL_SOFTCLOCK) 158 #define splsoftnet() splraise(IPL_SOFTNET) 159 #define splsoftserial() splraise(IPL_SOFTSERIAL) 160 161 /* 162 * Miscellaneous 163 */ 164 #define splvm() splraise(IPL_IMP) 165 #define splhigh() splraise(IPL_HIGH) 166 #define spl0() spllower(IPL_NONE) 167 #define splsched() splhigh() 168 #define spllock() splraise(IPL_SERIAL) /* XXX XXX XXX XXX */ 169 #define splx(x) spllower(x) 170 171 /* 172 * Software interrupt registration 173 * 174 * We hand-code this to ensure that it's atomic. 175 */ 176 static __inline void 177 softintr(register int sir) 178 { 179 __asm __volatile("orl %1, %0" : "=m"(ipending) : "ir" (1 << sir)); 180 } 181 182 #define setsoftnet() softintr(SIR_NET) 183 184 /* XXX does ipi goo belong here, or elsewhere? */ 185 186 #define I386_IPI_HALT 0x00000001 187 #define I386_IPI_FLUSH_FPU 0x00000002 188 #define I386_IPI_SYNCH_FPU 0x00000004 189 #define I386_IPI_TLB 0x00000008 190 #define I386_IPI_MTRR 0x00000010 191 192 #define I386_NIPI 5 193 194 #ifdef MULTIPROCESSOR 195 struct cpu_info; 196 197 void i386_send_ipi (struct cpu_info *, int); 198 void i386_broadcast_ipi (int); 199 void i386_multicast_ipi (int, int); 200 void i386_ipi_handler (void); 201 #endif 202 203 #endif /* !_LOCORE */ 204 205 /* 206 * Generic software interrupt support. 207 */ 208 209 #define I386_SOFTINTR_SOFTCLOCK 0 210 #define I386_SOFTINTR_SOFTNET 1 211 #define I386_SOFTINTR_SOFTSERIAL 2 212 #define I386_NSOFTINTR 3 213 214 #ifndef _LOCORE 215 #include <sys/queue.h> 216 217 struct i386_soft_intrhand { 218 TAILQ_ENTRY(i386_soft_intrhand) 219 sih_q; 220 struct i386_soft_intr *sih_intrhead; 221 void (*sih_fn)(void *); 222 void *sih_arg; 223 int sih_pending; 224 }; 225 226 struct i386_soft_intr { 227 TAILQ_HEAD(, i386_soft_intrhand) 228 softintr_q; 229 int softintr_ssir; 230 }; 231 232 #define i386_softintr_lock(si, s) \ 233 do { \ 234 (s) = splhigh(); \ 235 } while (/*CONSTCOND*/ 0) 236 237 #define i386_softintr_unlock(si, s) \ 238 do { \ 239 splx((s)); \ 240 } while (/*CONSTCOND*/ 0) 241 242 void *softintr_establish(int, void (*)(void *), void *); 243 void softintr_disestablish(void *); 244 void softintr_init(void); 245 void softintr_dispatch(int); 246 247 #define softintr_schedule(arg) \ 248 do { \ 249 struct i386_soft_intrhand *__sih = (arg); \ 250 struct i386_soft_intr *__si = __sih->sih_intrhead; \ 251 int __s; \ 252 \ 253 i386_softintr_lock(__si, __s); \ 254 if (__sih->sih_pending == 0) { \ 255 TAILQ_INSERT_TAIL(&__si->softintr_q, __sih, sih_q); \ 256 __sih->sih_pending = 1; \ 257 softintr(__si->softintr_ssir); \ 258 } \ 259 i386_softintr_unlock(__si, __s); \ 260 } while (/*CONSTCOND*/ 0) 261 #endif /* _LOCORE */ 262 263 #endif /* !_I386_INTR_H_ */ 264
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