intr.h revision 1.12.10.8 1 /* $NetBSD: intr.h,v 1.12.10.8 2000/09/23 17:30:07 sommerfeld Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _I386_INTR_H_
40 #define _I386_INTR_H_
41
42 /*
43 * Interrupt priority levels.
44 *
45 * There are tty, network and disk drivers that use free() at interrupt
46 * time, so imp > (tty | net | bio).
47 *
48 * Since run queues may be manipulated by both the statclock and tty,
49 * network, and disk drivers, clock > imp.
50 *
51 * IPL_HIGH must block everything that can manipulate a run queue.
52 *
53 * We need serial drivers to run at the absolute highest priority to
54 * avoid overruns, so serial > high.
55 */
56 #define IPL_NONE 0x00 /* nothing */
57 #define IPL_SOFTCLOCK 0x50 /* timeouts */
58 #define IPL_SOFTNET 0x60 /* protocol stacks */
59 #define IPL_BIO 0x70 /* block I/O */
60 #define IPL_NET 0x80 /* network */
61 #define IPL_SOFTSERIAL 0x90 /* serial */
62 #define IPL_TTY 0xa0 /* terminal */
63 #define IPL_IMP 0xb0 /* memory allocation */
64 #define IPL_AUDIO 0xc0 /* audio */
65 #define IPL_CLOCK 0xd0 /* clock */
66 #define IPL_HIGH 0xd0 /* everything */
67 #define IPL_SERIAL 0xe0 /* serial */
68 #define IPL_IPI 0xe0 /* inter-processor interrupts */
69 #define NIPL 16
70
71 /* Interrupt sharing types. */
72 #define IST_NONE 0 /* none */
73 #define IST_PULSE 1 /* pulsed */
74 #define IST_EDGE 2 /* edge-triggered */
75 #define IST_LEVEL 3 /* level-triggered */
76
77 /* Soft interrupt masks. */
78 #define SIR_CLOCK 31
79 #define SIR_NET 30
80 #define SIR_SERIAL 29
81
82 /* Hack for CLKF_INTR(). */
83 #define IPL_TAGINTR 28
84
85 #ifndef _LOCORE
86
87 #ifdef MULTIPROCESSOR
88 #include <machine/i82489reg.h>
89 #include <machine/i82489var.h>
90 #endif
91
92 extern volatile u_int32_t lapic_tpr;
93 volatile u_int32_t ipending;
94
95 int imasks[NIPL];
96 int iunmask[NIPL];
97
98 #define CPSHIFT 4
99 #define IMASK(level) imasks[(level)>>CPSHIFT]
100 #define IUNMASK(level) iunmask[(level)>>CPSHIFT]
101
102 extern void Xspllower __P((void));
103
104 static __inline int splraise __P((int));
105 static __inline void spllower __P((int));
106 static __inline void softintr __P((int, int));
107
108 /*
109 * Add a mask to cpl, and return the old value of cpl.
110 */
111 static __inline int
112 splraise(ncpl)
113 register int ncpl;
114 {
115 register int ocpl = lapic_tpr;
116
117 if (ncpl > ocpl)
118 lapic_tpr = ncpl;
119 return (ocpl);
120 }
121
122 /*
123 * Restore a value to cpl (unmasking interrupts). If any unmasked
124 * interrupts are pending, call Xspllower() to process them.
125 */
126 static __inline void
127 spllower(ncpl)
128 register int ncpl;
129 {
130 register int cmask;
131
132 lapic_tpr = ncpl;
133 cmask = IUNMASK(ncpl);
134 if (ipending & cmask)
135 Xspllower();
136 }
137
138 /*
139 * Hardware interrupt masks
140 */
141 #define splbio() splraise(IPL_BIO)
142 #define splnet() splraise(IPL_NET)
143 #define spltty() splraise(IPL_TTY)
144 #define splaudio() splraise(IPL_AUDIO)
145 #define splclock() splraise(IPL_CLOCK)
146 #define splstatclock() splclock()
147 #define splserial() splraise(IPL_SERIAL)
148 #define spllock() splraise(IPL_SERIAL) /* XXX XXX XXX XXX */
149 #define splsched() splraise(IPL_HIGH)
150 #define splipi() splraise(IPL_IPI)
151
152 #define spllpt() spltty()
153
154 #define SPL_ASSERT_ATMOST(x) KDASSERT(lapic_tpr <= (x))
155
156 /*
157 * Software interrupt masks
158 *
159 * NOTE: splsoftclock() is used by hardclock() to lower the priority from
160 * clock to softclock before it calls softclock().
161 */
162 #define spllowersoftclock() spllower(IPL_SOFTCLOCK)
163
164 #define splsoftclock() splraise(IPL_SOFTCLOCK)
165 #define splsoftnet() splraise(IPL_SOFTNET)
166 #define splsoftserial() splraise(IPL_SOFTSERIAL)
167
168 /*
169 * Miscellaneous
170 */
171 #define splimp() splraise(IPL_IMP)
172 #define splhigh() splraise(IPL_HIGH)
173 #define spl0() spllower(IPL_NONE)
174 #define splx(x) spllower(x)
175
176 /*
177 * Software interrupt registration
178 *
179 * We hand-code this to ensure that it's atomic.
180 */
181 static __inline void
182 softintr(sir, vec)
183 register int sir;
184 register int vec;
185 {
186 __asm __volatile("orl %1, %0" : "=m"(ipending) : "ir" (1 << sir));
187 #ifdef MULTIPROCESSOR
188 i82489_writereg(LAPIC_ICRLO,
189 vec | LAPIC_DLMODE_FIXED | LAPIC_LVL_ASSERT | LAPIC_DEST_SELF);
190 #endif
191 }
192
193 #define setsoftclock() softintr(SIR_CLOCK,IPL_SOFTCLOCK)
194 #define setsoftnet() softintr(SIR_NET,IPL_SOFTNET)
195 #define setsoftserial() softintr(SIR_SERIAL,IPL_SOFTSERIAL)
196
197
198 #define I386_IPI_HALT 0x00000001
199 #define I386_IPI_FLUSH_FPU 0x00000002
200 #define I386_IPI_SYNCH_FPU 0x00000004
201 #define I386_IPI_TLB 0x00000008
202 #define I386_IPI_MTRR 0x00000010
203
204 #define I386_NIPI 5
205
206 #ifdef MULTIPROCESSOR
207 void i386_send_ipi (struct cpu_info *, int);
208 void i386_broadcast_ipi (int);
209 void i386_ipi_handler (void);
210 #endif
211
212 #endif /* !_LOCORE */
213
214 #endif /* !_I386_INTR_H_ */
215