intr.h revision 1.12.12.1 1 /* $NetBSD: intr.h,v 1.12.12.1 2000/06/22 17:00:32 minoura Exp $ */
2
3 /*-
4 * Copyright (c) 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Charles M. Hannum.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. All advertising materials mentioning features or use of this software
19 * must display the following acknowledgement:
20 * This product includes software developed by the NetBSD
21 * Foundation, Inc. and its contributors.
22 * 4. Neither the name of The NetBSD Foundation nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific prior written permission.
25 *
26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
36 * POSSIBILITY OF SUCH DAMAGE.
37 */
38
39 #ifndef _I386_INTR_H_
40 #define _I386_INTR_H_
41
42 /* Interrupt priority `levels'. */
43 #define IPL_NONE 9 /* nothing */
44 #define IPL_SOFTCLOCK 8 /* timeouts */
45 #define IPL_SOFTNET 7 /* protocol stacks */
46 #define IPL_BIO 6 /* block I/O */
47 #define IPL_NET 5 /* network */
48 #define IPL_SOFTSERIAL 4 /* serial */
49 #define IPL_TTY 3 /* terminal */
50 #define IPL_IMP 3 /* memory allocation */
51 #define IPL_AUDIO 2 /* audio */
52 #define IPL_CLOCK 1 /* clock */
53 #define IPL_HIGH 1 /* everything */
54 #define IPL_SERIAL 0 /* serial */
55 #define NIPL 10
56
57 /* Interrupt sharing types. */
58 #define IST_NONE 0 /* none */
59 #define IST_PULSE 1 /* pulsed */
60 #define IST_EDGE 2 /* edge-triggered */
61 #define IST_LEVEL 3 /* level-triggered */
62
63 /* Soft interrupt masks. */
64 #define SIR_CLOCK 31
65 #define SIR_NET 30
66 #define SIR_SERIAL 29
67
68 /* Hack for CLKF_INTR(). */
69 #define IPL_TAGINTR 28
70
71 #ifndef _LOCORE
72
73 volatile int cpl, ipending, astpending;
74 int imask[NIPL];
75
76 extern void Xspllower __P((void));
77
78 static __inline int splraise __P((int));
79 static __inline void spllower __P((int));
80 static __inline void softintr __P((int));
81
82 /*
83 * Add a mask to cpl, and return the old value of cpl.
84 */
85 static __inline int
86 splraise(ncpl)
87 register int ncpl;
88 {
89 register int ocpl = cpl;
90
91 cpl = ocpl | ncpl;
92 return (ocpl);
93 }
94
95 /*
96 * Restore a value to cpl (unmasking interrupts). If any unmasked
97 * interrupts are pending, call Xspllower() to process them.
98 */
99 static __inline void
100 spllower(ncpl)
101 register int ncpl;
102 {
103
104 cpl = ncpl;
105 if (ipending & ~ncpl)
106 Xspllower();
107 }
108
109 /*
110 * Hardware interrupt masks
111 */
112 #define splbio() splraise(imask[IPL_BIO])
113 #define splnet() splraise(imask[IPL_NET])
114 #define spltty() splraise(imask[IPL_TTY])
115 #define splaudio() splraise(imask[IPL_AUDIO])
116 #define splclock() splraise(imask[IPL_CLOCK])
117 #define splstatclock() splclock()
118 #define splserial() splraise(imask[IPL_SERIAL])
119
120 #define spllpt() spltty()
121
122 /*
123 * Software interrupt masks
124 *
125 * NOTE: splsoftclock() is used by hardclock() to lower the priority from
126 * clock to softclock before it calls softclock().
127 */
128 #define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK])
129 #define splsoftclock() splraise(imask[IPL_SOFTCLOCK])
130 #define splsoftnet() splraise(imask[IPL_SOFTNET])
131 #define splsoftserial() splraise(imask[IPL_SOFTSERIAL])
132
133 /*
134 * Miscellaneous
135 */
136 #define splimp() splraise(imask[IPL_IMP])
137 #define splhigh() splraise(imask[IPL_HIGH])
138 #define spl0() spllower(0)
139 #define splx(x) spllower(x)
140
141 /*
142 * Software interrupt registration
143 *
144 * We hand-code this to ensure that it's atomic.
145 */
146 static __inline void
147 softintr(mask)
148 register int mask;
149 {
150 __asm __volatile("orl %1, %0" : "=m"(ipending) : "ir" (1 << mask));
151 }
152
153 #define setsoftast() (astpending = 1)
154 #define setsoftclock() softintr(SIR_CLOCK)
155 #define setsoftnet() softintr(SIR_NET)
156 #define setsoftserial() softintr(SIR_SERIAL)
157
158 #endif /* !_LOCORE */
159
160 #endif /* !_I386_INTR_H_ */
161