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intr.h revision 1.5.8.1 
      1 /*	$NetBSD: intr.h,v 1.5.8.1 1997/03/12 14:34:46 is Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _I386_INTR_H_
     33 #define _I386_INTR_H_
     34 
     35 /* Interrupt priority `levels'. */
     36 #define	IPL_NONE	8	/* nothing */
     37 #define	IPL_SOFTCLOCK	7	/* timeouts */
     38 #define	IPL_SOFTNET	6	/* protocol stacks */
     39 #define	IPL_BIO		5	/* block I/O */
     40 #define	IPL_NET		4	/* network */
     41 #define	IPL_SOFTSERIAL	3	/* serial */
     42 #define	IPL_TTY		2	/* terminal */
     43 #define	IPL_IMP		2	/* memory allocation */
     44 #define	IPL_CLOCK	1	/* clock */
     45 #define	IPL_HIGH	1	/* everything */
     46 #define	IPL_SERIAL	0	/* serial */
     47 #define	NIPL		9
     48 
     49 /* Interrupt sharing types. */
     50 #define	IST_NONE	0	/* none */
     51 #define	IST_PULSE	1	/* pulsed */
     52 #define	IST_EDGE	2	/* edge-triggered */
     53 #define	IST_LEVEL	3	/* level-triggered */
     54 
     55 /* Soft interrupt masks. */
     56 #define	SIR_CLOCK	31
     57 #define	SIR_NET		30
     58 #define	SIR_SERIAL	29
     59 
     60 #ifndef _LOCORE
     61 
     62 volatile int cpl, ipending, astpending;
     63 int imask[NIPL];
     64 
     65 extern void Xspllower __P((void));
     66 
     67 static __inline int splraise __P((int));
     68 static __inline int spllower __P((int));
     69 static __inline void splx __P((int));
     70 static __inline void softintr __P((int));
     71 
     72 /*
     73  * Add a mask to cpl, and return the old value of cpl.
     74  */
     75 static __inline int
     76 splraise(ncpl)
     77 	register int ncpl;
     78 {
     79 	register int ocpl = cpl;
     80 
     81 	cpl = ocpl | ncpl;
     82 	return (ocpl);
     83 }
     84 
     85 /*
     86  * Restore a value to cpl (unmasking interrupts).  If any unmasked
     87  * interrupts are pending, call Xspllower() to process them.
     88  */
     89 static __inline void
     90 splx(ncpl)
     91 	register int ncpl;
     92 {
     93 
     94 	cpl = ncpl;
     95 	if (ipending & ~ncpl)
     96 		Xspllower();
     97 }
     98 
     99 /*
    100  * Same as splx(), but we return the old value of spl, for the
    101  * benefit of some splsoftclock() callers.
    102  */
    103 static __inline int
    104 spllower(ncpl)
    105 	register int ncpl;
    106 {
    107 	register int ocpl = cpl;
    108 
    109 	cpl = ncpl;
    110 	if (ipending & ~ncpl)
    111 		Xspllower();
    112 	return (ocpl);
    113 }
    114 
    115 /*
    116  * Hardware interrupt masks
    117  */
    118 #define	splbio()	splraise(imask[IPL_BIO])
    119 #define	splnet()	splraise(imask[IPL_NET])
    120 #define	spltty()	splraise(imask[IPL_TTY])
    121 #define	splclock()	splraise(imask[IPL_CLOCK])
    122 #define	splimp()	splraise(imask[IPL_IMP])
    123 #define	splserial()	splraise(imask[IPL_SERIAL])
    124 #define	splstatclock()	splclock()
    125 
    126 /*
    127  * Software interrupt masks
    128  *
    129  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    130  * clock to softclock before it calls softclock().
    131  */
    132 #define	splsoftclock()	spllower(imask[IPL_SOFTCLOCK])
    133 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    134 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    135 
    136 /*
    137  * Miscellaneous
    138  */
    139 #define	splhigh()	splraise(imask[IPL_HIGH])
    140 #define	spl0()		spllower(0)
    141 
    142 /*
    143  * Software interrupt registration
    144  *
    145  * We hand-code this to ensure that it's atomic.
    146  */
    147 static __inline void
    148 softintr(mask)
    149 	register int mask;
    150 {
    151 
    152 	__asm __volatile("orl %0,_ipending" : : "ir" (1 << mask));
    153 }
    154 
    155 #define	setsoftast()	(astpending = 1)
    156 #define	setsoftclock()	softintr(SIR_CLOCK)
    157 #define	setsoftnet()	softintr(SIR_NET)
    158 #define	setsoftserial()	softintr(SIR_SERIAL)
    159 
    160 #endif /* !_LOCORE */
    161 
    162 #endif /* !_I386_INTR_H_ */
    163