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intr.h revision 1.8 
      1 /*	$NetBSD: intr.h,v 1.8 1998/07/18 21:27:27 is Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1996, 1997 Charles M. Hannum.  All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by Charles M. Hannum.
     17  * 4. The name of the author may not be used to endorse or promote products
     18  *    derived from this software without specific prior written permission.
     19  *
     20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     21  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     22  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     23  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     26  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     27  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _I386_INTR_H_
     33 #define _I386_INTR_H_
     34 
     35 /* Interrupt priority `levels'. */
     36 #define	IPL_NONE	9	/* nothing */
     37 #define	IPL_SOFTCLOCK	8	/* timeouts */
     38 #define	IPL_SOFTNET	7	/* protocol stacks */
     39 #define	IPL_BIO		6	/* block I/O */
     40 #define	IPL_NET		5	/* network */
     41 #define	IPL_SOFTSERIAL	4	/* serial */
     42 #define	IPL_TTY		3	/* terminal */
     43 #define	IPL_IMP		3	/* memory allocation */
     44 #define	IPL_AUDIO	2	/* audio */
     45 #define	IPL_CLOCK	1	/* clock */
     46 #define	IPL_HIGH	1	/* everything */
     47 #define	IPL_SERIAL	0	/* serial */
     48 #define	NIPL		10
     49 
     50 /* Interrupt sharing types. */
     51 #define	IST_NONE	0	/* none */
     52 #define	IST_PULSE	1	/* pulsed */
     53 #define	IST_EDGE	2	/* edge-triggered */
     54 #define	IST_LEVEL	3	/* level-triggered */
     55 
     56 /* Soft interrupt masks. */
     57 #define	SIR_CLOCK	31
     58 #define	SIR_NET		30
     59 #define	SIR_SERIAL	29
     60 
     61 #ifndef _LOCORE
     62 
     63 volatile int cpl, ipending, astpending;
     64 int imask[NIPL];
     65 
     66 extern void Xspllower __P((void));
     67 
     68 static __inline int splraise __P((int));
     69 static __inline int spllower __P((int));
     70 static __inline void splx __P((int));
     71 static __inline void softintr __P((int));
     72 
     73 /*
     74  * Add a mask to cpl, and return the old value of cpl.
     75  */
     76 static __inline int
     77 splraise(ncpl)
     78 	register int ncpl;
     79 {
     80 	register int ocpl = cpl;
     81 
     82 	cpl = ocpl | ncpl;
     83 	return (ocpl);
     84 }
     85 
     86 /*
     87  * Restore a value to cpl (unmasking interrupts).  If any unmasked
     88  * interrupts are pending, call Xspllower() to process them.
     89  */
     90 static __inline void
     91 splx(ncpl)
     92 	register int ncpl;
     93 {
     94 
     95 	cpl = ncpl;
     96 	if (ipending & ~ncpl)
     97 		Xspllower();
     98 }
     99 
    100 /*
    101  * Same as splx(), but we return the old value of spl, for the
    102  * benefit of some splsoftclock() callers.
    103  */
    104 static __inline int
    105 spllower(ncpl)
    106 	register int ncpl;
    107 {
    108 	register int ocpl = cpl;
    109 
    110 	cpl = ncpl;
    111 	if (ipending & ~ncpl)
    112 		Xspllower();
    113 	return (ocpl);
    114 }
    115 
    116 /*
    117  * Hardware interrupt masks
    118  */
    119 #define	splbio()	splraise(imask[IPL_BIO])
    120 #define	splnet()	splraise(imask[IPL_NET])
    121 #define	spltty()	splraise(imask[IPL_TTY])
    122 #define	splaudio()	splraise(imask[IPL_AUDIO])
    123 #define	splclock()	splraise(imask[IPL_CLOCK])
    124 #define	splstatclock()	splclock()
    125 #define	splserial()	splraise(imask[IPL_SERIAL])
    126 
    127 #define spllpt()	spltty()
    128 
    129 /*
    130  * Software interrupt masks
    131  *
    132  * NOTE: splsoftclock() is used by hardclock() to lower the priority from
    133  * clock to softclock before it calls softclock().
    134  */
    135 #define	splsoftclock()	spllower(imask[IPL_SOFTCLOCK])
    136 #define	splsoftnet()	splraise(imask[IPL_SOFTNET])
    137 #define	splsoftserial()	splraise(imask[IPL_SOFTSERIAL])
    138 
    139 /*
    140  * Miscellaneous
    141  */
    142 #define	splimp()	splraise(imask[IPL_IMP])
    143 #define	splhigh()	splraise(imask[IPL_HIGH])
    144 #define	spl0()		spllower(0)
    145 
    146 /*
    147  * Software interrupt registration
    148  *
    149  * We hand-code this to ensure that it's atomic.
    150  */
    151 static __inline void
    152 softintr(mask)
    153 	register int mask;
    154 {
    155 
    156 	__asm __volatile("orl %0,_ipending" : : "ir" (1 << mask));
    157 }
    158 
    159 #define	setsoftast()	(astpending = 1)
    160 #define	setsoftclock()	softintr(SIR_CLOCK)
    161 #define	setsoftnet()	softintr(SIR_NET)
    162 #define	setsoftserial()	softintr(SIR_SERIAL)
    163 
    164 #endif /* !_LOCORE */
    165 
    166 #endif /* !_I386_INTR_H_ */
    167