pmap.h revision 1.90.2.2 1 /* $NetBSD: pmap.h,v 1.90.2.2 2007/09/24 10:56:49 yamt Exp $ */
2
3 /*
4 *
5 * Copyright (c) 1997 Charles D. Cranor and Washington University.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgment:
18 * This product includes software developed by Charles D. Cranor and
19 * Washington University.
20 * 4. The name of the author may not be used to endorse or promote products
21 * derived from this software without specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35 /*
36 * Copyright (c) 2001 Wasabi Systems, Inc.
37 * All rights reserved.
38 *
39 * Written by Frank van der Linden for Wasabi Systems, Inc.
40 *
41 * Redistribution and use in source and binary forms, with or without
42 * modification, are permitted provided that the following conditions
43 * are met:
44 * 1. Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * 2. Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in the
48 * documentation and/or other materials provided with the distribution.
49 * 3. All advertising materials mentioning features or use of this software
50 * must display the following acknowledgement:
51 * This product includes software developed for the NetBSD Project by
52 * Wasabi Systems, Inc.
53 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
54 * or promote products derived from this software without specific prior
55 * written permission.
56 *
57 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
58 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
59 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
60 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
61 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
62 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
63 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
64 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
65 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
66 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
67 * POSSIBILITY OF SUCH DAMAGE.
68 */
69
70 /*
71 * pmap.h: see pmap.c for the history of this pmap module.
72 */
73
74 #ifndef _I386_PMAP_H_
75 #define _I386_PMAP_H_
76
77 #if defined(_KERNEL_OPT)
78 #include "opt_user_ldt.h"
79 #include "opt_largepages.h"
80 #endif
81
82 #include <machine/cpufunc.h>
83 #include <machine/pte.h>
84 #include <machine/segments.h>
85 #include <machine/atomic.h>
86
87 #include <uvm/uvm_object.h>
88
89 /*
90 * see pte.h for a description of i386 MMU terminology and hardware
91 * interface.
92 *
93 * a pmap describes a processes' 4GB virtual address space. this
94 * virtual address space can be broken up into 1024 4MB regions which
95 * are described by PDEs in the PDP. the PDEs are defined as follows:
96 *
97 * (ranges are inclusive -> exclusive, just like vm_map_entry start/end)
98 * (the following assumes that KERNBASE is 0xc0000000)
99 *
100 * PDE#s VA range usage
101 * 0->766 0x0 -> 0xbfc00000 user address space
102 * 767 0xbfc00000-> recursive mapping of PDP (used for
103 * 0xc0000000 linear mapping of PTPs)
104 * 768->1023 0xc0000000-> kernel address space (constant
105 * 0xffc00000 across all pmap's/processes)
106 * 1023 0xffc00000-> "alternate" recursive PDP mapping
107 * <end> (for other pmaps)
108 *
109 *
110 * note: a recursive PDP mapping provides a way to map all the PTEs for
111 * a 4GB address space into a linear chunk of virtual memory. in other
112 * words, the PTE for page 0 is the first int mapped into the 4MB recursive
113 * area. the PTE for page 1 is the second int. the very last int in the
114 * 4MB range is the PTE that maps VA 0xfffff000 (the last page in a 4GB
115 * address).
116 *
117 * all pmap's PD's must have the same values in slots 768->1023 so that
118 * the kernel is always mapped in every process. these values are loaded
119 * into the PD at pmap creation time.
120 *
121 * at any one time only one pmap can be active on a processor. this is
122 * the pmap whose PDP is pointed to by processor register %cr3. this pmap
123 * will have all its PTEs mapped into memory at the recursive mapping
124 * point (slot #767 as show above). when the pmap code wants to find the
125 * PTE for a virtual address, all it has to do is the following:
126 *
127 * address of PTE = (767 * 4MB) + (VA / PAGE_SIZE) * sizeof(pt_entry_t)
128 * = 0xbfc00000 + (VA / 4096) * 4
129 *
130 * what happens if the pmap layer is asked to perform an operation
131 * on a pmap that is not the one which is currently active? in that
132 * case we take the PA of the PDP of non-active pmap and put it in
133 * slot 1023 of the active pmap. this causes the non-active pmap's
134 * PTEs to get mapped in the final 4MB of the 4GB address space
135 * (e.g. starting at 0xffc00000).
136 *
137 * the following figure shows the effects of the recursive PDP mapping:
138 *
139 * PDP (%cr3)
140 * +----+
141 * | 0| -> PTP#0 that maps VA 0x0 -> 0x400000
142 * | |
143 * | |
144 * | 767| -> points back to PDP (%cr3) mapping VA 0xbfc00000 -> 0xc0000000
145 * | 768| -> first kernel PTP (maps 0xc0000000 -> 0xc0400000)
146 * | |
147 * |1023| -> points to alternate pmap's PDP (maps 0xffc00000 -> end)
148 * +----+
149 *
150 * note that the PDE#767 VA (0xbfc00000) is defined as "PTE_BASE"
151 * note that the PDE#1023 VA (0xffc00000) is defined as "APTE_BASE"
152 *
153 * starting at VA 0xbfc00000 the current active PDP (%cr3) acts as a
154 * PTP:
155 *
156 * PTP#767 == PDP(%cr3) => maps VA 0xbfc00000 -> 0xc0000000
157 * +----+
158 * | 0| -> maps the contents of PTP#0 at VA 0xbfc00000->0xbfc01000
159 * | |
160 * | |
161 * | 767| -> maps contents of PTP#767 (the PDP) at VA 0xbfeff000
162 * | 768| -> maps contents of first kernel PTP
163 * | |
164 * |1023|
165 * +----+
166 *
167 * note that mapping of the PDP at PTP#767's VA (0xbfeff000) is
168 * defined as "PDP_BASE".... within that mapping there are two
169 * defines:
170 * "PDP_PDE" (0xbfeffbfc) is the VA of the PDE in the PDP
171 * which points back to itself.
172 * "APDP_PDE" (0xbfeffffc) is the VA of the PDE in the PDP which
173 * establishes the recursive mapping of the alternate pmap.
174 * to set the alternate PDP, one just has to put the correct
175 * PA info in *APDP_PDE.
176 *
177 * note that in the APTE_BASE space, the APDP appears at VA
178 * "APDP_BASE" (0xfffff000).
179 */
180 /* XXX MP should we allocate one APDP_PDE per processor?? */
181
182 /*
183 * Mask to get rid of the sign-extended part of addresses.
184 */
185 #define VA_SIGN_MASK 0
186 #define VA_SIGN_NEG(va) ((va) | VA_SIGN_MASK)
187 /*
188 * XXXfvdl this one's not right.
189 */
190 #define VA_SIGN_POS(va) ((va) & ~VA_SIGN_MASK)
191
192 /*
193 * the following defines identify the slots used as described above.
194 */
195
196 #define L2_SLOT_PTE (KERNBASE/NBPD_L2-1) /* 767: for recursive PDP map */
197 #define L2_SLOT_KERN (KERNBASE/NBPD_L2) /* 768: start of kernel space */
198 #define L2_SLOT_KERNBASE L2_SLOT_KERN
199 #define L2_SLOT_APTE 1023 /* 1023: alternative recursive slot */
200
201 #define PDIR_SLOT_KERN L2_SLOT_KERN
202 #define PDIR_SLOT_PTE L2_SLOT_PTE
203 #define PDIR_SLOT_APTE L2_SLOT_APTE
204
205 /*
206 * the following defines give the virtual addresses of various MMU
207 * data structures:
208 * PTE_BASE and APTE_BASE: the base VA of the linear PTE mappings
209 * PDP_BASE and APDP_BASE: the base VA of the recursive mapping of the PDP
210 * PDP_PDE and APDP_PDE: the VA of the PDE that points back to the PDP/APDP
211 */
212
213 #define PTE_BASE ((pt_entry_t *) (L2_SLOT_PTE * NBPD_L2))
214 #define APTE_BASE ((pt_entry_t *) (VA_SIGN_NEG((L2_SLOT_APTE * NBPD_L2))))
215
216 #define L1_BASE PTE_BASE
217 #define AL1_BASE APTE_BASE
218
219 #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L2_SLOT_PTE * NBPD_L1))
220
221 #define AL2_BASE ((pd_entry_t *)((char *)AL1_BASE + L2_SLOT_PTE * NBPD_L1))
222
223 #define PDP_PDE (L2_BASE + PDIR_SLOT_PTE)
224 #define APDP_PDE (L2_BASE + PDIR_SLOT_APTE)
225
226 #define PDP_BASE L2_BASE
227 #define APDP_BASE AL2_BASE
228
229 /* largest value (-1 for APTP space) */
230 #define NKL2_MAX_ENTRIES (NTOPLEVEL_PDES - (KERNBASE/NBPD_L2) - 1)
231 #define NKL1_MAX_ENTRIES (unsigned long)(NKL2_MAX_ENTRIES * NPDPG)
232
233 #define NKL2_KIMG_ENTRIES 0 /* XXX unused */
234
235 #define NKL2_START_ENTRIES 0 /* XXX computed on runtime */
236 #define NKL1_START_ENTRIES 0 /* XXX unused */
237
238 #define NTOPLEVEL_PDES (PAGE_SIZE / (sizeof (pd_entry_t)))
239
240 #define NPDPG (PAGE_SIZE / sizeof (pd_entry_t))
241
242 #define ptei(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
243
244 /*
245 * pl*_pi: index in the ptp page for a pde mapping a VA.
246 * (pl*_i below is the index in the virtual array of all pdes per level)
247 */
248 #define pl1_pi(VA) (((VA_SIGN_POS(VA)) & L1_MASK) >> L1_SHIFT)
249 #define pl2_pi(VA) (((VA_SIGN_POS(VA)) & L2_MASK) >> L2_SHIFT)
250 #define pl3_pi(VA) (((VA_SIGN_POS(VA)) & L3_MASK) >> L3_SHIFT)
251 #define pl4_pi(VA) (((VA_SIGN_POS(VA)) & L4_MASK) >> L4_SHIFT)
252
253 /*
254 * pl*_i: generate index into pde/pte arrays in virtual space
255 */
256 #define pl1_i(VA) (((VA_SIGN_POS(VA)) & L1_FRAME) >> L1_SHIFT)
257 #define pl2_i(VA) (((VA_SIGN_POS(VA)) & L2_FRAME) >> L2_SHIFT)
258 #define pl3_i(VA) (((VA_SIGN_POS(VA)) & L3_FRAME) >> L3_SHIFT)
259 #define pl4_i(VA) (((VA_SIGN_POS(VA)) & L4_FRAME) >> L4_SHIFT)
260 #define pl_i(va, lvl) \
261 (((VA_SIGN_POS(va)) & ptp_masks[(lvl)-1]) >> ptp_shifts[(lvl)-1])
262
263 #define PTP_MASK_INITIALIZER { L1_FRAME, L2_FRAME }
264 #define PTP_SHIFT_INITIALIZER { L1_SHIFT, L2_SHIFT }
265 #define NKPTP_INITIALIZER { NKL1_START_ENTRIES, NKL2_START_ENTRIES }
266 #define NKPTPMAX_INITIALIZER { NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES }
267 #define NBPD_INITIALIZER { NBPD_L1, NBPD_L2 }
268 #define PDES_INITIALIZER { L2_BASE }
269 #define APDES_INITIALIZER { AL2_BASE }
270
271 /*
272 * PTP macros:
273 * a PTP's index is the PD index of the PDE that points to it
274 * a PTP's offset is the byte-offset in the PTE space that this PTP is at
275 * a PTP's VA is the first VA mapped by that PTP
276 */
277
278 #define ptp_va2o(va, lvl) (pl_i(va, (lvl)+1) * PAGE_SIZE)
279
280 #define PTP_LEVELS 2
281
282 /*
283 * PG_AVAIL usage: we make use of the ignored bits of the PTE
284 */
285
286 #define PG_W PG_AVAIL1 /* "wired" mapping */
287 #define PG_PVLIST PG_AVAIL2 /* mapping has entry on pvlist */
288 #define PG_X PG_AVAIL3 /* executable mapping */
289
290 /*
291 * Number of PTE's per cache line. 4 byte pte, 32-byte cache line
292 * Used to avoid false sharing of cache lines.
293 */
294 #define NPTECL 8
295
296 #ifdef _KERNEL
297 /*
298 * pmap data structures: see pmap.c for details of locking.
299 */
300
301 struct pmap;
302 typedef struct pmap *pmap_t;
303
304 /*
305 * we maintain a list of all non-kernel pmaps
306 */
307
308 LIST_HEAD(pmap_head, pmap); /* struct pmap_head: head of a pmap list */
309
310 /*
311 * the pmap structure
312 *
313 * note that the pm_obj contains the simple_lock, the reference count,
314 * page list, and number of PTPs within the pmap.
315 *
316 * XXX If we ever support processor numbers higher than 31, we'll have
317 * XXX to rethink the CPU mask.
318 */
319
320 struct pmap {
321 struct uvm_object pm_obj[PTP_LEVELS-1]; /* objects for lvl >= 1) */
322 #define pm_lock pm_obj[0].vmobjlock
323 #define pm_obj_l1 pm_obj[0]
324 #define pm_obj_l2 pm_obj[1]
325 #define pm_obj_l3 pm_obj[2]
326 LIST_ENTRY(pmap) pm_list; /* list (lck by pm_list lock) */
327 pd_entry_t *pm_pdir; /* VA of PD (lck by object lock) */
328 paddr_t pm_pdirpa; /* PA of PD (read-only after create) */
329 struct vm_page *pm_ptphint[PTP_LEVELS-1];
330 /* pointer to a PTP in our pmap */
331 struct pmap_statistics pm_stats; /* pmap stats (lck by object lock) */
332
333 vaddr_t pm_hiexec; /* highest executable mapping */
334 int pm_flags; /* see below */
335
336 union descriptor *pm_ldt; /* user-set LDT */
337 int pm_ldt_len; /* number of LDT entries */
338 int pm_ldt_sel; /* LDT selector */
339 uint32_t pm_cpus; /* mask of CPUs using pmap */
340 uint32_t pm_kernel_cpus; /* mask of CPUs using kernel part
341 of pmap */
342 };
343
344 /* pm_flags */
345 #define PMF_USER_LDT 0x01 /* pmap has user-set LDT */
346
347 /*
348 * for each managed physical page we maintain a list of <PMAP,VA>'s
349 * which it is mapped at. the list is headed by a pv_head structure.
350 * there is one pv_head per managed phys page (allocated at boot time).
351 * the pv_head structure points to a list of pv_entry structures (each
352 * describes one mapping).
353 */
354
355 struct pv_entry { /* locked by its list's pvh_lock */
356 SPLAY_ENTRY(pv_entry) pv_node; /* splay-tree node */
357 struct pmap *pv_pmap; /* the pmap */
358 vaddr_t pv_va; /* the virtual address */
359 struct vm_page *pv_ptp; /* the vm_page of the PTP */
360 struct pmap_cpu *pv_alloc_cpu; /* CPU allocated from */
361 };
362
363 /*
364 * pv_entrys are dynamically allocated in chunks from a single page.
365 * we keep track of how many pv_entrys are in use for each page and
366 * we can free pv_entry pages if needed. there is one lock for the
367 * entire allocation system.
368 */
369
370 struct pv_page_info {
371 TAILQ_ENTRY(pv_page) pvpi_list;
372 struct pv_entry *pvpi_pvfree;
373 int pvpi_nfree;
374 };
375
376 /*
377 * number of pv_entry's in a pv_page
378 * (note: won't work on systems where NPBG isn't a constant)
379 */
380
381 #define PVE_PER_PVPAGE ((PAGE_SIZE - sizeof(struct pv_page_info)) / \
382 sizeof(struct pv_entry))
383
384 /*
385 * a pv_page: where pv_entrys are allocated from
386 */
387
388 struct pv_page {
389 struct pv_page_info pvinfo;
390 struct pv_entry pvents[PVE_PER_PVPAGE];
391 };
392
393 /*
394 * global kernel variables
395 */
396
397 /* PDPpaddr: is the physical address of the kernel's PDP */
398 extern u_long PDPpaddr;
399
400 extern struct pmap kernel_pmap_store; /* kernel pmap */
401 extern int nkpde; /* current # of PDEs for kernel */
402 extern int pmap_pg_g; /* do we support PG_G? */
403 extern long nkptp[PTP_LEVELS];
404
405 /*
406 * macros
407 */
408
409 #define pmap_kernel() (&kernel_pmap_store)
410 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
411 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
412
413 #define pmap_clear_modify(pg) pmap_clear_attrs(pg, PG_M)
414 #define pmap_clear_reference(pg) pmap_clear_attrs(pg, PG_U)
415 #define pmap_copy(DP,SP,D,L,S)
416 #define pmap_is_modified(pg) pmap_test_attrs(pg, PG_M)
417 #define pmap_is_referenced(pg) pmap_test_attrs(pg, PG_U)
418 #define pmap_move(DP,SP,D,L,S)
419 #define pmap_phys_address(ppn) x86_ptob(ppn)
420 #define pmap_valid_entry(E) ((E) & PG_V) /* is PDE or PTE valid? */
421
422
423 /*
424 * prototypes
425 */
426
427 void pmap_activate(struct lwp *);
428 void pmap_bootstrap(vaddr_t);
429 bool pmap_clear_attrs(struct vm_page *, unsigned);
430 void pmap_deactivate(struct lwp *);
431 void pmap_page_remove (struct vm_page *);
432 void pmap_remove(struct pmap *, vaddr_t, vaddr_t);
433 bool pmap_test_attrs(struct vm_page *, unsigned);
434 void pmap_write_protect(struct pmap *, vaddr_t, vaddr_t, vm_prot_t);
435 int pmap_exec_fixup(struct vm_map *, struct trapframe *,
436 struct pcb *);
437 void pmap_load(void);
438
439 vaddr_t reserve_dumppages(vaddr_t); /* XXX: not a pmap fn */
440
441 void pmap_tlb_shootdown(pmap_t, vaddr_t, vaddr_t, pt_entry_t);
442 void pmap_tlb_shootwait(void);
443
444 #define PMAP_GROWKERNEL /* turn on pmap_growkernel interface */
445
446 /*
447 * Do idle page zero'ing uncached to avoid polluting the cache.
448 */
449 bool pmap_pageidlezero(paddr_t);
450 #define PMAP_PAGEIDLEZERO(pa) pmap_pageidlezero((pa))
451
452 /*
453 * inline functions
454 */
455
456 /*ARGSUSED*/
457 static __inline void
458 pmap_remove_all(struct pmap *pmap)
459 {
460 /* Nothing. */
461 }
462
463 /*
464 * pmap_update_pg: flush one page from the TLB (or flush the whole thing
465 * if hardware doesn't support one-page flushing)
466 */
467
468 __inline static void __attribute__((__unused__))
469 pmap_update_pg(vaddr_t va)
470 {
471 #if defined(I386_CPU)
472 if (cpu_class == CPUCLASS_386)
473 tlbflush();
474 else
475 #endif
476 invlpg((u_int) va);
477 }
478
479 /*
480 * pmap_update_2pg: flush two pages from the TLB
481 */
482
483 __inline static void __attribute__((__unused__))
484 pmap_update_2pg(vaddr_t va, vaddr_t vb)
485 {
486 #if defined(I386_CPU)
487 if (cpu_class == CPUCLASS_386)
488 tlbflush();
489 else
490 #endif
491 {
492 invlpg((u_int) va);
493 invlpg((u_int) vb);
494 }
495 }
496
497 /*
498 * pmap_page_protect: change the protection of all recorded mappings
499 * of a managed page
500 *
501 * => this function is a frontend for pmap_page_remove/pmap_clear_attrs
502 * => we only have to worry about making the page more protected.
503 * unprotecting a page is done on-demand at fault time.
504 */
505
506 __inline static void __attribute__((__unused__))
507 pmap_page_protect(struct vm_page *pg, vm_prot_t prot)
508 {
509 if ((prot & VM_PROT_WRITE) == 0) {
510 if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
511 (void) pmap_clear_attrs(pg, PG_RW);
512 } else {
513 pmap_page_remove(pg);
514 }
515 }
516 }
517
518 /*
519 * pmap_protect: change the protection of pages in a pmap
520 *
521 * => this function is a frontend for pmap_remove/pmap_write_protect
522 * => we only have to worry about making the page more protected.
523 * unprotecting a page is done on-demand at fault time.
524 */
525
526 __inline static void __attribute__((__unused__))
527 pmap_protect(struct pmap *pmap, vaddr_t sva, vaddr_t eva, vm_prot_t prot)
528 {
529 if ((prot & VM_PROT_WRITE) == 0) {
530 if (prot & (VM_PROT_READ|VM_PROT_EXECUTE)) {
531 pmap_write_protect(pmap, sva, eva, prot);
532 } else {
533 pmap_remove(pmap, sva, eva);
534 }
535 }
536 }
537
538 /*
539 * various address inlines
540 *
541 * vtopte: return a pointer to the PTE mapping a VA, works only for
542 * user and PT addresses
543 *
544 * kvtopte: return a pointer to the PTE mapping a kernel VA
545 */
546
547 #include <lib/libkern/libkern.h>
548
549 static __inline pt_entry_t * __attribute__((__unused__))
550 vtopte(vaddr_t va)
551 {
552
553 KASSERT(va < (L2_SLOT_KERN * NBPD_L2));
554
555 return (PTE_BASE + pl1_i(va));
556 }
557
558 static __inline pt_entry_t * __attribute__((__unused__))
559 kvtopte(vaddr_t va)
560 {
561
562 KASSERT(va >= (L2_SLOT_KERN * NBPD_L2));
563
564 #ifdef LARGEPAGES
565 {
566 pd_entry_t *pde;
567
568 pde = L2_BASE + pl2_i(va);
569 if (*pde & PG_PS)
570 return ((pt_entry_t *)pde);
571 }
572 #endif
573
574 return (PTE_BASE + pl1_i(va));
575 }
576
577 #define pmap_pte_set(p, n) x86_atomic_testset_ul(p, n)
578 #define pmap_pte_setbits(p, b) x86_atomic_setbits_l(p, b)
579 #define pmap_pte_clearbits(p, b) x86_atomic_clearbits_l(p, b)
580 #define pmap_cpu_has_pg_n() (cpu_class != CPUCLASS_386)
581 #define pmap_cpu_has_invlpg() (cpu_class != CPUCLASS_386)
582
583 paddr_t vtophys(vaddr_t);
584 vaddr_t pmap_map(vaddr_t, paddr_t, paddr_t, vm_prot_t);
585 void pmap_ldt_cleanup(struct lwp *);
586 void pmap_cpu_init_early(struct cpu_info *);
587 void pmap_cpu_init_late(struct cpu_info *);
588 void sse2_zero_page(void *);
589 void sse2_copy_page(void *, void *);
590
591 /*
592 * Hooks for the pool allocator.
593 */
594 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
595
596 /*
597 * TLB shootdown mailbox.
598 */
599
600 struct pmap_mbox {
601 volatile void *mb_pointer;
602 volatile uintptr_t mb_addr1;
603 volatile uintptr_t mb_addr2;
604 volatile uintptr_t mb_head;
605 volatile uintptr_t mb_tail;
606 volatile uintptr_t mb_global;
607 };
608
609 #endif /* _KERNEL */
610 #endif /* _I386_PMAP_H_ */
611