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pmap.h revision 1.98
      1 /*	$NetBSD: pmap.h,v 1.98 2008/01/11 20:00:15 bouyer Exp $	*/
      2 
      3 /*
      4  *
      5  * Copyright (c) 1997 Charles D. Cranor and Washington University.
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgment:
     18  *      This product includes software developed by Charles D. Cranor and
     19  *      Washington University.
     20  * 4. The name of the author may not be used to endorse or promote products
     21  *    derived from this software without specific prior written permission.
     22  *
     23  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     24  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     25  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     26  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     29  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     30  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     33  */
     34 
     35 /*
     36  * Copyright (c) 2001 Wasabi Systems, Inc.
     37  * All rights reserved.
     38  *
     39  * Written by Frank van der Linden for Wasabi Systems, Inc.
     40  *
     41  * Redistribution and use in source and binary forms, with or without
     42  * modification, are permitted provided that the following conditions
     43  * are met:
     44  * 1. Redistributions of source code must retain the above copyright
     45  *    notice, this list of conditions and the following disclaimer.
     46  * 2. Redistributions in binary form must reproduce the above copyright
     47  *    notice, this list of conditions and the following disclaimer in the
     48  *    documentation and/or other materials provided with the distribution.
     49  * 3. All advertising materials mentioning features or use of this software
     50  *    must display the following acknowledgement:
     51  *      This product includes software developed for the NetBSD Project by
     52  *      Wasabi Systems, Inc.
     53  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
     54  *    or promote products derived from this software without specific prior
     55  *    written permission.
     56  *
     57  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
     58  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     59  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     60  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
     61  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     62  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     63  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     64  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     65  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     66  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     67  * POSSIBILITY OF SUCH DAMAGE.
     68  */
     69 
     70 #ifndef	_I386_PMAP_H_
     71 #define	_I386_PMAP_H_
     72 
     73 #if defined(_KERNEL_OPT)
     74 #include "opt_user_ldt.h"
     75 #include "opt_xen.h"
     76 #endif
     77 
     78 #include <sys/atomic.h>
     79 
     80 #include <machine/pte.h>
     81 #include <machine/segments.h>
     82 #if defined(_KERNEL)
     83 #include <machine/cpufunc.h>
     84 #endif
     85 
     86 #include <uvm/uvm_object.h>
     87 #ifdef XEN
     88 #include <xen/xenfunc.h>
     89 #include <xen/xenpmap.h>
     90 #endif /* XEN */
     91 
     92 /*
     93  * see pte.h for a description of i386 MMU terminology and hardware
     94  * interface.
     95  *
     96  * a pmap describes a processes' 4GB virtual address space.  this
     97  * virtual address space can be broken up into 1024 4MB regions which
     98  * are described by PDEs in the PDP.  the PDEs are defined as follows:
     99  *
    100  * (ranges are inclusive -> exclusive, just like vm_map_entry start/end)
    101  * (the following assumes that KERNBASE is 0xc0000000)
    102  *
    103  * PDE#s	VA range		usage
    104  * 0->766	0x0 -> 0xbfc00000	user address space
    105  * 767		0xbfc00000->		recursive mapping of PDP (used for
    106  *			0xc0000000	linear mapping of PTPs)
    107  * 768->1023	0xc0000000->		kernel address space (constant
    108  *			0xffc00000	across all pmap's/processes)
    109  * 1023		0xffc00000->		"alternate" recursive PDP mapping
    110  *			<end>		(for other pmaps)
    111  *
    112  *
    113  * note: a recursive PDP mapping provides a way to map all the PTEs for
    114  * a 4GB address space into a linear chunk of virtual memory.  in other
    115  * words, the PTE for page 0 is the first int mapped into the 4MB recursive
    116  * area.  the PTE for page 1 is the second int.  the very last int in the
    117  * 4MB range is the PTE that maps VA 0xfffff000 (the last page in a 4GB
    118  * address).
    119  *
    120  * all pmap's PD's must have the same values in slots 768->1023 so that
    121  * the kernel is always mapped in every process.  these values are loaded
    122  * into the PD at pmap creation time.
    123  *
    124  * at any one time only one pmap can be active on a processor.  this is
    125  * the pmap whose PDP is pointed to by processor register %cr3.  this pmap
    126  * will have all its PTEs mapped into memory at the recursive mapping
    127  * point (slot #767 as show above).  when the pmap code wants to find the
    128  * PTE for a virtual address, all it has to do is the following:
    129  *
    130  * address of PTE = (767 * 4MB) + (VA / PAGE_SIZE) * sizeof(pt_entry_t)
    131  *                = 0xbfc00000 + (VA / 4096) * 4
    132  *
    133  * what happens if the pmap layer is asked to perform an operation
    134  * on a pmap that is not the one which is currently active?  in that
    135  * case we take the PA of the PDP of non-active pmap and put it in
    136  * slot 1023 of the active pmap.  this causes the non-active pmap's
    137  * PTEs to get mapped in the final 4MB of the 4GB address space
    138  * (e.g. starting at 0xffc00000).
    139  *
    140  * the following figure shows the effects of the recursive PDP mapping:
    141  *
    142  *   PDP (%cr3)
    143  *   +----+
    144  *   |   0| -> PTP#0 that maps VA 0x0 -> 0x400000
    145  *   |    |
    146  *   |    |
    147  *   | 767| -> points back to PDP (%cr3) mapping VA 0xbfc00000 -> 0xc0000000
    148  *   | 768| -> first kernel PTP (maps 0xc0000000 -> 0xc0400000)
    149  *   |    |
    150  *   |1023| -> points to alternate pmap's PDP (maps 0xffc00000 -> end)
    151  *   +----+
    152  *
    153  * note that the PDE#767 VA (0xbfc00000) is defined as "PTE_BASE"
    154  * note that the PDE#1023 VA (0xffc00000) is defined as "APTE_BASE"
    155  *
    156  * starting at VA 0xbfc00000 the current active PDP (%cr3) acts as a
    157  * PTP:
    158  *
    159  * PTP#767 == PDP(%cr3) => maps VA 0xbfc00000 -> 0xc0000000
    160  *   +----+
    161  *   |   0| -> maps the contents of PTP#0 at VA 0xbfc00000->0xbfc01000
    162  *   |    |
    163  *   |    |
    164  *   | 767| -> maps contents of PTP#767 (the PDP) at VA 0xbfeff000
    165  *   | 768| -> maps contents of first kernel PTP
    166  *   |    |
    167  *   |1023|
    168  *   +----+
    169  *
    170  * note that mapping of the PDP at PTP#767's VA (0xbfeff000) is
    171  * defined as "PDP_BASE".... within that mapping there are two
    172  * defines:
    173  *   "PDP_PDE" (0xbfeffbfc) is the VA of the PDE in the PDP
    174  *      which points back to itself.
    175  *   "APDP_PDE" (0xbfeffffc) is the VA of the PDE in the PDP which
    176  *      establishes the recursive mapping of the alternate pmap.
    177  *      to set the alternate PDP, one just has to put the correct
    178  *	PA info in *APDP_PDE.
    179  *
    180  * note that in the APTE_BASE space, the APDP appears at VA
    181  * "APDP_BASE" (0xfffff000).
    182  */
    183 /* XXX MP should we allocate one APDP_PDE per processor?? */
    184 
    185 /*
    186  * Mask to get rid of the sign-extended part of addresses.
    187  */
    188 #define VA_SIGN_MASK		0
    189 #define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
    190 /*
    191  * XXXfvdl this one's not right.
    192  */
    193 #define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
    194 
    195 /*
    196  * the following defines identify the slots used as described above.
    197  */
    198 
    199 #define L2_SLOT_PTE	(KERNBASE/NBPD_L2-1)	/* 767: for recursive PDP map */
    200 #define L2_SLOT_KERN	(KERNBASE/NBPD_L2)	/* 768: start of kernel space */
    201 #define	L2_SLOT_KERNBASE L2_SLOT_KERN
    202 #ifndef XEN
    203 #define L2_SLOT_APTE	1023		/* 1023: alternative recursive slot */
    204 #else
    205 #define L2_SLOT_APTE	1007		/* 1008-1023 reserved by Xen */
    206 #endif
    207 
    208 
    209 #define PDIR_SLOT_KERN	L2_SLOT_KERN
    210 #define PDIR_SLOT_PTE	L2_SLOT_PTE
    211 #define PDIR_SLOT_APTE	L2_SLOT_APTE
    212 
    213 /*
    214  * the following defines give the virtual addresses of various MMU
    215  * data structures:
    216  * PTE_BASE and APTE_BASE: the base VA of the linear PTE mappings
    217  * PDP_BASE and APDP_BASE: the base VA of the recursive mapping of the PDP
    218  * PDP_PDE and APDP_PDE: the VA of the PDE that points back to the PDP/APDP
    219  */
    220 
    221 #define PTE_BASE  ((pt_entry_t *) (L2_SLOT_PTE * NBPD_L2))
    222 #define APTE_BASE ((pt_entry_t *) (VA_SIGN_NEG((L2_SLOT_APTE * NBPD_L2))))
    223 
    224 #define L1_BASE		PTE_BASE
    225 #define AL1_BASE	APTE_BASE
    226 
    227 #define L2_BASE ((pd_entry_t *)((char *)L1_BASE + L2_SLOT_PTE * NBPD_L1))
    228 
    229 #define AL2_BASE ((pd_entry_t *)((char *)AL1_BASE + L2_SLOT_PTE * NBPD_L1))
    230 
    231 #define PDP_PDE		(L2_BASE + PDIR_SLOT_PTE)
    232 #define APDP_PDE	(L2_BASE + PDIR_SLOT_APTE)
    233 
    234 #define PDP_BASE	L2_BASE
    235 #define APDP_BASE	AL2_BASE
    236 
    237 /* largest value (-1 for APTP space) */
    238 #define NKL2_MAX_ENTRIES	(NTOPLEVEL_PDES - (KERNBASE/NBPD_L2) - 1)
    239 #define NKL1_MAX_ENTRIES	(unsigned long)(NKL2_MAX_ENTRIES * NPDPG)
    240 
    241 #define NKL2_KIMG_ENTRIES	0	/* XXX unused */
    242 
    243 #define NKL2_START_ENTRIES	0	/* XXX computed on runtime */
    244 #define NKL1_START_ENTRIES	0	/* XXX unused */
    245 
    246 #define NTOPLEVEL_PDES		(PAGE_SIZE / (sizeof (pd_entry_t)))
    247 
    248 #define NPDPG			(PAGE_SIZE / sizeof (pd_entry_t))
    249 
    250 #define PTP_MASK_INITIALIZER	{ L1_FRAME, L2_FRAME }
    251 #define PTP_SHIFT_INITIALIZER	{ L1_SHIFT, L2_SHIFT }
    252 #define NKPTP_INITIALIZER	{ NKL1_START_ENTRIES, NKL2_START_ENTRIES }
    253 #define NKPTPMAX_INITIALIZER	{ NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES }
    254 #define NBPD_INITIALIZER	{ NBPD_L1, NBPD_L2 }
    255 #define PDES_INITIALIZER	{ L2_BASE }
    256 #define APDES_INITIALIZER	{ AL2_BASE }
    257 
    258 #define PTP_LEVELS	2
    259 
    260 /*
    261  * PG_AVAIL usage: we make use of the ignored bits of the PTE
    262  */
    263 
    264 #define PG_W		PG_AVAIL1	/* "wired" mapping */
    265 #define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
    266 #define PG_X		PG_AVAIL3	/* executable mapping */
    267 
    268 /*
    269  * Number of PTE's per cache line.  4 byte pte, 32-byte cache line
    270  * Used to avoid false sharing of cache lines.
    271  */
    272 #define NPTECL		8
    273 
    274 #include <x86/pmap.h>
    275 
    276 #ifndef XEN
    277 #define pmap_pa2pte(a)			(a)
    278 #define pmap_pte2pa(a)			((a) & PG_FRAME)
    279 #define pmap_pte_set(p, n)		do { *(p) = (n); } while (0)
    280 #define pmap_pte_testset(p, n)		\
    281     atomic_swap_ulong((volatile unsigned long *)p, n)
    282 #define pmap_pte_setbits(p, b)		\
    283     atomic_or_ulong((volatile unsigned long *)p, b)
    284 #define pmap_pte_clearbits(p, b)	\
    285     atomic_and_ulong((volatile unsigned long *)p, ~(b))
    286 #define pmap_pte_flush()		/* nothing */
    287 #else
    288 static __inline pt_entry_t
    289 pmap_pa2pte(paddr_t pa)
    290 {
    291 	return (pt_entry_t)xpmap_ptom_masked(pa);
    292 }
    293 
    294 static __inline paddr_t
    295 pmap_pte2pa(pt_entry_t pte)
    296 {
    297 	return xpmap_mtop_masked(pte & PG_FRAME);
    298 }
    299 static __inline void
    300 pmap_pte_set(pt_entry_t *pte, pt_entry_t npte)
    301 {
    302 	int s = splvm();
    303 	xpq_queue_pte_update((pt_entry_t *)xpmap_ptetomach(pte), npte);
    304 	splx(s);
    305 }
    306 
    307 static __inline pt_entry_t
    308 pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte)
    309 {
    310 	int s = splvm();
    311 	pt_entry_t opte = *pte;
    312 	xpq_queue_pte_update((pt_entry_t *)xpmap_ptetomach(__UNVOLATILE(pte)),
    313 	    npte);
    314 	xpq_flush_queue();
    315 	splx(s);
    316 	return opte;
    317 }
    318 
    319 static __inline void
    320 pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits)
    321 {
    322 	int s = splvm();
    323 	xpq_queue_pte_update((pt_entry_t *)xpmap_ptetomach(__UNVOLATILE(pte)),
    324 	    (*pte) | bits);
    325 	xpq_flush_queue();
    326 	splx(s);
    327 }
    328 
    329 static __inline void
    330 pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits)
    331 {
    332 	int s = splvm();
    333 	xpq_queue_pte_update((pt_entry_t *)xpmap_ptetomach(__UNVOLATILE(pte)),
    334 	    (*pte) & ~bits);
    335 	xpq_flush_queue();
    336 	splx(s);
    337 }
    338 
    339 static __inline void
    340 pmap_pte_flush(void)
    341 {
    342 	int s = splvm();
    343 	xpq_flush_queue();
    344 	splx(s);
    345 }
    346 #endif
    347 
    348 struct trapframe;
    349 
    350 int	pmap_exec_fixup(struct vm_map *, struct trapframe *, struct pcb *);
    351 void	pmap_ldt_cleanup(struct lwp *);
    352 
    353 #ifdef XEN
    354 #define NKPTP_MIN       4       /* smallest value we allow */
    355 #define NKPTP_MAX       4
    356 #endif /* XXX has to die ! */
    357 
    358 
    359 #endif	/* _I386_PMAP_H_ */
    360