pte.h revision 1.13.2.2
1 1.13.2.1 skrll /* $NetBSD: pte.h,v 1.13.2.2 2004/09/18 14:35:40 skrll Exp $ */ 2 1.11 thorpej 3 1.10 mrg /* 4 1.10 mrg * 5 1.10 mrg * Copyright (c) 1997 Charles D. Cranor and Washington University. 6 1.1 cgd * All rights reserved. 7 1.1 cgd * 8 1.1 cgd * Redistribution and use in source and binary forms, with or without 9 1.1 cgd * modification, are permitted provided that the following conditions 10 1.1 cgd * are met: 11 1.1 cgd * 1. Redistributions of source code must retain the above copyright 12 1.1 cgd * notice, this list of conditions and the following disclaimer. 13 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright 14 1.1 cgd * notice, this list of conditions and the following disclaimer in the 15 1.1 cgd * documentation and/or other materials provided with the distribution. 16 1.1 cgd * 3. All advertising materials mentioning features or use of this software 17 1.10 mrg * must display the following acknowledgment: 18 1.10 mrg * This product includes software developed by Charles D. Cranor and 19 1.10 mrg * Washington University. 20 1.10 mrg * 4. The name of the author may not be used to endorse or promote products 21 1.10 mrg * derived from this software without specific prior written permission. 22 1.10 mrg * 23 1.10 mrg * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 1.10 mrg * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 1.10 mrg * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 1.10 mrg * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 1.10 mrg * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 1.10 mrg * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 1.10 mrg * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 1.10 mrg * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 1.10 mrg * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 1.10 mrg * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 1.1 cgd */ 34 1.1 cgd 35 1.1 cgd /* 36 1.10 mrg * pte.h rewritten by chuck based on the jolitz version, plus random 37 1.10 mrg * info on the pentium and other processors found on the net. the 38 1.10 mrg * goal of this rewrite is to provide enough documentation on the MMU 39 1.10 mrg * hardware that the reader will be able to understand it without having 40 1.10 mrg * to refer to a hardware manual. 41 1.1 cgd */ 42 1.1 cgd 43 1.3 andrew #ifndef _I386_PTE_H_ 44 1.3 andrew #define _I386_PTE_H_ 45 1.3 andrew 46 1.10 mrg /* 47 1.10 mrg * i386 MMU hardware structure: 48 1.10 mrg * 49 1.10 mrg * the i386 MMU is a two-level MMU which maps 4GB of virtual memory. 50 1.10 mrg * the pagesize is 4K (4096 [0x1000] bytes), although newer pentium 51 1.10 mrg * processors can support a 4MB pagesize as well. 52 1.10 mrg * 53 1.10 mrg * the first level table (segment table?) is called a "page directory" 54 1.10 mrg * and it contains 1024 page directory entries (PDEs). each PDE is 55 1.10 mrg * 4 bytes (an int), so a PD fits in a single 4K page. this page is 56 1.10 mrg * the page directory page (PDP). each PDE in a PDP maps 4MB of space 57 1.10 mrg * (1024 * 4MB = 4GB). a PDE contains the physical address of the 58 1.10 mrg * second level table: the page table. or, if 4MB pages are being used, 59 1.10 mrg * then the PDE contains the PA of the 4MB page being mapped. 60 1.10 mrg * 61 1.10 mrg * a page table consists of 1024 page table entries (PTEs). each PTE is 62 1.10 mrg * 4 bytes (an int), so a page table also fits in a single 4K page. a 63 1.10 mrg * 4K page being used as a page table is called a page table page (PTP). 64 1.10 mrg * each PTE in a PTP maps one 4K page (1024 * 4K = 4MB). a PTE contains 65 1.10 mrg * the physical address of the page it maps and some flag bits (described 66 1.10 mrg * below). 67 1.10 mrg * 68 1.10 mrg * the processor has a special register, "cr3", which points to the 69 1.10 mrg * the PDP which is currently controlling the mappings of the virtual 70 1.10 mrg * address space. 71 1.10 mrg * 72 1.10 mrg * the following picture shows the translation process for a 4K page: 73 1.10 mrg * 74 1.10 mrg * %cr3 register [PA of PDP] 75 1.10 mrg * | 76 1.10 mrg * | 77 1.10 mrg * | bits <31-22> of VA bits <21-12> of VA bits <11-0> 78 1.10 mrg * | index the PDP (0 - 1023) index the PTP are the page offset 79 1.10 mrg * | | | | 80 1.10 mrg * | v | | 81 1.10 mrg * +--->+----------+ | | 82 1.10 mrg * | PD Page | PA of v | 83 1.10 mrg * | |---PTP-------->+------------+ | 84 1.10 mrg * | 1024 PDE | | page table |--PTE--+ | 85 1.10 mrg * | entries | | (aka PTP) | | | 86 1.10 mrg * +----------+ | 1024 PTE | | | 87 1.10 mrg * | entries | | | 88 1.10 mrg * +------------+ | | 89 1.10 mrg * | | 90 1.10 mrg * bits <31-12> bits <11-0> 91 1.10 mrg * p h y s i c a l a d d r 92 1.10 mrg * 93 1.10 mrg * the i386 caches PTEs in a TLB. it is important to flush out old 94 1.10 mrg * TLB mappings when making a change to a mappings. writing to the 95 1.10 mrg * %cr3 will flush the entire TLB. newer processors also have an 96 1.10 mrg * instruction that will invalidate the mapping of a single page (which 97 1.10 mrg * is useful if you are changing a single mappings because it preserves 98 1.10 mrg * all the cached TLB entries). 99 1.10 mrg * 100 1.10 mrg * as shows, bits 31-12 of the PTE contain PA of the page being mapped. 101 1.10 mrg * the rest of the PTE is defined as follows: 102 1.10 mrg * bit# name use 103 1.10 mrg * 11 n/a available for OS use, hardware ignores it 104 1.10 mrg * 10 n/a available for OS use, hardware ignores it 105 1.10 mrg * 9 n/a available for OS use, hardware ignores it 106 1.10 mrg * 8 G global bit (see discussion below) 107 1.10 mrg * 7 PS page size [for PDEs] (0=4k, 1=4M <if supported>) 108 1.10 mrg * 6 D dirty (modified) page 109 1.10 mrg * 5 A accessed (referenced) page 110 1.10 mrg * 4 PCD cache disable 111 1.10 mrg * 3 PWT prevent write through (cache) 112 1.10 mrg * 2 U/S user/supervisor bit (0=supervisor only, 1=both u&s) 113 1.10 mrg * 1 R/W read/write bit (0=read only, 1=read-write) 114 1.10 mrg * 0 P present (valid) 115 1.10 mrg * 116 1.10 mrg * notes: 117 1.10 mrg * - on the i386 the R/W bit is ignored if processor is in supervisor 118 1.10 mrg * state (bug!) 119 1.10 mrg * - PS is only supported on newer processors 120 1.10 mrg * - PTEs with the G bit are global in the sense that they are not 121 1.10 mrg * flushed from the TLB when %cr3 is written (to flush, use the 122 1.10 mrg * "flush single page" instruction). this is only supported on 123 1.10 mrg * newer processors. this bit can be used to keep the kernel's 124 1.10 mrg * TLB entries around while context switching. since the kernel 125 1.10 mrg * is mapped into all processes at the same place it does not make 126 1.10 mrg * sense to flush these entries when switching from one process' 127 1.10 mrg * pmap to another. 128 1.10 mrg */ 129 1.10 mrg 130 1.11 thorpej #if !defined(_LOCORE) 131 1.10 mrg 132 1.10 mrg /* 133 1.10 mrg * here we define the data types for PDEs and PTEs 134 1.10 mrg */ 135 1.10 mrg 136 1.10 mrg typedef u_int32_t pd_entry_t; /* PDE */ 137 1.10 mrg typedef u_int32_t pt_entry_t; /* PTE */ 138 1.10 mrg 139 1.1 cgd #endif 140 1.1 cgd 141 1.10 mrg /* 142 1.10 mrg * now we define various for playing with virtual addresses 143 1.10 mrg */ 144 1.10 mrg 145 1.10 mrg #define PDSHIFT 22 /* offset of PD index in VA */ 146 1.10 mrg #define NBPD (1 << PDSHIFT) /* # bytes mapped by PD (4MB) */ 147 1.10 mrg #define PDOFSET (NBPD-1) /* mask for non-PD part of VA */ 148 1.10 mrg #if 0 /* not used? */ 149 1.13 thorpej #define NPTEPD (NBPD / PAGE_SIZE) /* # of PTEs in a PD */ 150 1.10 mrg #else 151 1.13 thorpej #define PTES_PER_PTP (NBPD / PAGE_SIZE) /* # of PTEs in a PTP */ 152 1.10 mrg #endif 153 1.1 cgd #define PD_MASK 0xffc00000 /* page directory address bits */ 154 1.4 mycroft #define PT_MASK 0x003ff000 /* page table address bits */ 155 1.1 cgd 156 1.10 mrg /* 157 1.10 mrg * here we define the bits of the PDE/PTE, as described above: 158 1.10 mrg * 159 1.10 mrg * XXXCDC: need to rename these (PG_u == ugly). 160 1.10 mrg */ 161 1.10 mrg 162 1.10 mrg #define PG_V 0x00000001 /* valid entry */ 163 1.10 mrg #define PG_RO 0x00000000 /* read-only page */ 164 1.10 mrg #define PG_RW 0x00000002 /* read-write page */ 165 1.10 mrg #define PG_u 0x00000004 /* user accessible page */ 166 1.13.2.1 skrll #define PG_PROT 0x00000806 /* all protection bits */ 167 1.4 mycroft #define PG_N 0x00000018 /* non-cacheable */ 168 1.4 mycroft #define PG_U 0x00000020 /* has been used */ 169 1.4 mycroft #define PG_M 0x00000040 /* has been modified */ 170 1.10 mrg #define PG_PS 0x00000080 /* 4MB page size */ 171 1.10 mrg #define PG_G 0x00000100 /* global, don't TLB flush */ 172 1.10 mrg #define PG_AVAIL1 0x00000200 /* ignored by hardware */ 173 1.10 mrg #define PG_AVAIL2 0x00000400 /* ignored by hardware */ 174 1.10 mrg #define PG_AVAIL3 0x00000800 /* ignored by hardware */ 175 1.4 mycroft #define PG_FRAME 0xfffff000 /* page frame mask */ 176 1.12 thorpej 177 1.12 thorpej #define PG_LGFRAME 0xffc00000 /* large (4MB) page frame mask */ 178 1.1 cgd 179 1.10 mrg /* 180 1.10 mrg * various short-hand protection codes 181 1.10 mrg */ 182 1.10 mrg 183 1.10 mrg #define PG_KR 0x00000000 /* kernel read-only */ 184 1.10 mrg #define PG_KW 0x00000002 /* kernel read-write */ 185 1.10 mrg 186 1.10 mrg /* 187 1.10 mrg * page protection exception bits 188 1.10 mrg */ 189 1.10 mrg 190 1.10 mrg #define PGEX_P 0x01 /* protection violation (vs. no mapping) */ 191 1.10 mrg #define PGEX_W 0x02 /* exception during a write cycle */ 192 1.10 mrg #define PGEX_U 0x04 /* exception while in user mode (upl) */ 193 1.3 andrew 194 1.3 andrew #endif /* _I386_PTE_H_ */ 195
Indexes created Sat Nov 01 05:10:12 GMT 2025