pte.h revision 1.14
1 /* $NetBSD: pte.h,v 1.14 2003/08/24 17:52:33 chs Exp $ */ 2 3 /* 4 * 5 * Copyright (c) 1997 Charles D. Cranor and Washington University. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgment: 18 * This product includes software developed by Charles D. Cranor and 19 * Washington University. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * pte.h rewritten by chuck based on the jolitz version, plus random 37 * info on the pentium and other processors found on the net. the 38 * goal of this rewrite is to provide enough documentation on the MMU 39 * hardware that the reader will be able to understand it without having 40 * to refer to a hardware manual. 41 */ 42 43 #ifndef _I386_PTE_H_ 44 #define _I386_PTE_H_ 45 46 /* 47 * i386 MMU hardware structure: 48 * 49 * the i386 MMU is a two-level MMU which maps 4GB of virtual memory. 50 * the pagesize is 4K (4096 [0x1000] bytes), although newer pentium 51 * processors can support a 4MB pagesize as well. 52 * 53 * the first level table (segment table?) is called a "page directory" 54 * and it contains 1024 page directory entries (PDEs). each PDE is 55 * 4 bytes (an int), so a PD fits in a single 4K page. this page is 56 * the page directory page (PDP). each PDE in a PDP maps 4MB of space 57 * (1024 * 4MB = 4GB). a PDE contains the physical address of the 58 * second level table: the page table. or, if 4MB pages are being used, 59 * then the PDE contains the PA of the 4MB page being mapped. 60 * 61 * a page table consists of 1024 page table entries (PTEs). each PTE is 62 * 4 bytes (an int), so a page table also fits in a single 4K page. a 63 * 4K page being used as a page table is called a page table page (PTP). 64 * each PTE in a PTP maps one 4K page (1024 * 4K = 4MB). a PTE contains 65 * the physical address of the page it maps and some flag bits (described 66 * below). 67 * 68 * the processor has a special register, "cr3", which points to the 69 * the PDP which is currently controlling the mappings of the virtual 70 * address space. 71 * 72 * the following picture shows the translation process for a 4K page: 73 * 74 * %cr3 register [PA of PDP] 75 * | 76 * | 77 * | bits <31-22> of VA bits <21-12> of VA bits <11-0> 78 * | index the PDP (0 - 1023) index the PTP are the page offset 79 * | | | | 80 * | v | | 81 * +--->+----------+ | | 82 * | PD Page | PA of v | 83 * | |---PTP-------->+------------+ | 84 * | 1024 PDE | | page table |--PTE--+ | 85 * | entries | | (aka PTP) | | | 86 * +----------+ | 1024 PTE | | | 87 * | entries | | | 88 * +------------+ | | 89 * | | 90 * bits <31-12> bits <11-0> 91 * p h y s i c a l a d d r 92 * 93 * the i386 caches PTEs in a TLB. it is important to flush out old 94 * TLB mappings when making a change to a mappings. writing to the 95 * %cr3 will flush the entire TLB. newer processors also have an 96 * instruction that will invalidate the mapping of a single page (which 97 * is useful if you are changing a single mappings because it preserves 98 * all the cached TLB entries). 99 * 100 * as shows, bits 31-12 of the PTE contain PA of the page being mapped. 101 * the rest of the PTE is defined as follows: 102 * bit# name use 103 * 11 n/a available for OS use, hardware ignores it 104 * 10 n/a available for OS use, hardware ignores it 105 * 9 n/a available for OS use, hardware ignores it 106 * 8 G global bit (see discussion below) 107 * 7 PS page size [for PDEs] (0=4k, 1=4M <if supported>) 108 * 6 D dirty (modified) page 109 * 5 A accessed (referenced) page 110 * 4 PCD cache disable 111 * 3 PWT prevent write through (cache) 112 * 2 U/S user/supervisor bit (0=supervisor only, 1=both u&s) 113 * 1 R/W read/write bit (0=read only, 1=read-write) 114 * 0 P present (valid) 115 * 116 * notes: 117 * - on the i386 the R/W bit is ignored if processor is in supervisor 118 * state (bug!) 119 * - PS is only supported on newer processors 120 * - PTEs with the G bit are global in the sense that they are not 121 * flushed from the TLB when %cr3 is written (to flush, use the 122 * "flush single page" instruction). this is only supported on 123 * newer processors. this bit can be used to keep the kernel's 124 * TLB entries around while context switching. since the kernel 125 * is mapped into all processes at the same place it does not make 126 * sense to flush these entries when switching from one process' 127 * pmap to another. 128 */ 129 130 #if !defined(_LOCORE) 131 132 /* 133 * here we define the data types for PDEs and PTEs 134 */ 135 136 typedef u_int32_t pd_entry_t; /* PDE */ 137 typedef u_int32_t pt_entry_t; /* PTE */ 138 139 #endif 140 141 /* 142 * now we define various for playing with virtual addresses 143 */ 144 145 #define PDSHIFT 22 /* offset of PD index in VA */ 146 #define NBPD (1 << PDSHIFT) /* # bytes mapped by PD (4MB) */ 147 #define PDOFSET (NBPD-1) /* mask for non-PD part of VA */ 148 #if 0 /* not used? */ 149 #define NPTEPD (NBPD / PAGE_SIZE) /* # of PTEs in a PD */ 150 #else 151 #define PTES_PER_PTP (NBPD / PAGE_SIZE) /* # of PTEs in a PTP */ 152 #endif 153 #define PD_MASK 0xffc00000 /* page directory address bits */ 154 #define PT_MASK 0x003ff000 /* page table address bits */ 155 156 /* 157 * here we define the bits of the PDE/PTE, as described above: 158 * 159 * XXXCDC: need to rename these (PG_u == ugly). 160 */ 161 162 #define PG_V 0x00000001 /* valid entry */ 163 #define PG_RO 0x00000000 /* read-only page */ 164 #define PG_RW 0x00000002 /* read-write page */ 165 #define PG_u 0x00000004 /* user accessible page */ 166 #define PG_PROT 0x00000806 /* all protection bits */ 167 #define PG_N 0x00000018 /* non-cacheable */ 168 #define PG_U 0x00000020 /* has been used */ 169 #define PG_M 0x00000040 /* has been modified */ 170 #define PG_PS 0x00000080 /* 4MB page size */ 171 #define PG_G 0x00000100 /* global, don't TLB flush */ 172 #define PG_AVAIL1 0x00000200 /* ignored by hardware */ 173 #define PG_AVAIL2 0x00000400 /* ignored by hardware */ 174 #define PG_AVAIL3 0x00000800 /* ignored by hardware */ 175 #define PG_FRAME 0xfffff000 /* page frame mask */ 176 177 #define PG_LGFRAME 0xffc00000 /* large (4MB) page frame mask */ 178 179 /* 180 * various short-hand protection codes 181 */ 182 183 #define PG_KR 0x00000000 /* kernel read-only */ 184 #define PG_KW 0x00000002 /* kernel read-write */ 185 186 /* 187 * page protection exception bits 188 */ 189 190 #define PGEX_P 0x01 /* protection violation (vs. no mapping) */ 191 #define PGEX_W 0x02 /* exception during a write cycle */ 192 #define PGEX_U 0x04 /* exception while in user mode (upl) */ 193 194 #endif /* _I386_PTE_H_ */ 195
Indexes created Tue Sep 30 11:09:46 GMT 2025