specialreg.h revision 1.5.2.1
1 1.1 cgd /*- 2 1.1 cgd * Copyright (c) 1991 The Regents of the University of California. 3 1.1 cgd * All rights reserved. 4 1.1 cgd * 5 1.1 cgd * Redistribution and use in source and binary forms, with or without 6 1.1 cgd * modification, are permitted provided that the following conditions 7 1.1 cgd * are met: 8 1.1 cgd * 1. Redistributions of source code must retain the above copyright 9 1.1 cgd * notice, this list of conditions and the following disclaimer. 10 1.1 cgd * 2. Redistributions in binary form must reproduce the above copyright 11 1.1 cgd * notice, this list of conditions and the following disclaimer in the 12 1.1 cgd * documentation and/or other materials provided with the distribution. 13 1.1 cgd * 3. All advertising materials mentioning features or use of this software 14 1.1 cgd * must display the following acknowledgement: 15 1.1 cgd * This product includes software developed by the University of 16 1.1 cgd * California, Berkeley and its contributors. 17 1.1 cgd * 4. Neither the name of the University nor the names of its contributors 18 1.1 cgd * may be used to endorse or promote products derived from this software 19 1.1 cgd * without specific prior written permission. 20 1.1 cgd * 21 1.1 cgd * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 22 1.1 cgd * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 1.1 cgd * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 1.1 cgd * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 25 1.1 cgd * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 1.1 cgd * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 1.1 cgd * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 1.1 cgd * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 1.1 cgd * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 1.1 cgd * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 1.1 cgd * SUCH DAMAGE. 32 1.1 cgd * 33 1.3 cgd * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 34 1.5.2.1 mycroft * $Id: specialreg.h,v 1.5.2.1 1994/08/03 23:36:36 mycroft Exp $ 35 1.1 cgd */ 36 1.1 cgd 37 1.1 cgd /* 38 1.2 deraadt * Bits in 386 special registers: 39 1.1 cgd */ 40 1.1 cgd #define CR0_PE 0x00000001 /* Protected mode Enable */ 41 1.2 deraadt #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 42 1.2 deraadt #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 43 1.2 deraadt #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 44 1.2 deraadt #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 45 1.2 deraadt #define CR0_PG 0x80000000 /* PaGing enable */ 46 1.2 deraadt 47 1.2 deraadt /* 48 1.2 deraadt * Bits in 486 special registers: 49 1.2 deraadt */ 50 1.2 deraadt #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 51 1.4 mycroft #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 52 1.2 deraadt #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 53 1.5 mycroft #define CR0_NW 0x20000000 /* Not Write-through */ 54 1.5 mycroft #define CR0_CD 0x40000000 /* Cache Disable */ 55 1.5.2.1 mycroft 56 1.5.2.1 mycroft /* 57 1.5.2.1 mycroft * Cyrix 486 DLC special registers, accessable as IO ports. 58 1.5.2.1 mycroft */ 59 1.5.2.1 mycroft #define CCR0 0xc0 /* configuration control register 0 */ 60 1.5.2.1 mycroft #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 61 1.5.2.1 mycroft #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 62 1.5.2.1 mycroft #define CCR0_A20M 0x04 /* enables A20M# input pin */ 63 1.5.2.1 mycroft #define CCR0_KEN 0x08 /* enables KEN# input pin */ 64 1.5.2.1 mycroft #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 65 1.5.2.1 mycroft #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 66 1.5.2.1 mycroft #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 67 1.5.2.1 mycroft #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 68 1.5.2.1 mycroft 69 1.5.2.1 mycroft #define CCR1 0xc1 /* configuration control register 1 */ 70 1.5.2.1 mycroft #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 71 1.5.2.1 mycroft /* the remaining 7 bits of this register are reserved */ 72 1.5.2.1 mycroft 73 1.5.2.1 mycroft /* 74 1.5.2.1 mycroft * the following four 3-byte registers control the non-cacheable regions. 75 1.5.2.1 mycroft * These registers must be written as three seperate bytes. 76 1.5.2.1 mycroft * 77 1.5.2.1 mycroft * NCRx+0: A31-A24 of starting address 78 1.5.2.1 mycroft * NCRx+1: A23-A16 of starting address 79 1.5.2.1 mycroft * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 80 1.5.2.1 mycroft * 81 1.5.2.1 mycroft * The non-cacheable region's starting address must be aligned to the 82 1.5.2.1 mycroft * size indicated by the NCR_SIZE_xx field. 83 1.5.2.1 mycroft */ 84 1.5.2.1 mycroft #define NCR1 0xc4 85 1.5.2.1 mycroft #define NCR2 0xc7 86 1.5.2.1 mycroft #define NCR3 0xca 87 1.5.2.1 mycroft #define NCR4 0xcd 88 1.5.2.1 mycroft 89 1.5.2.1 mycroft #define NCR_SIZE_0K 0 90 1.5.2.1 mycroft #define NCR_SIZE_4K 1 91 1.5.2.1 mycroft #define NCR_SIZE_8K 2 92 1.5.2.1 mycroft #define NCR_SIZE_16K 3 93 1.5.2.1 mycroft #define NCR_SIZE_32K 4 94 1.5.2.1 mycroft #define NCR_SIZE_64K 5 95 1.5.2.1 mycroft #define NCR_SIZE_128K 6 96 1.5.2.1 mycroft #define NCR_SIZE_256K 7 97 1.5.2.1 mycroft #define NCR_SIZE_512K 8 98 1.5.2.1 mycroft #define NCR_SIZE_1M 9 99 1.5.2.1 mycroft #define NCR_SIZE_2M 10 100 1.5.2.1 mycroft #define NCR_SIZE_4M 11 101 1.5.2.1 mycroft #define NCR_SIZE_8M 12 102 1.5.2.1 mycroft #define NCR_SIZE_16M 13 103 1.5.2.1 mycroft #define NCR_SIZE_32M 14 104 1.5.2.1 mycroft #define NCR_SIZE_4G 15 105 1.5.2.1 mycroft 106
Indexes created Sun Oct 26 17:10:13 GMT 2025