specialreg.h revision 1.19.4.1
1 /* $NetBSD: specialreg.h,v 1.19.4.1 2001/10/01 12:40:02 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by the University of 18 * California, Berkeley and its contributors. 19 * 4. Neither the name of the University nor the names of its contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91 36 */ 37 38 /* 39 * Bits in 386 special registers: 40 */ 41 #define CR0_PE 0x00000001 /* Protected mode Enable */ 42 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */ 43 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */ 44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */ 46 #define CR0_PG 0x80000000 /* PaGing enable */ 47 48 /* 49 * Bits in 486 special registers: 50 */ 51 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 52 #define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */ 53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54 #define CR0_NW 0x20000000 /* Not Write-through */ 55 #define CR0_CD 0x40000000 /* Cache Disable */ 56 57 /* 58 * Cyrix 486 DLC special registers, accessible as IO ports. 59 */ 60 #define CCR0 0xc0 /* configuration control register 0 */ 61 #define CCR0_NC0 0x01 /* first 64K of each 1M memory region is non-cacheable */ 62 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 63 #define CCR0_A20M 0x04 /* enables A20M# input pin */ 64 #define CCR0_KEN 0x08 /* enables KEN# input pin */ 65 #define CCR0_FLUSH 0x10 /* enables FLUSH# input pin */ 66 #define CCR0_BARB 0x20 /* flushes internal cache when entering hold state */ 67 #define CCR0_CO 0x40 /* cache org: 1=direct mapped, 0=2x set assoc */ 68 #define CCR0_SUSPEND 0x80 /* enables SUSP# and SUSPA# pins */ 69 70 #define CCR1 0xc1 /* configuration control register 1 */ 71 #define CCR1_RPL 0x01 /* enables RPLSET and RPLVAL# pins */ 72 /* the remaining 7 bits of this register are reserved */ 73 74 /* 75 * bits in the pentiums %cr4 register: 76 */ 77 78 #define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */ 79 #define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */ 80 #define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */ 81 #define CR4_DE 0x00000008 /* debugging extension */ 82 #define CR4_PSE 0x00000010 /* large (4MB) page size enable */ 83 #define CR4_PAE 0x00000020 /* physical address extension enable */ 84 #define CR4_MCE 0x00000040 /* machine check enable */ 85 #define CR4_PGE 0x00000080 /* page global enable */ 86 #define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */ 87 #define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */ 88 #define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */ 89 90 /* 91 * CPUID "features" bits: 92 */ 93 94 #define CPUID_FPU 0x00000001 /* processor has an FPU? */ 95 #define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */ 96 #define CPUID_DE 0x00000004 /* has debugging extension */ 97 #define CPUID_PSE 0x00000008 /* has page 4MB page size extension */ 98 #define CPUID_TSC 0x00000010 /* has time stamp counter */ 99 #define CPUID_MSR 0x00000020 /* has mode specific registers */ 100 #define CPUID_PAE 0x00000040 /* has phys address extension */ 101 #define CPUID_MCE 0x00000080 /* has machine check exception */ 102 #define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */ 103 #define CPUID_APIC 0x00000200 /* has enabled APIC */ 104 #define CPUID_B10 0x00000400 /* reserved, MTRR */ 105 #define CPUID_SEP 0x00000800 /* has SYSENTER/SYSEXIT extension */ 106 #define CPUID_MTRR 0x00001000 /* has memory type range register */ 107 #define CPUID_PGE 0x00002000 /* has page global extension */ 108 #define CPUID_MCA 0x00004000 /* has machine check architecture */ 109 #define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */ 110 #define CPUID_FGPAT 0x00010000 /* Page Attribute Table */ 111 #define CPUID_PSE36 0x00020000 /* 36-bit PSE */ 112 #define CPUID_PN 0x00040000 /* processor serial number */ 113 #define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */ 114 #define CPUID_B20 0x00100000 /* reserved */ 115 #define CPUID_DS 0x00200000 /* Debug Store */ 116 #define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */ 117 #define CPUID_MMX 0x00800000 /* MMX supported */ 118 #define CPUID_FXSR 0x01000000 /* fast FP/MMX save/restore */ 119 #define CPUID_SSE 0x02000000 /* streaming SIMD extensions */ 120 #define CPUID_SSE2 0x04000000 /* streaming SIMD extensions #2 */ 121 #define CPUID_SS 0x08000000 /* self-snoop */ 122 #define CPUID_B28 0x10000000 /* reserved */ 123 #define CPUID_TM 0x20000000 /* thermal monitor (TCC) */ 124 #define CPUID_B30 0x40000000 /* reserved */ 125 #define CPUID_B31 0x80000000 /* reserved */ 126 127 #define CPUID_FLAGS1 "\20\1FPU\2VME\3DE\4PSE\5TSC\6MSR\7PAE" \ 128 "\10MCE\11CX8\12APIC\13B10\14SEP\15MTRR" 129 #define CPUID_MASK1 0x00001fff 130 #define CPUID_FLAGS2 "\20\16PGE\17MCA\20CMOV\21FGPAT\22PSE36\23PN\24CFLUSH" \ 131 "\25B20\26DS\27ACPI\30MMX\31FXSR\32SSE\33SSE2" \ 132 "\34SS\35B28\36TM\37B30\40B31" 133 #define CPUID_MASK2 0xffffe000 134 135 /* 136 * Model-specific registers for the i386 family 137 */ 138 #define MSR_P5_MC_ADDR 0x000 /* P5 only */ 139 #define MSR_P5_MC_TYPE 0x001 /* P5 only */ 140 #define MSR_TSC 0x010 141 #define MSR_CESR 0x011 /* P5 only (trap on P6) */ 142 #define MSR_CTR0 0x012 /* P5 only (trap on P6) */ 143 #define MSR_CTR1 0x013 /* P5 only (trap on P6) */ 144 #define MSR_APICBASE 0x01b 145 #define MSR_EBL_CR_POWERON 0x02a 146 #define MSR_TEST_CTL 0x033 147 #define MSR_BIOS_UPDT_TRIG 0x079 148 #define MSR_BBL_CR_D0 0x088 /* PII+ only */ 149 #define MSR_BBL_CR_D1 0x089 /* PII+ only */ 150 #define MSR_BBL_CR_D2 0x08a /* PII+ only */ 151 #define MSR_BIOS_SIGN 0x08b 152 #define MSR_PERFCTR0 0x0c1 153 #define MSR_PERFCTR1 0x0c2 154 #define MSR_MTRRcap 0x0fe 155 #define MSR_BBL_CR_ADDR 0x116 /* PII+ only */ 156 #define MSR_BBL_CR_DECC 0x118 /* PII+ only */ 157 #define MSR_BBL_CR_CTL 0x119 /* PII+ only */ 158 #define MSR_BBL_CR_TRIG 0x11a /* PII+ only */ 159 #define MSR_BBL_CR_BUSY 0x11b /* PII+ only */ 160 #define MSR_BBL_CR_CTR3 0x11e /* PII+ only */ 161 #define MSR_MCG_CAP 0x179 162 #define MSR_MCG_STATUS 0x17a 163 #define MSR_MCG_CTL 0x17b 164 #define MSR_EVNTSEL0 0x186 165 #define MSR_EVNTSEL1 0x187 166 #define MSR_DEBUGCTLMSR 0x1d9 167 #define MSR_LASTBRANCHFROMIP 0x1db 168 #define MSR_LASTBRANCHTOIP 0x1dc 169 #define MSR_LASTINTFROMIP 0x1dd 170 #define MSR_LASTINTTOIP 0x1de 171 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 172 #define MSR_MTRRphysBase0 0x200 173 #define MSR_MTRRphysMask0 0x201 174 #define MSR_MTRRphysBase1 0x202 175 #define MSR_MTRRphysMask1 0x203 176 #define MSR_MTRRphysBase2 0x204 177 #define MSR_MTRRphysMask2 0x205 178 #define MSR_MTRRphysBase3 0x206 179 #define MSR_MTRRphysMask3 0x207 180 #define MSR_MTRRphysBase4 0x208 181 #define MSR_MTRRphysMask4 0x209 182 #define MSR_MTRRphysBase5 0x20a 183 #define MSR_MTRRphysMask5 0x20b 184 #define MSR_MTRRphysBase6 0x20c 185 #define MSR_MTRRphysMask6 0x20d 186 #define MSR_MTRRphysBase7 0x20e 187 #define MSR_MTRRphysMask7 0x20f 188 #define MSR_MTRRfix64K_00000 0x250 189 #define MSR_MTRRfix16K_80000 0x258 190 #define MSR_MTRRfix16K_A0000 0x259 191 #define MSR_MTRRfix4K_C0000 0x268 192 #define MSR_MTRRfix4K_C8000 0x269 193 #define MSR_MTRRfix4K_D0000 0x26a 194 #define MSR_MTRRfix4K_D8000 0x26b 195 #define MSR_MTRRfix4K_E0000 0x26c 196 #define MSR_MTRRfix4K_E8000 0x26d 197 #define MSR_MTRRfix4K_F0000 0x26e 198 #define MSR_MTRRfix4K_F8000 0x26f 199 #define MSR_MTRRdefType 0x2ff 200 #define MSR_MC0_CTL 0x400 201 #define MSR_MC0_STATUS 0x401 202 #define MSR_MC0_ADDR 0x402 203 #define MSR_MC0_MISC 0x403 204 #define MSR_MC1_CTL 0x404 205 #define MSR_MC1_STATUS 0x405 206 #define MSR_MC1_ADDR 0x406 207 #define MSR_MC1_MISC 0x407 208 #define MSR_MC2_CTL 0x408 209 #define MSR_MC2_STATUS 0x409 210 #define MSR_MC2_ADDR 0x40a 211 #define MSR_MC2_MISC 0x40b 212 #define MSR_MC4_CTL 0x40c 213 #define MSR_MC4_STATUS 0x40d 214 #define MSR_MC4_ADDR 0x40e 215 #define MSR_MC4_MISC 0x40f 216 #define MSR_MC3_CTL 0x410 217 #define MSR_MC3_STATUS 0x411 218 #define MSR_MC3_ADDR 0x412 219 #define MSR_MC3_MISC 0x413 220 221 /* 222 * AMD K6 MSRs. 223 */ 224 #define MSR_K6_UWCCR 0xc0000085 225 226 /* 227 * Constants related to MTRRs 228 */ 229 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 230 #define MTRR_N16K 16 231 #define MTRR_N4K 64 232 233 /* 234 * the following four 3-byte registers control the non-cacheable regions. 235 * These registers must be written as three separate bytes. 236 * 237 * NCRx+0: A31-A24 of starting address 238 * NCRx+1: A23-A16 of starting address 239 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 240 * 241 * The non-cacheable region's starting address must be aligned to the 242 * size indicated by the NCR_SIZE_xx field. 243 */ 244 #define NCR1 0xc4 245 #define NCR2 0xc7 246 #define NCR3 0xca 247 #define NCR4 0xcd 248 249 #define NCR_SIZE_0K 0 250 #define NCR_SIZE_4K 1 251 #define NCR_SIZE_8K 2 252 #define NCR_SIZE_16K 3 253 #define NCR_SIZE_32K 4 254 #define NCR_SIZE_64K 5 255 #define NCR_SIZE_128K 6 256 #define NCR_SIZE_256K 7 257 #define NCR_SIZE_512K 8 258 #define NCR_SIZE_1M 9 259 #define NCR_SIZE_2M 10 260 #define NCR_SIZE_4M 11 261 #define NCR_SIZE_8M 12 262 #define NCR_SIZE_16M 13 263 #define NCR_SIZE_32M 14 264 #define NCR_SIZE_4G 15 265 266 /* 267 * Performance monitor events. 268 * 269 * Note that 586-class and 686-class CPUs have different performance 270 * monitors available, and they are accessed differently: 271 * 272 * 686-class: `rdpmc' instruction 273 * 586-class: `rdmsr' instruction, CESR MSR 274 * 275 * The descriptions of these events are too lenghy to include here. 276 * See Appendix A of "Intel Architecture Software Developer's 277 * Manual, Volume 3: System Programming" for more information. 278 */ 279 280 /* 281 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits 282 * is CTR1. 283 */ 284 285 #define PMC5_CESR_EVENT 0x003f 286 #define PMC5_CESR_OS 0x0040 287 #define PMC5_CESR_USR 0x0080 288 #define PMC5_CESR_E 0x0100 289 #define PMC5_CESR_P 0x0200 290 291 /* 292 * 686-class Event Selector MSR format. 293 */ 294 295 #define PMC6_EVTSEL_EVENT 0x000000ff 296 #define PMC6_EVTSEL_UNIT 0x0000ff00 297 #define PMC6_EVTSEL_UNIT_SHIFT 8 298 #define PMC6_EVTSEL_USR (1 << 16) 299 #define PMC6_EVTSEL_OS (1 << 17) 300 #define PMC6_EVTSEL_E (1 << 18) 301 #define PMC6_EVTSEL_PC (1 << 19) 302 #define PMC6_EVTSEL_INT (1 << 20) 303 #define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */ 304 #define PMC6_EVTSEL_INV (1 << 23) 305 #define PMC6_EVTSEL_COUNTER_MASK 0xff000000 306 #define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24 307 308 /* Data Cache Unit */ 309 #define PMC6_DATA_MEM_REFS 0x43 310 #define PMC6_DCU_LINES_IN 0x45 311 #define PMC6_DCU_M_LINES_IN 0x46 312 #define PMC6_DCU_M_LINES_OUT 0x47 313 #define PMC6_DCU_MISS_OUTSTANDING 0x48 314 315 /* Instruction Fetch Unit */ 316 #define PMC6_IFU_IFETCH 0x80 317 #define PMC6_IFU_IFETCH_MISS 0x81 318 #define PMC6_ITLB_MISS 0x85 319 #define PMC6_IFU_MEM_STALL 0x86 320 #define PMC6_ILD_STALL 0x87 321 322 /* L2 Cache */ 323 #define PMC6_L2_IFETCH 0x28 324 #define PMC6_L2_LD 0x29 325 #define PMC6_L2_ST 0x2a 326 #define PMC6_L2_LINES_IN 0x24 327 #define PMC6_L2_LINES_OUT 0x26 328 #define PMC6_L2_M_LINES_INM 0x25 329 #define PMC6_L2_M_LINES_OUTM 0x27 330 #define PMC6_L2_RQSTS 0x2e 331 #define PMC6_L2_ADS 0x21 332 #define PMC6_L2_DBUS_BUSY 0x22 333 #define PMC6_L2_DBUS_BUSY_RD 0x23 334 335 /* External Bus Logic */ 336 #define PMC6_BUS_DRDY_CLOCKS 0x62 337 #define PMC6_BUS_LOCK_CLOCKS 0x63 338 #define PMC6_BUS_REQ_OUTSTANDING 0x60 339 #define PMC6_BUS_TRAN_BRD 0x65 340 #define PMC6_BUS_TRAN_RFO 0x66 341 #define PMC6_BUS_TRANS_WB 0x67 342 #define PMC6_BUS_TRAN_IFETCH 0x68 343 #define PMC6_BUS_TRAN_INVAL 0x69 344 #define PMC6_BUS_TRAN_PWR 0x6a 345 #define PMC6_BUS_TRANS_P 0x6b 346 #define PMC6_BUS_TRANS_IO 0x6c 347 #define PMC6_BUS_TRAN_DEF 0x6d 348 #define PMC6_BUS_TRAN_BURST 0x6e 349 #define PMC6_BUS_TRAN_ANY 0x70 350 #define PMC6_BUS_TRAN_MEM 0x6f 351 #define PMC6_BUS_DATA_RCV 0x64 352 #define PMC6_BUS_BNR_DRV 0x61 353 #define PMC6_BUS_HIT_DRV 0x7a 354 #define PMC6_BUS_HITM_DRDV 0x7b 355 #define PMC6_BUS_SNOOP_STALL 0x7e 356 357 /* Floating Point Unit */ 358 #define PMC6_FLOPS 0xc1 359 #define PMC6_FP_COMP_OPS_EXE 0x10 360 #define PMC6_FP_ASSIST 0x11 361 #define PMC6_MUL 0x12 362 #define PMC6_DIV 0x12 363 #define PMC6_CYCLES_DIV_BUSY 0x14 364 365 /* Memory Ordering */ 366 #define PMC6_LD_BLOCKS 0x03 367 #define PMC6_SB_DRAINS 0x04 368 #define PMC6_MISALIGN_MEM_REF 0x05 369 #define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */ 370 #define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */ 371 372 /* Instruction Decoding and Retirement */ 373 #define PMC6_INST_RETIRED 0xc0 374 #define PMC6_UOPS_RETIRED 0xc2 375 #define PMC6_INST_DECODED 0xd0 376 #define PMC6_EMON_KNI_INST_RETIRED 0xd8 377 #define PMC6_EMON_KNI_COMP_INST_RET 0xd9 378 379 /* Interrupts */ 380 #define PMC6_HW_INT_RX 0xc8 381 #define PMC6_CYCLES_INT_MASKED 0xc6 382 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7 383 384 /* Branches */ 385 #define PMC6_BR_INST_RETIRED 0xc4 386 #define PMC6_BR_MISS_PRED_RETIRED 0xc5 387 #define PMC6_BR_TAKEN_RETIRED 0xc9 388 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca 389 #define PMC6_BR_INST_DECODED 0xe0 390 #define PMC6_BTB_MISSES 0xe2 391 #define PMC6_BR_BOGUS 0xe4 392 #define PMC6_BACLEARS 0xe6 393 394 /* Stalls */ 395 #define PMC6_RESOURCE_STALLS 0xa2 396 #define PMC6_PARTIAL_RAT_STALLS 0xd2 397 398 /* Segment Register Loads */ 399 #define PMC6_SEGMENT_REG_LOADS 0x06 400 401 /* Clocks */ 402 #define PMC6_CPU_CLK_UNHALTED 0x79 403 404 /* MMX Unit */ 405 #define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */ 406 #define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */ 407 #define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */ 408 #define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */ 409 #define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */ 410 #define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */ 411 #define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */ 412 413 /* Segment Register Renaming */ 414 #define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */ 415 #define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */ 416 #define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */ 417
Indexes created Thu Oct 23 22:10:10 GMT 2025