elan520.c revision 1.10
1 /* $NetBSD: elan520.c,v 1.10 2005/10/11 15:58:37 drochner Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.10 2005/10/11 15:58:37 drochner Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/wdog.h> 56 #include <sys/gpio.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #include "gpio.h" 67 #if NGPIO > 0 68 #include <dev/gpio/gpiovar.h> 69 #endif 70 71 #include <arch/i386/pci/elan520reg.h> 72 73 #include <dev/sysmon/sysmonvar.h> 74 75 struct elansc_softc { 76 struct device sc_dev; 77 bus_space_tag_t sc_memt; 78 bus_space_handle_t sc_memh; 79 int sc_echobug; 80 81 struct sysmon_wdog sc_smw; 82 /* GPIO interface */ 83 struct gpio_chipset_tag sc_gpio_gc; 84 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 85 }; 86 87 #if NGPIO > 0 88 static int elansc_gpio_pin_read(void *, int); 89 static void elansc_gpio_pin_write(void *, int, int); 90 static void elansc_gpio_pin_ctl(void *, int, int); 91 #endif 92 93 static void 94 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 95 { 96 int s; 97 uint8_t echo_mode = 0; /* XXX: gcc */ 98 99 s = splhigh(); 100 101 /* Switch off GP bus echo mode if we need to. */ 102 if (sc->sc_echobug) { 103 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 104 MMCR_GPECHO); 105 bus_space_write_1(sc->sc_memt, sc->sc_memh, 106 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 107 } 108 109 /* Unlock the register. */ 110 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 111 WDTMRCTL_UNLOCK1); 112 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 113 WDTMRCTL_UNLOCK2); 114 115 /* Write the value. */ 116 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 117 118 /* Switch GP bus echo mode back. */ 119 if (sc->sc_echobug) 120 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 121 echo_mode); 122 123 splx(s); 124 } 125 126 static void 127 elansc_wdogctl_reset(struct elansc_softc *sc) 128 { 129 int s; 130 uint8_t echo_mode = 0/* XXX: gcc */; 131 132 s = splhigh(); 133 134 /* Switch off GP bus echo mode if we need to. */ 135 if (sc->sc_echobug) { 136 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 137 MMCR_GPECHO); 138 bus_space_write_1(sc->sc_memt, sc->sc_memh, 139 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 140 } 141 142 /* Reset the watchdog. */ 143 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 144 WDTMRCTL_RESET1); 145 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 146 WDTMRCTL_RESET2); 147 148 /* Switch GP bus echo mode back. */ 149 if (sc->sc_echobug) 150 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 151 echo_mode); 152 153 splx(s); 154 } 155 156 static const struct { 157 int period; /* whole seconds */ 158 uint16_t exp; /* exponent select */ 159 } elansc_wdog_periods[] = { 160 { 1, WDTMRCTL_EXP_SEL25 }, 161 { 2, WDTMRCTL_EXP_SEL26 }, 162 { 4, WDTMRCTL_EXP_SEL27 }, 163 { 8, WDTMRCTL_EXP_SEL28 }, 164 { 16, WDTMRCTL_EXP_SEL29 }, 165 { 32, WDTMRCTL_EXP_SEL30 }, 166 { 0, 0 }, 167 }; 168 169 static int 170 elansc_wdog_setmode(struct sysmon_wdog *smw) 171 { 172 struct elansc_softc *sc = smw->smw_cookie; 173 int i; 174 uint16_t exp_sel = 0; /* XXX: gcc */ 175 176 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 177 elansc_wdogctl_write(sc, 178 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 179 } else { 180 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 181 smw->smw_period = 32; 182 exp_sel = WDTMRCTL_EXP_SEL30; 183 } else { 184 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 185 if (elansc_wdog_periods[i].period == 186 smw->smw_period) { 187 exp_sel = elansc_wdog_periods[i].exp; 188 break; 189 } 190 } 191 if (elansc_wdog_periods[i].period == 0) 192 return (EINVAL); 193 } 194 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 195 WDTMRCTL_WRST_ENB | exp_sel); 196 elansc_wdogctl_reset(sc); 197 } 198 return (0); 199 } 200 201 static int 202 elansc_wdog_tickle(struct sysmon_wdog *smw) 203 { 204 struct elansc_softc *sc = smw->smw_cookie; 205 206 elansc_wdogctl_reset(sc); 207 return (0); 208 } 209 210 static int 211 elansc_match(struct device *parent, struct cfdata *match, void *aux) 212 { 213 struct pci_attach_args *pa = aux; 214 215 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 216 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 217 return (10); /* beat pchb */ 218 219 return (0); 220 } 221 222 static const char *elansc_speeds[] = { 223 "(reserved 00)", 224 "100MHz", 225 "133MHz", 226 "(reserved 11)", 227 }; 228 229 static void 230 elansc_attach(struct device *parent, struct device *self, void *aux) 231 { 232 struct elansc_softc *sc = (void *) self; 233 struct pci_attach_args *pa = aux; 234 uint16_t rev; 235 uint8_t ressta, cpuctl; 236 #if NGPIO > 0 237 struct gpiobus_attach_args gba; 238 int pin; 239 int reg, shift; 240 uint16_t data; 241 #endif 242 243 printf(": AMD Elan SC520 System Controller\n"); 244 245 sc->sc_memt = pa->pa_memt; 246 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 247 &sc->sc_memh) != 0) { 248 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 249 return; 250 } 251 252 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 253 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 254 255 printf("%s: product %d stepping %d.%d, CPU clock %s\n", 256 sc->sc_dev.dv_xname, 257 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 258 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 259 (rev & REVID_MINSTEP), 260 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 261 262 /* 263 * SC520 rev A1 has a bug that affects the watchdog timer. If 264 * the GP bus echo mode is enabled, writing to the watchdog control 265 * register is blocked. 266 * 267 * The BIOS in some systems (e.g. the Soekris net4501) enables 268 * GP bus echo for various reasons, so we need to switch it off 269 * when we talk to the watchdog timer. 270 * 271 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 272 * XXX problem, so we'll just enable it for all Elan SC520s 273 * XXX for now. --thorpej (at) NetBSD.org 274 */ 275 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 276 (0 << REVID_MAJSTEP_SHIFT) | (1))) 277 sc->sc_echobug = 1; 278 279 /* 280 * Determine cause of the last reset, and issue a warning if it 281 * was due to watchdog expiry. 282 */ 283 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 284 if (ressta & RESSTA_WDT_RST_DET) 285 printf("%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", 286 sc->sc_dev.dv_xname); 287 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 288 289 /* 290 * Hook up the watchdog timer. 291 */ 292 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 293 sc->sc_smw.smw_cookie = sc; 294 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 295 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 296 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 297 if (sysmon_wdog_register(&sc->sc_smw) != 0) 298 printf("%s: unable to register watchdog with sysmon\n", 299 sc->sc_dev.dv_xname); 300 301 /* Set up the watchdog registers with some defaults. */ 302 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 303 304 /* ...and clear it. */ 305 elansc_wdogctl_reset(sc); 306 307 #if NGPIO > 0 308 /* Initialize GPIO pins array */ 309 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 310 sc->sc_gpio_pins[pin].pin_num = pin; 311 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 312 GPIO_PIN_OUTPUT; 313 314 /* Read initial state */ 315 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 316 shift = pin % 16; 317 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 318 if ((data & (1 << shift)) == 0) 319 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 320 else 321 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 322 if (elansc_gpio_pin_read(sc, pin) == 0) 323 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 324 else 325 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 326 } 327 328 /* Create controller tag */ 329 sc->sc_gpio_gc.gp_cookie = sc; 330 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 331 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 332 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 333 334 gba.gba_gc = &sc->sc_gpio_gc; 335 gba.gba_pins = sc->sc_gpio_pins; 336 gba.gba_npins = ELANSC_PIO_NPINS; 337 338 /* Attach GPIO framework */ 339 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 340 #endif /* NGPIO */ 341 } 342 343 CFATTACH_DECL(elansc, sizeof(struct elansc_softc), 344 elansc_match, elansc_attach, NULL, NULL); 345 346 #if NGPIO > 0 347 static int 348 elansc_gpio_pin_read(void *arg, int pin) 349 { 350 struct elansc_softc *sc = arg; 351 int reg, shift; 352 u_int16_t data; 353 354 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 355 shift = pin % 16; 356 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 357 358 return ((data >> shift) & 0x1); 359 } 360 361 static void 362 elansc_gpio_pin_write(void *arg, int pin, int value) 363 { 364 struct elansc_softc *sc = arg; 365 int reg, shift; 366 u_int16_t data; 367 368 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 369 shift = pin % 16; 370 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 371 if (value == 0) 372 data &= ~(1 << shift); 373 else if (value == 1) 374 data |= (1 << shift); 375 376 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 377 } 378 379 static void 380 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 381 { 382 struct elansc_softc *sc = arg; 383 int reg, shift; 384 u_int16_t data; 385 386 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 387 shift = pin % 16; 388 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 389 if (flags & GPIO_PIN_INPUT) 390 data &= ~(1 << shift); 391 if (flags & GPIO_PIN_OUTPUT) 392 data |= (1 << shift); 393 394 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 395 } 396 #endif /* NGPIO */ 397
Indexes created Mon Sep 29 21:09:56 GMT 2025