elan520.c revision 1.17
1 /* $NetBSD: elan520.c,v 1.17 2007/12/15 05:37:03 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.17 2007/12/15 05:37:03 dyoung Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/wdog.h> 56 #include <sys/gpio.h> 57 58 #include <uvm/uvm_extern.h> 59 60 #include <machine/bus.h> 61 62 #include <dev/pci/pcivar.h> 63 64 #include <dev/pci/pcidevs.h> 65 66 #include "gpio.h" 67 #if NGPIO > 0 68 #include <dev/gpio/gpiovar.h> 69 #endif 70 71 #include <arch/i386/pci/elan520reg.h> 72 73 #include <dev/sysmon/sysmonvar.h> 74 75 struct elansc_softc { 76 struct device sc_dev; 77 bus_space_tag_t sc_memt; 78 bus_space_handle_t sc_memh; 79 int sc_echobug; 80 81 struct sysmon_wdog sc_smw; 82 #if NGPIO > 0 83 /* GPIO interface */ 84 struct gpio_chipset_tag sc_gpio_gc; 85 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 86 #endif 87 }; 88 89 #if NGPIO > 0 90 static int elansc_gpio_pin_read(void *, int); 91 static void elansc_gpio_pin_write(void *, int, int); 92 static void elansc_gpio_pin_ctl(void *, int, int); 93 #endif 94 95 static void 96 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 97 { 98 int s; 99 uint8_t echo_mode = 0; /* XXX: gcc */ 100 101 s = splhigh(); 102 103 /* Switch off GP bus echo mode if we need to. */ 104 if (sc->sc_echobug) { 105 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 106 MMCR_GPECHO); 107 bus_space_write_1(sc->sc_memt, sc->sc_memh, 108 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 109 } 110 111 /* Unlock the register. */ 112 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 113 WDTMRCTL_UNLOCK1); 114 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 115 WDTMRCTL_UNLOCK2); 116 117 /* Write the value. */ 118 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 119 120 /* Switch GP bus echo mode back. */ 121 if (sc->sc_echobug) 122 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 123 echo_mode); 124 125 splx(s); 126 } 127 128 static void 129 elansc_wdogctl_reset(struct elansc_softc *sc) 130 { 131 int s; 132 uint8_t echo_mode = 0/* XXX: gcc */; 133 134 s = splhigh(); 135 136 /* Switch off GP bus echo mode if we need to. */ 137 if (sc->sc_echobug) { 138 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 139 MMCR_GPECHO); 140 bus_space_write_1(sc->sc_memt, sc->sc_memh, 141 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 142 } 143 144 /* Reset the watchdog. */ 145 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 146 WDTMRCTL_RESET1); 147 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 148 WDTMRCTL_RESET2); 149 150 /* Switch GP bus echo mode back. */ 151 if (sc->sc_echobug) 152 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 153 echo_mode); 154 155 splx(s); 156 } 157 158 static const struct { 159 int period; /* whole seconds */ 160 uint16_t exp; /* exponent select */ 161 } elansc_wdog_periods[] = { 162 { 1, WDTMRCTL_EXP_SEL25 }, 163 { 2, WDTMRCTL_EXP_SEL26 }, 164 { 4, WDTMRCTL_EXP_SEL27 }, 165 { 8, WDTMRCTL_EXP_SEL28 }, 166 { 16, WDTMRCTL_EXP_SEL29 }, 167 { 32, WDTMRCTL_EXP_SEL30 }, 168 { 0, 0 }, 169 }; 170 171 static int 172 elansc_wdog_setmode(struct sysmon_wdog *smw) 173 { 174 struct elansc_softc *sc = smw->smw_cookie; 175 int i; 176 uint16_t exp_sel = 0; /* XXX: gcc */ 177 178 if (!device_has_power(&sc->sc_dev)) 179 return EBUSY; 180 181 if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 182 elansc_wdogctl_write(sc, 183 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 184 } else { 185 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 186 smw->smw_period = 32; 187 exp_sel = WDTMRCTL_EXP_SEL30; 188 } else { 189 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 190 if (elansc_wdog_periods[i].period == 191 smw->smw_period) { 192 exp_sel = elansc_wdog_periods[i].exp; 193 break; 194 } 195 } 196 if (elansc_wdog_periods[i].period == 0) 197 return (EINVAL); 198 } 199 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 200 WDTMRCTL_WRST_ENB | exp_sel); 201 elansc_wdogctl_reset(sc); 202 } 203 return (0); 204 } 205 206 static int 207 elansc_wdog_tickle(struct sysmon_wdog *smw) 208 { 209 struct elansc_softc *sc = smw->smw_cookie; 210 211 if (!device_has_power(&sc->sc_dev)) 212 return EBUSY; 213 214 elansc_wdogctl_reset(sc); 215 return (0); 216 } 217 218 static int 219 elansc_match(struct device *parent, struct cfdata *match, 220 void *aux) 221 { 222 struct pci_attach_args *pa = aux; 223 224 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 225 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 226 return (10); /* beat pchb */ 227 228 return (0); 229 } 230 231 static const char *elansc_speeds[] = { 232 "(reserved 00)", 233 "100MHz", 234 "133MHz", 235 "(reserved 11)", 236 }; 237 238 static bool 239 elansc_suspend(device_t dev) 240 { 241 struct elansc_softc *sc = device_private(dev); 242 243 if ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) != WDOG_MODE_DISARMED) { 244 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 245 return false; 246 } 247 return true; 248 } 249 250 static bool 251 elansc_resume(device_t dev) 252 { 253 struct elansc_softc *sc = device_private(dev); 254 255 /* Set up the watchdog registers with some defaults. */ 256 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 257 258 /* ...and clear it. */ 259 elansc_wdogctl_reset(sc); 260 261 return true; 262 } 263 264 static void 265 elansc_attach(struct device *parent, struct device *self, void *aux) 266 { 267 struct elansc_softc *sc = device_private(self); 268 struct pci_attach_args *pa = aux; 269 uint16_t rev; 270 uint8_t ressta, cpuctl; 271 #if NGPIO > 0 272 struct gpiobus_attach_args gba; 273 int pin; 274 int reg, shift; 275 uint16_t data; 276 #endif 277 278 aprint_naive(": System Controller\n"); 279 aprint_normal(": AMD Elan SC520 System Controller\n"); 280 281 sc->sc_memt = pa->pa_memt; 282 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 283 &sc->sc_memh) != 0) { 284 aprint_error("%s: unable to map registers\n", 285 sc->sc_dev.dv_xname); 286 return; 287 } 288 289 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 290 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 291 292 aprint_normal("%s: product %d stepping %d.%d, CPU clock %s\n", 293 sc->sc_dev.dv_xname, 294 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 295 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 296 (rev & REVID_MINSTEP), 297 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 298 299 /* 300 * SC520 rev A1 has a bug that affects the watchdog timer. If 301 * the GP bus echo mode is enabled, writing to the watchdog control 302 * register is blocked. 303 * 304 * The BIOS in some systems (e.g. the Soekris net4501) enables 305 * GP bus echo for various reasons, so we need to switch it off 306 * when we talk to the watchdog timer. 307 * 308 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 309 * XXX problem, so we'll just enable it for all Elan SC520s 310 * XXX for now. --thorpej (at) NetBSD.org 311 */ 312 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 313 (0 << REVID_MAJSTEP_SHIFT) | (1))) 314 sc->sc_echobug = 1; 315 316 /* 317 * Determine cause of the last reset, and issue a warning if it 318 * was due to watchdog expiry. 319 */ 320 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 321 if (ressta & RESSTA_WDT_RST_DET) 322 aprint_error( 323 "%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", 324 sc->sc_dev.dv_xname); 325 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 326 327 /* 328 * Hook up the watchdog timer. 329 */ 330 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 331 sc->sc_smw.smw_cookie = sc; 332 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 333 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 334 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 335 if (sysmon_wdog_register(&sc->sc_smw) != 0) 336 aprint_error("%s: unable to register watchdog with sysmon\n", 337 sc->sc_dev.dv_xname); 338 339 /* Set up the watchdog registers with some defaults. */ 340 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 341 342 /* ...and clear it. */ 343 elansc_wdogctl_reset(sc); 344 345 pmf_device_register(self, elansc_suspend, elansc_resume); 346 347 #if NGPIO > 0 348 /* Initialize GPIO pins array */ 349 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 350 sc->sc_gpio_pins[pin].pin_num = pin; 351 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 352 GPIO_PIN_OUTPUT; 353 354 /* Read initial state */ 355 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 356 shift = pin % 16; 357 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 358 if ((data & (1 << shift)) == 0) 359 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 360 else 361 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 362 if (elansc_gpio_pin_read(sc, pin) == 0) 363 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 364 else 365 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 366 } 367 368 /* Create controller tag */ 369 sc->sc_gpio_gc.gp_cookie = sc; 370 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 371 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 372 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 373 374 gba.gba_gc = &sc->sc_gpio_gc; 375 gba.gba_pins = sc->sc_gpio_pins; 376 gba.gba_npins = ELANSC_PIO_NPINS; 377 378 /* Attach GPIO framework */ 379 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 380 #endif /* NGPIO */ 381 } 382 383 CFATTACH_DECL(elansc, sizeof(struct elansc_softc), 384 elansc_match, elansc_attach, NULL, NULL); 385 386 #if NGPIO > 0 387 static int 388 elansc_gpio_pin_read(void *arg, int pin) 389 { 390 struct elansc_softc *sc = arg; 391 int reg, shift; 392 uint16_t data; 393 394 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 395 shift = pin % 16; 396 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 397 398 return ((data >> shift) & 0x1); 399 } 400 401 static void 402 elansc_gpio_pin_write(void *arg, int pin, int value) 403 { 404 struct elansc_softc *sc = arg; 405 int reg, shift; 406 uint16_t data; 407 408 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 409 shift = pin % 16; 410 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 411 if (value == 0) 412 data &= ~(1 << shift); 413 else if (value == 1) 414 data |= (1 << shift); 415 416 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 417 } 418 419 static void 420 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 421 { 422 struct elansc_softc *sc = arg; 423 int reg, shift; 424 uint16_t data; 425 426 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 427 shift = pin % 16; 428 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 429 if (flags & GPIO_PIN_INPUT) 430 data &= ~(1 << shift); 431 if (flags & GPIO_PIN_OUTPUT) 432 data |= (1 << shift); 433 434 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 435 } 436 #endif /* NGPIO */ 437
Indexes created Tue Sep 30 11:09:46 GMT 2025