elan520.c revision 1.19
1 /* $NetBSD: elan520.c,v 1.19 2007/12/16 21:14:22 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.19 2007/12/16 21:14:22 dyoung Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/gpio.h> 56 #include <sys/mutex.h> 57 #include <sys/wdog.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 65 #include <dev/pci/pcidevs.h> 66 67 #include "gpio.h" 68 #if NGPIO > 0 69 #include <dev/gpio/gpiovar.h> 70 #endif 71 72 #include <arch/i386/pci/elan520reg.h> 73 74 #include <dev/sysmon/sysmonvar.h> 75 76 struct elansc_softc { 77 struct device sc_dev; 78 bus_space_tag_t sc_memt; 79 bus_space_handle_t sc_memh; 80 int sc_echobug; 81 82 kmutex_t sc_mtx; 83 84 bool sc_suspended; 85 struct sysmon_wdog sc_smw; 86 #if NGPIO > 0 87 /* GPIO interface */ 88 struct gpio_chipset_tag sc_gpio_gc; 89 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 90 #endif 91 }; 92 93 #if NGPIO > 0 94 static int elansc_gpio_pin_read(void *, int); 95 static void elansc_gpio_pin_write(void *, int, int); 96 static void elansc_gpio_pin_ctl(void *, int, int); 97 #endif 98 99 static void 100 elansc_childdetached(device_t self, device_t child) 101 { 102 /* elansc does not presently keep a pointer to children such 103 * as the gpio, so there is nothing to do. 104 */ 105 } 106 107 static void 108 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 109 { 110 uint8_t echo_mode = 0; /* XXX: gcc */ 111 112 KASSERT(mutex_owned(&sc->sc_mtx)); 113 114 /* Switch off GP bus echo mode if we need to. */ 115 if (sc->sc_echobug) { 116 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 117 MMCR_GPECHO); 118 bus_space_write_1(sc->sc_memt, sc->sc_memh, 119 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 120 } 121 122 /* Unlock the register. */ 123 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 124 WDTMRCTL_UNLOCK1); 125 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 126 WDTMRCTL_UNLOCK2); 127 128 /* Write the value. */ 129 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 130 131 /* Switch GP bus echo mode back. */ 132 if (sc->sc_echobug) 133 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 134 echo_mode); 135 } 136 137 static void 138 elansc_wdogctl_reset(struct elansc_softc *sc) 139 { 140 uint8_t echo_mode = 0/* XXX: gcc */; 141 142 KASSERT(mutex_owned(&sc->sc_mtx)); 143 144 /* Switch off GP bus echo mode if we need to. */ 145 if (sc->sc_echobug) { 146 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 147 MMCR_GPECHO); 148 bus_space_write_1(sc->sc_memt, sc->sc_memh, 149 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 150 } 151 152 /* Reset the watchdog. */ 153 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 154 WDTMRCTL_RESET1); 155 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 156 WDTMRCTL_RESET2); 157 158 /* Switch GP bus echo mode back. */ 159 if (sc->sc_echobug) 160 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 161 echo_mode); 162 } 163 164 static const struct { 165 int period; /* whole seconds */ 166 uint16_t exp; /* exponent select */ 167 } elansc_wdog_periods[] = { 168 { 1, WDTMRCTL_EXP_SEL25 }, 169 { 2, WDTMRCTL_EXP_SEL26 }, 170 { 4, WDTMRCTL_EXP_SEL27 }, 171 { 8, WDTMRCTL_EXP_SEL28 }, 172 { 16, WDTMRCTL_EXP_SEL29 }, 173 { 32, WDTMRCTL_EXP_SEL30 }, 174 { 0, 0 }, 175 }; 176 177 static int 178 elansc_wdog_arm(struct elansc_softc *sc) 179 { 180 struct sysmon_wdog *smw = &sc->sc_smw; 181 int i; 182 uint16_t exp_sel = 0; /* XXX: gcc */ 183 184 KASSERT(mutex_owned(&sc->sc_mtx)); 185 186 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 187 smw->smw_period = 32; 188 exp_sel = WDTMRCTL_EXP_SEL30; 189 } else { 190 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 191 if (elansc_wdog_periods[i].period == 192 smw->smw_period) { 193 exp_sel = elansc_wdog_periods[i].exp; 194 break; 195 } 196 } 197 if (elansc_wdog_periods[i].period == 0) 198 return EINVAL; 199 } 200 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 201 WDTMRCTL_WRST_ENB | exp_sel); 202 elansc_wdogctl_reset(sc); 203 return 0; 204 } 205 206 static int 207 elansc_wdog_setmode(struct sysmon_wdog *smw) 208 { 209 struct elansc_softc *sc = smw->smw_cookie; 210 int rc = 0; 211 212 mutex_enter(&sc->sc_mtx); 213 214 if (!device_is_active(&sc->sc_dev)) 215 rc = ENXIO; 216 else if (!device_has_power(&sc->sc_dev) || sc->sc_suspended) 217 rc = EBUSY; 218 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 219 elansc_wdogctl_write(sc, 220 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 221 } else 222 rc = elansc_wdog_arm(sc); 223 224 mutex_exit(&sc->sc_mtx); 225 return rc; 226 } 227 228 static int 229 elansc_wdog_tickle(struct sysmon_wdog *smw) 230 { 231 struct elansc_softc *sc = smw->smw_cookie; 232 233 mutex_enter(&sc->sc_mtx); 234 elansc_wdogctl_reset(sc); 235 mutex_exit(&sc->sc_mtx); 236 return 0; 237 } 238 239 static int 240 elansc_match(struct device *parent, struct cfdata *match, 241 void *aux) 242 { 243 struct pci_attach_args *pa = aux; 244 245 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 246 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 247 return (10); /* beat pchb */ 248 249 return (0); 250 } 251 252 static const char *elansc_speeds[] = { 253 "(reserved 00)", 254 "100MHz", 255 "133MHz", 256 "(reserved 11)", 257 }; 258 259 static bool 260 elansc_suspend(device_t dev) 261 { 262 bool rc; 263 struct elansc_softc *sc = device_private(dev); 264 265 mutex_enter(&sc->sc_mtx); 266 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 267 if (rc) 268 sc->sc_suspended = true; 269 mutex_exit(&sc->sc_mtx); 270 if (!rc) 271 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 272 return rc; 273 } 274 275 static bool 276 elansc_resume(device_t dev) 277 { 278 struct elansc_softc *sc = device_private(dev); 279 280 mutex_enter(&sc->sc_mtx); 281 sc->sc_suspended = false; 282 /* Set up the watchdog registers with some defaults. */ 283 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 284 285 /* ...and clear it. */ 286 elansc_wdogctl_reset(sc); 287 mutex_exit(&sc->sc_mtx); 288 289 return true; 290 } 291 292 static int 293 elansc_detach(device_t self, int flags) 294 { 295 int rc; 296 struct elansc_softc *sc = device_private(self); 297 298 if ((rc = config_detach_children(self, flags)) != 0) 299 return rc; 300 301 pmf_device_deregister(self); 302 303 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 304 if (rc == ERESTART) 305 rc = EINTR; 306 return rc; 307 } 308 309 mutex_enter(&sc->sc_mtx); 310 311 /* Set up the watchdog registers with some defaults. */ 312 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 313 314 /* ...and clear it. */ 315 elansc_wdogctl_reset(sc); 316 317 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 318 319 mutex_exit(&sc->sc_mtx); 320 mutex_destroy(&sc->sc_mtx); 321 return 0; 322 } 323 324 static void 325 elansc_attach(struct device *parent, struct device *self, void *aux) 326 { 327 struct elansc_softc *sc = device_private(self); 328 struct pci_attach_args *pa = aux; 329 uint16_t rev; 330 uint8_t ressta, cpuctl; 331 #if NGPIO > 0 332 struct gpiobus_attach_args gba; 333 int pin; 334 int reg, shift; 335 uint16_t data; 336 #endif 337 338 aprint_naive(": System Controller\n"); 339 aprint_normal(": AMD Elan SC520 System Controller\n"); 340 341 sc->sc_memt = pa->pa_memt; 342 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 343 &sc->sc_memh) != 0) { 344 aprint_error("%s: unable to map registers\n", 345 sc->sc_dev.dv_xname); 346 return; 347 } 348 349 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 350 351 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 352 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 353 354 aprint_normal("%s: product %d stepping %d.%d, CPU clock %s\n", 355 sc->sc_dev.dv_xname, 356 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 357 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 358 (rev & REVID_MINSTEP), 359 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 360 361 /* 362 * SC520 rev A1 has a bug that affects the watchdog timer. If 363 * the GP bus echo mode is enabled, writing to the watchdog control 364 * register is blocked. 365 * 366 * The BIOS in some systems (e.g. the Soekris net4501) enables 367 * GP bus echo for various reasons, so we need to switch it off 368 * when we talk to the watchdog timer. 369 * 370 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 371 * XXX problem, so we'll just enable it for all Elan SC520s 372 * XXX for now. --thorpej (at) NetBSD.org 373 */ 374 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 375 (0 << REVID_MAJSTEP_SHIFT) | (1))) 376 sc->sc_echobug = 1; 377 378 /* 379 * Determine cause of the last reset, and issue a warning if it 380 * was due to watchdog expiry. 381 */ 382 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 383 if (ressta & RESSTA_WDT_RST_DET) 384 aprint_error( 385 "%s: WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n", 386 sc->sc_dev.dv_xname); 387 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 388 389 /* Set up the watchdog registers with some defaults. */ 390 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 391 392 /* ...and clear it. */ 393 elansc_wdogctl_reset(sc); 394 395 pmf_device_register(self, elansc_suspend, elansc_resume); 396 397 #if NGPIO > 0 398 /* Initialize GPIO pins array */ 399 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 400 sc->sc_gpio_pins[pin].pin_num = pin; 401 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 402 GPIO_PIN_OUTPUT; 403 404 /* Read initial state */ 405 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 406 shift = pin % 16; 407 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 408 if ((data & (1 << shift)) == 0) 409 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 410 else 411 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 412 if (elansc_gpio_pin_read(sc, pin) == 0) 413 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 414 else 415 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 416 } 417 418 /* Create controller tag */ 419 sc->sc_gpio_gc.gp_cookie = sc; 420 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 421 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 422 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 423 424 gba.gba_gc = &sc->sc_gpio_gc; 425 gba.gba_pins = sc->sc_gpio_pins; 426 gba.gba_npins = ELANSC_PIO_NPINS; 427 428 /* Attach GPIO framework */ 429 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 430 #endif /* NGPIO */ 431 432 /* 433 * Hook up the watchdog timer. 434 */ 435 sc->sc_smw.smw_name = sc->sc_dev.dv_xname; 436 sc->sc_smw.smw_cookie = sc; 437 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 438 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 439 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 440 if (sysmon_wdog_register(&sc->sc_smw) != 0) 441 aprint_error("%s: unable to register watchdog with sysmon\n", 442 sc->sc_dev.dv_xname); 443 } 444 445 CFATTACH_DECL2(elansc, sizeof(struct elansc_softc), 446 elansc_match, elansc_attach, elansc_detach, NULL, NULL, 447 elansc_childdetached); 448 449 #if NGPIO > 0 450 static int 451 elansc_gpio_pin_read(void *arg, int pin) 452 { 453 struct elansc_softc *sc = arg; 454 int reg, shift; 455 uint16_t data; 456 457 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 458 shift = pin % 16; 459 460 mutex_enter(&sc->sc_mtx); 461 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 462 mutex_exit(&sc->sc_mtx); 463 464 return ((data >> shift) & 0x1); 465 } 466 467 static void 468 elansc_gpio_pin_write(void *arg, int pin, int value) 469 { 470 struct elansc_softc *sc = arg; 471 int reg, shift; 472 uint16_t data; 473 474 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 475 shift = pin % 16; 476 477 mutex_enter(&sc->sc_mtx); 478 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 479 if (value == 0) 480 data &= ~(1 << shift); 481 else if (value == 1) 482 data |= (1 << shift); 483 484 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 485 mutex_exit(&sc->sc_mtx); 486 } 487 488 static void 489 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 490 { 491 struct elansc_softc *sc = arg; 492 int reg, shift; 493 uint16_t data; 494 495 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 496 shift = pin % 16; 497 mutex_enter(&sc->sc_mtx); 498 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 499 if (flags & GPIO_PIN_INPUT) 500 data &= ~(1 << shift); 501 if (flags & GPIO_PIN_OUTPUT) 502 data |= (1 << shift); 503 504 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 505 mutex_exit(&sc->sc_mtx); 506 } 507 #endif /* NGPIO */ 508
Indexes created Mon Sep 29 21:09:56 GMT 2025