elan520.c revision 1.21
1 /* $NetBSD: elan520.c,v 1.21 2008/01/08 04:47:44 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.21 2008/01/08 04:47:44 dyoung Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/device.h> 55 #include <sys/gpio.h> 56 #include <sys/mutex.h> 57 #include <sys/wdog.h> 58 59 #include <uvm/uvm_extern.h> 60 61 #include <machine/bus.h> 62 63 #include <dev/pci/pcivar.h> 64 65 #include <dev/pci/pcidevs.h> 66 67 #include "gpio.h" 68 #if NGPIO > 0 69 #include <dev/gpio/gpiovar.h> 70 #endif 71 72 #include <arch/i386/pci/elan520reg.h> 73 74 #include <dev/sysmon/sysmonvar.h> 75 76 struct elansc_softc { 77 struct device sc_dev; 78 bus_space_tag_t sc_memt; 79 bus_space_handle_t sc_memh; 80 int sc_echobug; 81 82 kmutex_t sc_mtx; 83 84 struct sysmon_wdog sc_smw; 85 #if NGPIO > 0 86 /* GPIO interface */ 87 struct gpio_chipset_tag sc_gpio_gc; 88 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 89 #endif 90 }; 91 92 #if NGPIO > 0 93 static int elansc_gpio_pin_read(void *, int); 94 static void elansc_gpio_pin_write(void *, int, int); 95 static void elansc_gpio_pin_ctl(void *, int, int); 96 #endif 97 98 static void 99 elansc_childdetached(device_t self, device_t child) 100 { 101 /* elansc does not presently keep a pointer to children such 102 * as the gpio, so there is nothing to do. 103 */ 104 } 105 106 static void 107 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 108 { 109 uint8_t echo_mode = 0; /* XXX: gcc */ 110 111 KASSERT(mutex_owned(&sc->sc_mtx)); 112 113 /* Switch off GP bus echo mode if we need to. */ 114 if (sc->sc_echobug) { 115 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 116 MMCR_GPECHO); 117 bus_space_write_1(sc->sc_memt, sc->sc_memh, 118 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 119 } 120 121 /* Unlock the register. */ 122 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 123 WDTMRCTL_UNLOCK1); 124 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 125 WDTMRCTL_UNLOCK2); 126 127 /* Write the value. */ 128 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 129 130 /* Switch GP bus echo mode back. */ 131 if (sc->sc_echobug) 132 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 133 echo_mode); 134 } 135 136 static void 137 elansc_wdogctl_reset(struct elansc_softc *sc) 138 { 139 uint8_t echo_mode = 0/* XXX: gcc */; 140 141 KASSERT(mutex_owned(&sc->sc_mtx)); 142 143 /* Switch off GP bus echo mode if we need to. */ 144 if (sc->sc_echobug) { 145 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 146 MMCR_GPECHO); 147 bus_space_write_1(sc->sc_memt, sc->sc_memh, 148 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 149 } 150 151 /* Reset the watchdog. */ 152 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 153 WDTMRCTL_RESET1); 154 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 155 WDTMRCTL_RESET2); 156 157 /* Switch GP bus echo mode back. */ 158 if (sc->sc_echobug) 159 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 160 echo_mode); 161 } 162 163 static const struct { 164 int period; /* whole seconds */ 165 uint16_t exp; /* exponent select */ 166 } elansc_wdog_periods[] = { 167 { 1, WDTMRCTL_EXP_SEL25 }, 168 { 2, WDTMRCTL_EXP_SEL26 }, 169 { 4, WDTMRCTL_EXP_SEL27 }, 170 { 8, WDTMRCTL_EXP_SEL28 }, 171 { 16, WDTMRCTL_EXP_SEL29 }, 172 { 32, WDTMRCTL_EXP_SEL30 }, 173 { 0, 0 }, 174 }; 175 176 static int 177 elansc_wdog_arm(struct elansc_softc *sc) 178 { 179 struct sysmon_wdog *smw = &sc->sc_smw; 180 int i; 181 uint16_t exp_sel = 0; /* XXX: gcc */ 182 183 KASSERT(mutex_owned(&sc->sc_mtx)); 184 185 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 186 smw->smw_period = 32; 187 exp_sel = WDTMRCTL_EXP_SEL30; 188 } else { 189 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 190 if (elansc_wdog_periods[i].period == 191 smw->smw_period) { 192 exp_sel = elansc_wdog_periods[i].exp; 193 break; 194 } 195 } 196 if (elansc_wdog_periods[i].period == 0) 197 return EINVAL; 198 } 199 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 200 WDTMRCTL_WRST_ENB | exp_sel); 201 elansc_wdogctl_reset(sc); 202 return 0; 203 } 204 205 static int 206 elansc_wdog_setmode(struct sysmon_wdog *smw) 207 { 208 struct elansc_softc *sc = smw->smw_cookie; 209 int rc = 0; 210 211 mutex_enter(&sc->sc_mtx); 212 213 if (!device_is_active(&sc->sc_dev)) 214 rc = EBUSY; 215 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 216 elansc_wdogctl_write(sc, 217 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 218 } else 219 rc = elansc_wdog_arm(sc); 220 221 mutex_exit(&sc->sc_mtx); 222 return rc; 223 } 224 225 static int 226 elansc_wdog_tickle(struct sysmon_wdog *smw) 227 { 228 struct elansc_softc *sc = smw->smw_cookie; 229 230 mutex_enter(&sc->sc_mtx); 231 elansc_wdogctl_reset(sc); 232 mutex_exit(&sc->sc_mtx); 233 return 0; 234 } 235 236 static int 237 elansc_match(device_t parent, struct cfdata *match, void *aux) 238 { 239 struct pci_attach_args *pa = aux; 240 241 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 242 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 243 return (10); /* beat pchb */ 244 245 return (0); 246 } 247 248 static const char *elansc_speeds[] = { 249 "(reserved 00)", 250 "100MHz", 251 "133MHz", 252 "(reserved 11)", 253 }; 254 255 static bool 256 elansc_suspend(device_t dev) 257 { 258 bool rc; 259 struct elansc_softc *sc = device_private(dev); 260 261 mutex_enter(&sc->sc_mtx); 262 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 263 mutex_exit(&sc->sc_mtx); 264 if (!rc) 265 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 266 return rc; 267 } 268 269 static bool 270 elansc_resume(device_t dev) 271 { 272 struct elansc_softc *sc = device_private(dev); 273 274 mutex_enter(&sc->sc_mtx); 275 /* Set up the watchdog registers with some defaults. */ 276 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 277 278 /* ...and clear it. */ 279 elansc_wdogctl_reset(sc); 280 mutex_exit(&sc->sc_mtx); 281 282 return true; 283 } 284 285 static int 286 elansc_detach(device_t self, int flags) 287 { 288 int rc; 289 struct elansc_softc *sc = device_private(self); 290 291 if ((rc = config_detach_children(self, flags)) != 0) 292 return rc; 293 294 pmf_device_deregister(self); 295 296 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 297 if (rc == ERESTART) 298 rc = EINTR; 299 return rc; 300 } 301 302 mutex_enter(&sc->sc_mtx); 303 304 /* Set up the watchdog registers with some defaults. */ 305 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 306 307 /* ...and clear it. */ 308 elansc_wdogctl_reset(sc); 309 310 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 311 312 mutex_exit(&sc->sc_mtx); 313 mutex_destroy(&sc->sc_mtx); 314 return 0; 315 } 316 317 static void 318 elansc_attach(device_t parent, device_t self, void *aux) 319 { 320 struct elansc_softc *sc = device_private(self); 321 struct pci_attach_args *pa = aux; 322 uint16_t rev; 323 uint8_t ressta, cpuctl; 324 #if NGPIO > 0 325 struct gpiobus_attach_args gba; 326 int pin; 327 int reg, shift; 328 uint16_t data; 329 #endif 330 331 aprint_naive(": System Controller\n"); 332 aprint_normal(": AMD Elan SC520 System Controller\n"); 333 334 sc->sc_memt = pa->pa_memt; 335 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 336 &sc->sc_memh) != 0) { 337 aprint_error_dev(&sc->sc_dev, "unable to map registers\n"); 338 return; 339 } 340 341 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 342 343 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 344 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 345 346 aprint_normal_dev(&sc->sc_dev, 347 "product %d stepping %d.%d, CPU clock %s\n", 348 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 349 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 350 (rev & REVID_MINSTEP), 351 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 352 353 /* 354 * SC520 rev A1 has a bug that affects the watchdog timer. If 355 * the GP bus echo mode is enabled, writing to the watchdog control 356 * register is blocked. 357 * 358 * The BIOS in some systems (e.g. the Soekris net4501) enables 359 * GP bus echo for various reasons, so we need to switch it off 360 * when we talk to the watchdog timer. 361 * 362 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 363 * XXX problem, so we'll just enable it for all Elan SC520s 364 * XXX for now. --thorpej (at) NetBSD.org 365 */ 366 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 367 (0 << REVID_MAJSTEP_SHIFT) | (1))) 368 sc->sc_echobug = 1; 369 370 /* 371 * Determine cause of the last reset, and issue a warning if it 372 * was due to watchdog expiry. 373 */ 374 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 375 if (ressta & RESSTA_WDT_RST_DET) 376 aprint_error_dev(&sc->sc_dev, 377 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 378 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 379 380 /* Set up the watchdog registers with some defaults. */ 381 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 382 383 /* ...and clear it. */ 384 elansc_wdogctl_reset(sc); 385 386 pmf_device_register(self, elansc_suspend, elansc_resume); 387 388 #if NGPIO > 0 389 /* Initialize GPIO pins array */ 390 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 391 sc->sc_gpio_pins[pin].pin_num = pin; 392 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 393 GPIO_PIN_OUTPUT; 394 395 /* Read initial state */ 396 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 397 shift = pin % 16; 398 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 399 if ((data & (1 << shift)) == 0) 400 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 401 else 402 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 403 if (elansc_gpio_pin_read(sc, pin) == 0) 404 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 405 else 406 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 407 } 408 409 /* Create controller tag */ 410 sc->sc_gpio_gc.gp_cookie = sc; 411 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 412 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 413 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 414 415 gba.gba_gc = &sc->sc_gpio_gc; 416 gba.gba_pins = sc->sc_gpio_pins; 417 gba.gba_npins = ELANSC_PIO_NPINS; 418 419 /* Attach GPIO framework */ 420 config_found_ia(&sc->sc_dev, "gpiobus", &gba, gpiobus_print); 421 #endif /* NGPIO */ 422 423 /* 424 * Hook up the watchdog timer. 425 */ 426 sc->sc_smw.smw_name = device_xname(&sc->sc_dev); 427 sc->sc_smw.smw_cookie = sc; 428 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 429 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 430 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 431 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 432 aprint_error_dev(&sc->sc_dev, 433 "unable to register watchdog with sysmon\n"); 434 } 435 } 436 437 CFATTACH_DECL2(elansc, sizeof(struct elansc_softc), 438 elansc_match, elansc_attach, elansc_detach, NULL, NULL, 439 elansc_childdetached); 440 441 #if NGPIO > 0 442 static int 443 elansc_gpio_pin_read(void *arg, int pin) 444 { 445 struct elansc_softc *sc = arg; 446 int reg, shift; 447 uint16_t data; 448 449 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 450 shift = pin % 16; 451 452 mutex_enter(&sc->sc_mtx); 453 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 454 mutex_exit(&sc->sc_mtx); 455 456 return ((data >> shift) & 0x1); 457 } 458 459 static void 460 elansc_gpio_pin_write(void *arg, int pin, int value) 461 { 462 struct elansc_softc *sc = arg; 463 int reg, shift; 464 uint16_t data; 465 466 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 467 shift = pin % 16; 468 469 mutex_enter(&sc->sc_mtx); 470 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 471 if (value == 0) 472 data &= ~(1 << shift); 473 else if (value == 1) 474 data |= (1 << shift); 475 476 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 477 mutex_exit(&sc->sc_mtx); 478 } 479 480 static void 481 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 482 { 483 struct elansc_softc *sc = arg; 484 int reg, shift; 485 uint16_t data; 486 487 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 488 shift = pin % 16; 489 mutex_enter(&sc->sc_mtx); 490 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 491 if (flags & GPIO_PIN_INPUT) 492 data &= ~(1 << shift); 493 if (flags & GPIO_PIN_OUTPUT) 494 data |= (1 << shift); 495 496 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 497 mutex_exit(&sc->sc_mtx); 498 } 499 #endif /* NGPIO */ 500
Indexes created Mon Sep 29 21:09:56 GMT 2025