elan520.c revision 1.29
1 /* $NetBSD: elan520.c,v 1.29 2008/04/07 03:57:51 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.29 2008/04/07 03:57:51 dyoung Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/time.h> 55 #include <sys/device.h> 56 #include <sys/gpio.h> 57 #include <sys/mutex.h> 58 #include <sys/wdog.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <machine/bus.h> 63 64 #include <dev/pci/pcivar.h> 65 66 #include <dev/pci/pcidevs.h> 67 68 #include "gpio.h" 69 #if NGPIO > 0 70 #include <dev/gpio/gpiovar.h> 71 #endif 72 73 #include <arch/i386/pci/elan520reg.h> 74 75 #include <dev/sysmon/sysmonvar.h> 76 77 #define ELAN_IRQ 1 78 #define PG0_PROT_SIZE PAGE_SIZE 79 80 struct elansc_softc { 81 device_t sc_dev; 82 device_t sc_par; 83 device_t sc_pex; 84 85 pci_chipset_tag_t sc_pc; 86 pcitag_t sc_tag; 87 bus_space_tag_t sc_memt; 88 bus_space_handle_t sc_memh; 89 int sc_echobug; 90 91 kmutex_t sc_mtx; 92 93 struct sysmon_wdog sc_smw; 94 void *sc_eih; 95 void *sc_pih; 96 void *sc_sh; 97 uint8_t sc_mpicmode; 98 uint8_t sc_picicr; 99 int sc_pg0par; 100 int sc_textpar[3]; 101 #if NGPIO > 0 102 /* GPIO interface */ 103 struct gpio_chipset_tag sc_gpio_gc; 104 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 105 #endif 106 }; 107 108 int elansc_wpvnmi = 1; 109 int elansc_pcinmi = 1; 110 int elansc_do_protect_pg0 = 1; 111 112 #if NGPIO > 0 113 static int elansc_gpio_pin_read(void *, int); 114 static void elansc_gpio_pin_write(void *, int, int); 115 static void elansc_gpio_pin_ctl(void *, int, int); 116 #endif 117 118 static void elansc_print_par(device_t, int, uint32_t); 119 static void elanpex_intr_establish(device_t, struct elansc_softc *); 120 static void elanpar_intr_establish(device_t, struct elansc_softc *); 121 static void elanpex_intr_disestablish(struct elansc_softc *); 122 static void elanpar_intr_disestablish(struct elansc_softc *); 123 static bool elanpar_shutdown(device_t, int); 124 static bool elanpex_shutdown(device_t, int); 125 126 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 127 128 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 129 130 static void 131 elansc_childdetached(device_t self, device_t child) 132 { 133 struct elansc_softc *sc = device_private(self); 134 135 if (child == sc->sc_par) 136 sc->sc_par = NULL; 137 if (child == sc->sc_pex) 138 sc->sc_pex = NULL; 139 /* elansc does not presently keep a pointer to 140 * the gpio, so there is nothing to do if it is detached. 141 */ 142 } 143 144 static void 145 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 146 { 147 uint8_t echo_mode = 0; /* XXX: gcc */ 148 149 KASSERT(mutex_owned(&sc->sc_mtx)); 150 151 /* Switch off GP bus echo mode if we need to. */ 152 if (sc->sc_echobug) { 153 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 154 MMCR_GPECHO); 155 bus_space_write_1(sc->sc_memt, sc->sc_memh, 156 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 157 } 158 159 /* Unlock the register. */ 160 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 161 WDTMRCTL_UNLOCK1); 162 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 163 WDTMRCTL_UNLOCK2); 164 165 /* Write the value. */ 166 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 167 168 /* Switch GP bus echo mode back. */ 169 if (sc->sc_echobug) 170 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 171 echo_mode); 172 } 173 174 static void 175 elansc_wdogctl_reset(struct elansc_softc *sc) 176 { 177 uint8_t echo_mode = 0/* XXX: gcc */; 178 179 KASSERT(mutex_owned(&sc->sc_mtx)); 180 181 /* Switch off GP bus echo mode if we need to. */ 182 if (sc->sc_echobug) { 183 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 184 MMCR_GPECHO); 185 bus_space_write_1(sc->sc_memt, sc->sc_memh, 186 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 187 } 188 189 /* Reset the watchdog. */ 190 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 191 WDTMRCTL_RESET1); 192 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 193 WDTMRCTL_RESET2); 194 195 /* Switch GP bus echo mode back. */ 196 if (sc->sc_echobug) 197 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 198 echo_mode); 199 } 200 201 static const struct { 202 int period; /* whole seconds */ 203 uint16_t exp; /* exponent select */ 204 } elansc_wdog_periods[] = { 205 { 1, WDTMRCTL_EXP_SEL25 }, 206 { 2, WDTMRCTL_EXP_SEL26 }, 207 { 4, WDTMRCTL_EXP_SEL27 }, 208 { 8, WDTMRCTL_EXP_SEL28 }, 209 { 16, WDTMRCTL_EXP_SEL29 }, 210 { 32, WDTMRCTL_EXP_SEL30 }, 211 { 0, 0 }, 212 }; 213 214 static int 215 elansc_wdog_arm(struct elansc_softc *sc) 216 { 217 struct sysmon_wdog *smw = &sc->sc_smw; 218 int i; 219 uint16_t exp_sel = 0; /* XXX: gcc */ 220 221 KASSERT(mutex_owned(&sc->sc_mtx)); 222 223 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 224 smw->smw_period = 32; 225 exp_sel = WDTMRCTL_EXP_SEL30; 226 } else { 227 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 228 if (elansc_wdog_periods[i].period == 229 smw->smw_period) { 230 exp_sel = elansc_wdog_periods[i].exp; 231 break; 232 } 233 } 234 if (elansc_wdog_periods[i].period == 0) 235 return EINVAL; 236 } 237 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 238 WDTMRCTL_WRST_ENB | exp_sel); 239 elansc_wdogctl_reset(sc); 240 return 0; 241 } 242 243 static int 244 elansc_wdog_setmode(struct sysmon_wdog *smw) 245 { 246 struct elansc_softc *sc = smw->smw_cookie; 247 int rc = 0; 248 249 mutex_enter(&sc->sc_mtx); 250 251 if (!device_is_active(sc->sc_dev)) 252 rc = EBUSY; 253 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 254 elansc_wdogctl_write(sc, 255 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 256 } else 257 rc = elansc_wdog_arm(sc); 258 259 mutex_exit(&sc->sc_mtx); 260 return rc; 261 } 262 263 static int 264 elansc_wdog_tickle(struct sysmon_wdog *smw) 265 { 266 struct elansc_softc *sc = smw->smw_cookie; 267 268 mutex_enter(&sc->sc_mtx); 269 elansc_wdogctl_reset(sc); 270 mutex_exit(&sc->sc_mtx); 271 return 0; 272 } 273 274 static int 275 elansc_match(device_t parent, struct cfdata *match, void *aux) 276 { 277 struct pci_attach_args *pa = aux; 278 279 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_AMD && 280 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_AMD_SC520_SC) 281 return (10); /* beat pchb */ 282 283 return (0); 284 } 285 286 static const char *elansc_speeds[] = { 287 "(reserved 00)", 288 "100MHz", 289 "133MHz", 290 "(reserved 11)", 291 }; 292 293 static int 294 elanpar_intr(void *arg) 295 { 296 struct elansc_softc *sc = arg; 297 uint16_t wpvsta; 298 unsigned win; 299 uint32_t par; 300 const char *wpvstr; 301 302 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 303 304 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 305 return 0; 306 307 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 308 309 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 310 311 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 312 MMCR_WPVSTA_WPV_STA); 313 314 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 315 case MMCR_WPVSTA_WPV_MSTR_CPU: 316 wpvstr = "cpu"; 317 break; 318 case MMCR_WPVSTA_WPV_MSTR_PCI: 319 wpvstr = "pci"; 320 break; 321 case MMCR_WPVSTA_WPV_MSTR_GP: 322 wpvstr = "gp"; 323 break; 324 default: 325 wpvstr = "unknown"; 326 break; 327 } 328 aprint_error_dev(sc->sc_par, 329 "%s violated write-protect window %u\n", wpvstr, win); 330 elansc_print_par(sc->sc_par, win, par); 331 return 0; 332 } 333 334 static int 335 elanpex_intr(void *arg) 336 { 337 static struct { 338 const char *string; 339 bool nonfatal; 340 } cmd[16] = { 341 [0] = {.string = "not latched"} 342 , [1] = {.string = "special cycle"} 343 , [2] = {.string = "i/o read"} 344 , [3] = {.string = "i/o write"} 345 , [4] = {.string = "4"} 346 , [5] = {.string = "5"} 347 , [6] = {.string = "memory rd"} 348 , [7] = {.string = "memory wr"} 349 , [8] = {.string = "8"} 350 , [9] = {.string = "9"} 351 , [10] = {.string = "cfg rd", .nonfatal = true} 352 , [11] = {.string = "cfg wr"} 353 , [12] = {.string = "memory rd mul"} 354 , [13] = {.string = "dual-address cycle"} 355 , [14] = {.string = "memory rd line"} 356 , [15] = {.string = "memory wr & inv"} 357 }; 358 359 static const struct { 360 uint16_t bit; 361 const char *msg; 362 } mmsg[] = { 363 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 364 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 365 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 366 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 367 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 368 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 369 }, tmsg[] = { 370 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 371 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 372 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 373 }; 374 uint8_t pciarbsta; 375 uint16_t mstcmd, mstirq, tgtid, tgtirq; 376 uint32_t mstaddr; 377 uint16_t mstack = 0, tgtack = 0; 378 int fatal = 0, i, handled = 0; 379 struct elansc_softc *sc = arg; 380 381 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 382 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 383 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 384 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 385 386 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 387 aprint_error_dev(sc->sc_pex, 388 "grant time-out, GNT%" __PRIuBITS "# asserted\n", 389 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 390 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 391 MMCR_PCIARBSTA_GNT_TO_STA); 392 handled = true; 393 } 394 395 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 396 397 for (i = 0; i < __arraycount(mmsg); i++) { 398 if ((mstirq & mmsg[i].bit) == 0) 399 continue; 400 aprint_error_dev(sc->sc_pex, 401 "%s %08" PRIx32 " master %s\n", 402 cmd[mstcmd].string, mstaddr, mmsg[i].msg); 403 404 mstack |= mmsg[i].bit; 405 if (!cmd[mstcmd].nonfatal) 406 fatal = true; 407 } 408 409 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 410 411 for (i = 0; i < __arraycount(tmsg); i++) { 412 if ((tgtirq & tmsg[i].bit) == 0) 413 continue; 414 aprint_error_dev(sc->sc_pex, "%1x target %s\n", tgtid, 415 tmsg[i].msg); 416 tgtack |= tmsg[i].bit; 417 } 418 419 /* acknowledge interrupts */ 420 if (tgtack != 0) { 421 handled = true; 422 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 423 tgtack); 424 } 425 if (mstack != 0) { 426 handled = true; 427 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 428 mstack); 429 } 430 return fatal ? 0 : (handled ? 1 : 0); 431 } 432 433 #define elansc_print_1(__dev, __sc, __reg) \ 434 do { \ 435 aprint_debug_dev(__dev, \ 436 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 437 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 438 } while (/*CONSTCOND*/0) 439 440 static void 441 elansc_print_par(device_t dev, int i, uint32_t par) 442 { 443 uint32_t addr, sz, unit; 444 const char *tgtstr; 445 446 switch (par & MMCR_PAR_TARGET) { 447 default: 448 case MMCR_PAR_TARGET_OFF: 449 tgtstr = "off"; 450 break; 451 case MMCR_PAR_TARGET_GPIO: 452 tgtstr = "gpio"; 453 break; 454 case MMCR_PAR_TARGET_GPMEM: 455 tgtstr = "gpmem"; 456 break; 457 case MMCR_PAR_TARGET_PCI: 458 tgtstr = "pci"; 459 break; 460 case MMCR_PAR_TARGET_BOOTCS: 461 tgtstr = "bootcs"; 462 break; 463 case MMCR_PAR_TARGET_ROMCS1: 464 tgtstr = "romcs1"; 465 break; 466 case MMCR_PAR_TARGET_ROMCS2: 467 tgtstr = "romcs2"; 468 break; 469 case MMCR_PAR_TARGET_SDRAM: 470 tgtstr = "sdram"; 471 break; 472 } 473 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 474 unit = 1; 475 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 476 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 477 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 478 unit = 64 * 1024; 479 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 480 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 481 } else { 482 unit = 4 * 1024; 483 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 484 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 485 } 486 487 aprint_debug_dev(dev, 488 "PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 489 " start %08" PRIx32 " size %" PRIu32 "\n", 490 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 491 addr * unit, (sz + 1) * unit); 492 } 493 494 static void 495 elansc_print_all_par(device_t dev, 496 bus_space_tag_t memt, bus_space_handle_t memh) 497 { 498 int i; 499 uint32_t par; 500 501 for (i = 0; i < 16; i++) { 502 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 503 elansc_print_par(dev, i, par); 504 } 505 } 506 507 static int 508 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 509 { 510 int i; 511 uint32_t par; 512 513 for (i = 0; i < 16; i++) { 514 515 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 516 517 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 518 break; 519 } 520 if (i == 16) 521 return -1; 522 return i; 523 } 524 525 static void 526 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 527 { 528 uint32_t par; 529 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 530 par &= ~MMCR_PAR_TARGET; 531 par |= MMCR_PAR_TARGET_OFF; 532 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 533 } 534 535 struct pareg { 536 paddr_t start; 537 paddr_t end; 538 }; 539 540 static int 541 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 542 { 543 struct pareg *residue = regions; 544 paddr_t start, end; 545 paddr_t start0, end0; 546 547 start0 = region0->start; 548 end0 = region0->end; 549 550 if (start0 % unit != 0) 551 start = start0 + unit - start0 % unit; 552 else 553 start = start0; 554 555 end = end0 - end0 % unit; 556 557 if (start >= end) 558 return 0; 559 560 residue->start = start; 561 residue->end = end; 562 residue++; 563 564 if (start0 < start) { 565 residue->start = start0; 566 residue->end = start; 567 residue++; 568 } 569 if (end < end0) { 570 residue->start = end; 571 residue->end = end0; 572 residue++; 573 } 574 return residue - regions; 575 } 576 577 static void 578 elansc_protect_text(device_t self, struct elansc_softc *sc) 579 { 580 int i, j, nregion, pidx, tidx = 0, xnregion; 581 uint32_t par; 582 uint32_t protsize, unprotsize; 583 paddr_t start_pa, end_pa; 584 extern char kernel_text, etext; 585 bus_space_tag_t memt; 586 bus_space_handle_t memh; 587 struct pareg region0, regions[3], xregions[3]; 588 589 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 590 591 memt = sc->sc_memt; 592 memh = sc->sc_memh; 593 594 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 595 ®ion0.start) || 596 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 597 ®ion0.end)) 598 return; 599 600 if (&etext - &kernel_text != region0.end - region0.start) { 601 aprint_error_dev(self, "kernel text may not be contiguous\n"); 602 return; 603 } 604 605 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 606 aprint_error_dev(self, "cannot allocate PAR\n"); 607 return; 608 } 609 610 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 611 612 aprint_debug_dev(self, 613 "protect kernel text at physical addresses %p - %p\n", 614 (void *)region0.start, (void *)region0.end); 615 616 nregion = region_paddr_to_par(®ion0, regions, sfkb); 617 if (nregion == 0) { 618 aprint_error_dev(self, "kernel text is unprotected\n"); 619 return; 620 } 621 622 unprotsize = 0; 623 for (i = 1; i < nregion; i++) 624 unprotsize += regions[i].end - regions[i].start; 625 626 start_pa = regions[0].start; 627 end_pa = regions[0].end; 628 629 aprint_debug_dev(self, 630 "actually protect kernel text at physical addresses %p - %p\n", 631 (void *)start_pa, (void *)end_pa); 632 633 aprint_verbose_dev(self, 634 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 635 636 protsize = end_pa - start_pa; 637 638 #if 0 639 /* set PG_SZ, attribute, target, size, address. */ 640 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 641 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 642 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 643 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 644 #else 645 elansc_protect(sc, pidx, start_pa, protsize); 646 #endif 647 648 sc->sc_textpar[tidx++] = pidx; 649 650 unprotsize = 0; 651 for (i = 1; i < nregion; i++) { 652 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 653 if (xnregion == 0) { 654 aprint_verbose_dev(self, "skip region %p - %p\n", 655 (void *)regions[i].start, (void *)regions[i].end); 656 continue; 657 } 658 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 659 unprotsize += regions[i].end - regions[i].start; 660 continue; 661 } 662 elansc_protect(sc, pidx, xregions[0].start, 663 xregions[0].end - xregions[0].start); 664 sc->sc_textpar[tidx++] = pidx; 665 666 aprint_debug_dev(self, 667 "protect add'l kernel text at physical addresses %p - %p\n", 668 (void *)xregions[0].start, (void *)xregions[0].end); 669 670 for (j = 1; j < xnregion; j++) 671 unprotsize += xregions[j].end - xregions[j].start; 672 } 673 aprint_verbose_dev(self, 674 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 675 676 } 677 678 static void 679 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 680 { 681 uint32_t addr_field, blksz, par, size_field; 682 683 /* set attribute, target. */ 684 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 685 686 KASSERT(addr % fkb == 0 && sz % fkb == 0); 687 688 if (addr % sfkb == 0 && sz % sfkb == 0) { 689 par |= MMCR_PAR_PG_SZ; 690 691 size_field = MMCR_PAR_64KB_SZ; 692 addr_field = MMCR_PAR_64KB_ST_ADR; 693 blksz = 64 * 1024; 694 } else { 695 size_field = MMCR_PAR_4KB_SZ; 696 addr_field = MMCR_PAR_4KB_ST_ADR; 697 blksz = 4 * 1024; 698 } 699 700 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 701 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 702 703 /* set size and address. */ 704 par |= __SHIFTIN(sz / blksz - 1, size_field); 705 par |= __SHIFTIN(addr / blksz, addr_field); 706 707 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 708 } 709 710 static int 711 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 712 { 713 int pidx; 714 const paddr_t pg0_paddr = 0; 715 bus_space_tag_t memt; 716 bus_space_handle_t memh; 717 718 memt = sc->sc_memt; 719 memh = sc->sc_memh; 720 721 if (elansc_do_protect_pg0 == 0) 722 return -1; 723 724 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 725 return -1; 726 727 aprint_debug_dev(self, "protect page 0\n"); 728 729 #if 0 730 /* set PG_SZ, attribute, target, size, address. */ 731 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 732 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 733 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 734 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 735 #else 736 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 737 #endif 738 return pidx; 739 } 740 741 static void 742 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 743 { 744 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 745 MMCR_PCIARBSTA_GNT_TO_STA); 746 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 747 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 748 } 749 750 static bool 751 elansc_suspend(device_t dev PMF_FN_ARGS) 752 { 753 bool rc; 754 struct elansc_softc *sc = device_private(dev); 755 756 mutex_enter(&sc->sc_mtx); 757 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 758 mutex_exit(&sc->sc_mtx); 759 if (!rc) 760 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 761 return rc; 762 } 763 764 static bool 765 elansc_resume(device_t dev PMF_FN_ARGS) 766 { 767 struct elansc_softc *sc = device_private(dev); 768 769 mutex_enter(&sc->sc_mtx); 770 /* Set up the watchdog registers with some defaults. */ 771 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 772 773 /* ...and clear it. */ 774 elansc_wdogctl_reset(sc); 775 mutex_exit(&sc->sc_mtx); 776 777 return true; 778 } 779 780 static int 781 elansc_detach(device_t self, int flags) 782 { 783 int rc; 784 struct elansc_softc *sc = device_private(self); 785 786 if ((rc = config_detach_children(self, flags)) != 0) 787 return rc; 788 789 pmf_device_deregister(self); 790 791 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 792 if (rc == ERESTART) 793 rc = EINTR; 794 return rc; 795 } 796 797 mutex_enter(&sc->sc_mtx); 798 799 /* Set up the watchdog registers with some defaults. */ 800 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 801 802 /* ...and clear it. */ 803 elansc_wdogctl_reset(sc); 804 805 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 806 807 mutex_exit(&sc->sc_mtx); 808 mutex_destroy(&sc->sc_mtx); 809 return 0; 810 } 811 812 static void * 813 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 814 { 815 struct pic *pic; 816 void *ih; 817 818 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 819 aprint_error_dev(dev, "PIC for irq %d not found\n", 820 ELAN_IRQ); 821 return NULL; 822 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 823 IST_LEVEL, IPL_HIGH, handler, arg)) == NULL) { 824 aprint_error_dev(dev, 825 "could not establish interrupt\n"); 826 return NULL; 827 } 828 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 829 return ih; 830 } 831 832 static bool 833 elanpex_resume(device_t self PMF_FN_ARGS) 834 { 835 struct elansc_softc *sc = device_private(device_parent(self)); 836 837 elanpex_intr_establish(self, sc); 838 return sc->sc_eih != NULL; 839 } 840 841 static bool 842 elanpex_suspend(device_t self PMF_FN_ARGS) 843 { 844 struct elansc_softc *sc = device_private(device_parent(self)); 845 846 elanpex_intr_disestablish(sc); 847 848 return true; 849 } 850 851 static bool 852 elanpar_resume(device_t self PMF_FN_ARGS) 853 { 854 struct elansc_softc *sc = device_private(device_parent(self)); 855 856 elanpar_intr_establish(self, sc); 857 return sc->sc_pih != NULL; 858 } 859 860 static bool 861 elanpar_suspend(device_t self PMF_FN_ARGS) 862 { 863 struct elansc_softc *sc = device_private(device_parent(self)); 864 865 elanpar_intr_disestablish(sc); 866 867 return true; 868 } 869 870 static void 871 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 872 { 873 uint8_t sysarbctl; 874 uint16_t pcihostmap, mstirq, tgtirq; 875 876 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 877 MMCR_PCIHOSTMAP); 878 /* Priority P2 (Master PIC IR1) */ 879 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 880 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 881 if (elansc_pcinmi) 882 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 883 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 884 pcihostmap); 885 886 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 887 888 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 889 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 890 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 891 892 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 893 894 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 895 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 896 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 897 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 898 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 899 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 900 901 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 902 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 903 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 904 905 if (elansc_pcinmi) { 906 sc->sc_eih = nmi_establish(elanpex_intr, sc); 907 908 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 909 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 910 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 911 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 912 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 913 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 914 915 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 916 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 917 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 918 } else 919 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 920 921 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 922 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 923 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 924 } 925 926 static void 927 elanpex_attach(device_t parent, device_t self, void *aux) 928 { 929 struct elansc_softc *sc = device_private(parent); 930 931 aprint_naive(": PCI Exceptions\n"); 932 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 933 934 elanpex_intr_establish(self, sc); 935 936 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 937 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 938 939 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 940 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 941 942 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 943 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 944 945 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 946 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 947 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 948 949 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 950 elanpex_shutdown)) 951 aprint_error_dev(self, "could not establish power hooks\n"); 952 } 953 954 static bool 955 elanpex_shutdown(device_t self, int flags) 956 { 957 struct elansc_softc *sc = device_private(device_parent(self)); 958 uint8_t sysarbctl; 959 uint16_t pcihostmap, mstirq, tgtirq; 960 961 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 962 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 963 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 964 965 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 966 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 967 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 968 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 969 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 970 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 971 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 972 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 973 974 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 975 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 976 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 977 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 978 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 979 980 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 981 MMCR_PCIHOSTMAP); 982 /* Priority P2 (Master PIC IR1) */ 983 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 984 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 985 pcihostmap); 986 987 return true; 988 } 989 990 static void 991 elanpex_intr_disestablish(struct elansc_softc *sc) 992 { 993 elanpex_shutdown(sc->sc_pex, 0); 994 995 if (elansc_pcinmi) 996 nmi_disestablish(sc->sc_eih); 997 else 998 intr_disestablish(sc->sc_eih); 999 sc->sc_eih = NULL; 1000 1001 } 1002 1003 static int 1004 elanpex_detach(device_t self, int flags) 1005 { 1006 struct elansc_softc *sc = device_private(device_parent(self)); 1007 1008 pmf_device_deregister(self); 1009 elanpex_intr_disestablish(sc); 1010 1011 return 0; 1012 } 1013 1014 static void 1015 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1016 { 1017 uint8_t adddecctl, wpvmap; 1018 1019 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1020 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1021 if (elansc_wpvnmi) 1022 wpvmap |= MMCR_WPVMAP_INT_NMI; 1023 else 1024 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1025 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1026 1027 /* clear interrupt status */ 1028 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1029 MMCR_WPVSTA_WPV_STA); 1030 1031 /* establish interrupt */ 1032 if (elansc_wpvnmi) 1033 sc->sc_pih = nmi_establish(elanpar_intr, sc); 1034 else 1035 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1036 1037 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1038 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1039 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1040 } 1041 1042 static bool 1043 elanpar_shutdown(device_t self, int flags) 1044 { 1045 int i; 1046 struct elansc_softc *sc = device_private(device_parent(self)); 1047 1048 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1049 if (sc->sc_textpar[i] == -1) 1050 continue; 1051 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1052 sc->sc_textpar[i] = -1; 1053 } 1054 if (sc->sc_pg0par != -1) { 1055 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1056 sc->sc_pg0par = -1; 1057 } 1058 return true; 1059 } 1060 1061 static void 1062 elanpar_attach(device_t parent, device_t self, void *aux) 1063 { 1064 struct elansc_softc *sc = device_private(parent); 1065 1066 aprint_naive(": Programmable Address Regions\n"); 1067 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1068 1069 elansc_print_1(self, sc, MMCR_WPVMAP); 1070 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1071 1072 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1073 elansc_protect_text(self, sc); 1074 1075 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1076 1077 elanpar_intr_establish(self, sc); 1078 1079 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1080 1081 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1082 elanpar_shutdown)) 1083 aprint_error_dev(self, "could not establish power hooks\n"); 1084 } 1085 1086 static void 1087 elanpar_intr_disestablish(struct elansc_softc *sc) 1088 { 1089 uint8_t adddecctl, wpvmap; 1090 1091 /* disable interrupt, acknowledge it, disestablish our 1092 * handler, unmap it 1093 */ 1094 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1095 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1096 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1097 1098 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1099 MMCR_WPVSTA_WPV_STA); 1100 1101 if (elansc_wpvnmi) 1102 nmi_disestablish(sc->sc_pih); 1103 else 1104 intr_disestablish(sc->sc_pih); 1105 sc->sc_pih = NULL; 1106 1107 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1108 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1109 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1110 } 1111 1112 static int 1113 elanpar_detach(device_t self, int flags) 1114 { 1115 struct elansc_softc *sc = device_private(device_parent(self)); 1116 1117 pmf_device_deregister(self); 1118 1119 elanpar_shutdown(self, 0); 1120 1121 elanpar_intr_disestablish(sc); 1122 1123 return 0; 1124 } 1125 1126 static void 1127 elansc_attach(device_t parent, device_t self, void *aux) 1128 { 1129 struct elansc_softc *sc = device_private(self); 1130 struct pci_attach_args *pa = aux; 1131 uint16_t rev; 1132 uint8_t cpuctl, picicr, ressta; 1133 #if NGPIO > 0 1134 struct gpiobus_attach_args gba; 1135 int pin, reg, shift; 1136 uint16_t data; 1137 #endif 1138 1139 sc->sc_dev = self; 1140 1141 sc->sc_pc = pa->pa_pc; 1142 sc->sc_tag = pa->pa_tag; 1143 1144 aprint_naive(": System Controller\n"); 1145 aprint_normal(": AMD Elan SC520 System Controller\n"); 1146 1147 sc->sc_memt = pa->pa_memt; 1148 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1149 &sc->sc_memh) != 0) { 1150 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1151 return; 1152 } 1153 1154 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1155 1156 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1157 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1158 1159 aprint_normal_dev(sc->sc_dev, 1160 "product %d stepping %d.%d, CPU clock %s\n", 1161 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1162 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1163 (rev & REVID_MINSTEP), 1164 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1165 1166 /* 1167 * SC520 rev A1 has a bug that affects the watchdog timer. If 1168 * the GP bus echo mode is enabled, writing to the watchdog control 1169 * register is blocked. 1170 * 1171 * The BIOS in some systems (e.g. the Soekris net4501) enables 1172 * GP bus echo for various reasons, so we need to switch it off 1173 * when we talk to the watchdog timer. 1174 * 1175 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1176 * XXX problem, so we'll just enable it for all Elan SC520s 1177 * XXX for now. --thorpej (at) NetBSD.org 1178 */ 1179 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1180 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1181 sc->sc_echobug = 1; 1182 1183 /* 1184 * Determine cause of the last reset, and issue a warning if it 1185 * was due to watchdog expiry. 1186 */ 1187 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1188 if (ressta & RESSTA_WDT_RST_DET) 1189 aprint_error_dev(sc->sc_dev, 1190 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1191 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1192 1193 elansc_print_1(self, sc, MMCR_MPICMODE); 1194 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1195 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1196 elansc_print_1(self, sc, MMCR_PICICR); 1197 1198 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1199 MMCR_MPICMODE); 1200 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1201 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1202 1203 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1204 picicr = sc->sc_picicr; 1205 if (elansc_pcinmi || elansc_wpvnmi) 1206 picicr |= MMCR_PICICR_NMI_ENB; 1207 #if 0 1208 /* PC/AT compatibility */ 1209 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1210 #endif 1211 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1212 1213 elansc_print_1(self, sc, MMCR_PICICR); 1214 elansc_print_1(self, sc, MMCR_MPICMODE); 1215 1216 mutex_enter(&sc->sc_mtx); 1217 /* Set up the watchdog registers with some defaults. */ 1218 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1219 1220 /* ...and clear it. */ 1221 elansc_wdogctl_reset(sc); 1222 mutex_exit(&sc->sc_mtx); 1223 1224 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1225 aprint_error_dev(self, "could not establish power hooks\n"); 1226 1227 #if NGPIO > 0 1228 /* Initialize GPIO pins array */ 1229 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1230 sc->sc_gpio_pins[pin].pin_num = pin; 1231 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1232 GPIO_PIN_OUTPUT; 1233 1234 /* Read initial state */ 1235 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1236 shift = pin % 16; 1237 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1238 if ((data & (1 << shift)) == 0) 1239 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1240 else 1241 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1242 if (elansc_gpio_pin_read(sc, pin) == 0) 1243 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1244 else 1245 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1246 } 1247 1248 /* Create controller tag */ 1249 sc->sc_gpio_gc.gp_cookie = sc; 1250 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1251 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1252 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1253 1254 gba.gba_gc = &sc->sc_gpio_gc; 1255 gba.gba_pins = sc->sc_gpio_pins; 1256 gba.gba_npins = ELANSC_PIO_NPINS; 1257 1258 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1259 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1260 /* Attach GPIO framework */ 1261 config_found_ia(sc->sc_dev, "gpiobus", &gba, gpiobus_print); 1262 #endif /* NGPIO */ 1263 1264 /* 1265 * Hook up the watchdog timer. 1266 */ 1267 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1268 sc->sc_smw.smw_cookie = sc; 1269 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1270 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1271 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1272 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1273 aprint_error_dev(sc->sc_dev, 1274 "unable to register watchdog with sysmon\n"); 1275 } 1276 } 1277 1278 static int 1279 elanpex_match(device_t parent, struct cfdata *match, void *aux) 1280 { 1281 struct elansc_softc *sc = device_private(parent); 1282 1283 return sc->sc_pex == NULL; 1284 } 1285 1286 static int 1287 elanpar_match(device_t parent, struct cfdata *match, void *aux) 1288 { 1289 struct elansc_softc *sc = device_private(parent); 1290 1291 return sc->sc_par == NULL; 1292 } 1293 1294 CFATTACH_DECL_NEW(elanpar, sizeof(struct device), 1295 elanpar_match, elanpar_attach, elanpar_detach, NULL); 1296 1297 CFATTACH_DECL_NEW(elanpex, sizeof(struct device), 1298 elanpex_match, elanpex_attach, elanpex_detach, NULL); 1299 1300 CFATTACH_DECL2_NEW(elansc, sizeof(struct elansc_softc), 1301 elansc_match, elansc_attach, elansc_detach, NULL, NULL, 1302 elansc_childdetached); 1303 1304 #if NGPIO > 0 1305 static int 1306 elansc_gpio_pin_read(void *arg, int pin) 1307 { 1308 struct elansc_softc *sc = arg; 1309 int reg, shift; 1310 uint16_t data; 1311 1312 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1313 shift = pin % 16; 1314 1315 mutex_enter(&sc->sc_mtx); 1316 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1317 mutex_exit(&sc->sc_mtx); 1318 1319 return ((data >> shift) & 0x1); 1320 } 1321 1322 static void 1323 elansc_gpio_pin_write(void *arg, int pin, int value) 1324 { 1325 struct elansc_softc *sc = arg; 1326 int reg, shift; 1327 uint16_t data; 1328 1329 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1330 shift = pin % 16; 1331 1332 mutex_enter(&sc->sc_mtx); 1333 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1334 if (value == 0) 1335 data &= ~(1 << shift); 1336 else if (value == 1) 1337 data |= (1 << shift); 1338 1339 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1340 mutex_exit(&sc->sc_mtx); 1341 } 1342 1343 static void 1344 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1345 { 1346 struct elansc_softc *sc = arg; 1347 int reg, shift; 1348 uint16_t data; 1349 1350 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1351 shift = pin % 16; 1352 mutex_enter(&sc->sc_mtx); 1353 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1354 if (flags & GPIO_PIN_INPUT) 1355 data &= ~(1 << shift); 1356 if (flags & GPIO_PIN_OUTPUT) 1357 data |= (1 << shift); 1358 1359 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1360 mutex_exit(&sc->sc_mtx); 1361 } 1362 #endif /* NGPIO */ 1363
Indexes created Mon Sep 29 21:09:56 GMT 2025