elan520.c revision 1.31
1 /* $NetBSD: elan520.c,v 1.31 2008/04/08 20:30:17 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Device driver for the AMD Elan SC520 System Controller. This attaches 41 * where the "pchb" driver might normally attach, and provides support for 42 * extra features on the SC520, such as the watchdog timer and GPIO. 43 * 44 * Information about the GP bus echo bug work-around is from code posted 45 * to the "soekris-tech" mailing list by Jasper Wallace. 46 */ 47 48 #include <sys/cdefs.h> 49 50 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.31 2008/04/08 20:30:17 dyoung Exp $"); 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/time.h> 55 #include <sys/device.h> 56 #include <sys/gpio.h> 57 #include <sys/mutex.h> 58 #include <sys/wdog.h> 59 60 #include <uvm/uvm_extern.h> 61 62 #include <machine/bus.h> 63 64 #include <dev/pci/pcivar.h> 65 66 #include <dev/pci/pcidevs.h> 67 68 #include "gpio.h" 69 #if NGPIO > 0 70 #include <dev/gpio/gpiovar.h> 71 #endif 72 73 #include <arch/i386/pci/elan520reg.h> 74 75 #include <dev/sysmon/sysmonvar.h> 76 77 #define ELAN_IRQ 1 78 #define PG0_PROT_SIZE PAGE_SIZE 79 80 struct elansc_softc { 81 device_t sc_dev; 82 device_t sc_par; 83 device_t sc_pex; 84 device_t sc_pci; 85 86 pci_chipset_tag_t sc_pc; 87 pcitag_t sc_tag; 88 bus_space_tag_t sc_memt; 89 bus_space_handle_t sc_memh; 90 int sc_echobug; 91 92 kmutex_t sc_mtx; 93 94 struct sysmon_wdog sc_smw; 95 void *sc_eih; 96 void *sc_pih; 97 void *sc_sh; 98 uint8_t sc_mpicmode; 99 uint8_t sc_picicr; 100 int sc_pg0par; 101 int sc_textpar[3]; 102 #if NGPIO > 0 103 /* GPIO interface */ 104 struct gpio_chipset_tag sc_gpio_gc; 105 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 106 #endif 107 }; 108 109 static bool elansc_attached = false; 110 int elansc_wpvnmi = 1; 111 int elansc_pcinmi = 1; 112 int elansc_do_protect_pg0 = 1; 113 114 #if NGPIO > 0 115 static int elansc_gpio_pin_read(void *, int); 116 static void elansc_gpio_pin_write(void *, int, int); 117 static void elansc_gpio_pin_ctl(void *, int, int); 118 #endif 119 120 static void elansc_print_par(device_t, int, uint32_t); 121 122 static void elanpar_intr_establish(device_t, struct elansc_softc *); 123 static void elanpar_intr_disestablish(struct elansc_softc *); 124 static bool elanpar_shutdown(device_t, int); 125 126 static void elanpex_intr_establish(device_t, struct elansc_softc *); 127 static void elanpex_intr_disestablish(struct elansc_softc *); 128 static bool elanpex_shutdown(device_t, int); 129 130 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 131 132 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 133 134 static void 135 elansc_childdetached(device_t self, device_t child) 136 { 137 struct elansc_softc *sc = device_private(self); 138 139 if (child == sc->sc_par) 140 sc->sc_par = NULL; 141 if (child == sc->sc_pex) 142 sc->sc_pex = NULL; 143 if (child == sc->sc_pci) 144 sc->sc_pci = NULL; 145 146 /* elansc does not presently keep a pointer to 147 * the gpio, so there is nothing to do if it is detached. 148 */ 149 } 150 151 static int 152 elansc_match(device_t parent, cfdata_t match, void *aux) 153 { 154 struct pcibus_attach_args *pba = aux; 155 pcitag_t tag; 156 pcireg_t id; 157 158 if (elansc_attached) 159 return 0; 160 161 if (pcimatch(parent, match, aux) == 0) 162 return 0; 163 164 if (pba->pba_bus != 0) 165 return 0; 166 167 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 168 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 169 170 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 171 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 172 return 10; 173 174 return 0; 175 } 176 177 /* 178 * Performance tuning for Soekris net4501: 179 * - enable SDRAM write buffer and read prefetching 180 */ 181 #if 0 182 uint8_t dbctl; 183 184 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 185 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 186 dbctl |= MMCR_DBCTL_WB_WM_16DW; 187 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 188 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 189 #endif 190 191 /* 192 * Performance tuning for PCI bus on the AMD Elan SC520: 193 * - enable concurrent arbitration of PCI and CPU busses 194 * (and PCI buffer) 195 * - enable PCI automatic delayed read transactions and 196 * write posting 197 * - enable PCI read buffer snooping (coherency) 198 */ 199 static void 200 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 201 { 202 uint8_t sysarbctl; 203 uint16_t hbctl; 204 const bool concurrency = true; /* concurrent bus arbitration */ 205 206 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 207 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 208 aprint_debug_dev(self, 209 "concurrent arbitration mode is active\n"); 210 } else if (concurrency) { 211 aprint_verbose_dev(self, "activating concurrent " 212 "arbitration mode\n"); 213 /* activate concurrent bus arbitration */ 214 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 215 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 216 } 217 218 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 219 220 /* target read FIFO snoop */ 221 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 222 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 223 else { 224 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 225 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 226 } 227 228 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 229 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 230 else if (concurrency) { 231 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 232 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 233 } 234 235 /* auto delay read txn: looks safe, but seems to cause 236 * net4526 w/ minipci ath fits 237 */ 238 #if 0 239 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 240 aprint_debug_dev(self, 241 "automatic read transaction delay is active\n"); 242 else { 243 aprint_verbose_dev(self, 244 "activating automatic read transaction delay\n"); 245 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 246 } 247 #endif 248 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 249 } 250 251 static void 252 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 253 { 254 uint8_t echo_mode = 0; /* XXX: gcc */ 255 256 KASSERT(mutex_owned(&sc->sc_mtx)); 257 258 /* Switch off GP bus echo mode if we need to. */ 259 if (sc->sc_echobug) { 260 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 261 MMCR_GPECHO); 262 bus_space_write_1(sc->sc_memt, sc->sc_memh, 263 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 264 } 265 266 /* Unlock the register. */ 267 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 268 WDTMRCTL_UNLOCK1); 269 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 270 WDTMRCTL_UNLOCK2); 271 272 /* Write the value. */ 273 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 274 275 /* Switch GP bus echo mode back. */ 276 if (sc->sc_echobug) 277 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 278 echo_mode); 279 } 280 281 static void 282 elansc_wdogctl_reset(struct elansc_softc *sc) 283 { 284 uint8_t echo_mode = 0/* XXX: gcc */; 285 286 KASSERT(mutex_owned(&sc->sc_mtx)); 287 288 /* Switch off GP bus echo mode if we need to. */ 289 if (sc->sc_echobug) { 290 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 291 MMCR_GPECHO); 292 bus_space_write_1(sc->sc_memt, sc->sc_memh, 293 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 294 } 295 296 /* Reset the watchdog. */ 297 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 298 WDTMRCTL_RESET1); 299 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 300 WDTMRCTL_RESET2); 301 302 /* Switch GP bus echo mode back. */ 303 if (sc->sc_echobug) 304 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 305 echo_mode); 306 } 307 308 static const struct { 309 int period; /* whole seconds */ 310 uint16_t exp; /* exponent select */ 311 } elansc_wdog_periods[] = { 312 { 1, WDTMRCTL_EXP_SEL25 }, 313 { 2, WDTMRCTL_EXP_SEL26 }, 314 { 4, WDTMRCTL_EXP_SEL27 }, 315 { 8, WDTMRCTL_EXP_SEL28 }, 316 { 16, WDTMRCTL_EXP_SEL29 }, 317 { 32, WDTMRCTL_EXP_SEL30 }, 318 { 0, 0 }, 319 }; 320 321 static int 322 elansc_wdog_arm(struct elansc_softc *sc) 323 { 324 struct sysmon_wdog *smw = &sc->sc_smw; 325 int i; 326 uint16_t exp_sel = 0; /* XXX: gcc */ 327 328 KASSERT(mutex_owned(&sc->sc_mtx)); 329 330 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 331 smw->smw_period = 32; 332 exp_sel = WDTMRCTL_EXP_SEL30; 333 } else { 334 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 335 if (elansc_wdog_periods[i].period == 336 smw->smw_period) { 337 exp_sel = elansc_wdog_periods[i].exp; 338 break; 339 } 340 } 341 if (elansc_wdog_periods[i].period == 0) 342 return EINVAL; 343 } 344 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 345 WDTMRCTL_WRST_ENB | exp_sel); 346 elansc_wdogctl_reset(sc); 347 return 0; 348 } 349 350 static int 351 elansc_wdog_setmode(struct sysmon_wdog *smw) 352 { 353 struct elansc_softc *sc = smw->smw_cookie; 354 int rc = 0; 355 356 mutex_enter(&sc->sc_mtx); 357 358 if (!device_is_active(sc->sc_dev)) 359 rc = EBUSY; 360 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 361 elansc_wdogctl_write(sc, 362 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 363 } else 364 rc = elansc_wdog_arm(sc); 365 366 mutex_exit(&sc->sc_mtx); 367 return rc; 368 } 369 370 static int 371 elansc_wdog_tickle(struct sysmon_wdog *smw) 372 { 373 struct elansc_softc *sc = smw->smw_cookie; 374 375 mutex_enter(&sc->sc_mtx); 376 elansc_wdogctl_reset(sc); 377 mutex_exit(&sc->sc_mtx); 378 return 0; 379 } 380 381 static const char *elansc_speeds[] = { 382 "(reserved 00)", 383 "100MHz", 384 "133MHz", 385 "(reserved 11)", 386 }; 387 388 static int 389 elanpar_intr(void *arg) 390 { 391 struct elansc_softc *sc = arg; 392 uint16_t wpvsta; 393 unsigned win; 394 uint32_t par; 395 const char *wpvstr; 396 397 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 398 399 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 400 return 0; 401 402 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 403 404 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 405 406 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 407 MMCR_WPVSTA_WPV_STA); 408 409 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 410 case MMCR_WPVSTA_WPV_MSTR_CPU: 411 wpvstr = "cpu"; 412 break; 413 case MMCR_WPVSTA_WPV_MSTR_PCI: 414 wpvstr = "pci"; 415 break; 416 case MMCR_WPVSTA_WPV_MSTR_GP: 417 wpvstr = "gp"; 418 break; 419 default: 420 wpvstr = "unknown"; 421 break; 422 } 423 aprint_error_dev(sc->sc_par, 424 "%s violated write-protect window %u\n", wpvstr, win); 425 elansc_print_par(sc->sc_par, win, par); 426 return 0; 427 } 428 429 static int 430 elanpex_intr(void *arg) 431 { 432 static struct { 433 const char *string; 434 bool nonfatal; 435 } cmd[16] = { 436 [0] = {.string = "not latched"} 437 , [1] = {.string = "special cycle"} 438 , [2] = {.string = "i/o read"} 439 , [3] = {.string = "i/o write"} 440 , [4] = {.string = "4"} 441 , [5] = {.string = "5"} 442 , [6] = {.string = "memory rd"} 443 , [7] = {.string = "memory wr"} 444 , [8] = {.string = "8"} 445 , [9] = {.string = "9"} 446 , [10] = {.string = "cfg rd", .nonfatal = true} 447 , [11] = {.string = "cfg wr"} 448 , [12] = {.string = "memory rd mul"} 449 , [13] = {.string = "dual-address cycle"} 450 , [14] = {.string = "memory rd line"} 451 , [15] = {.string = "memory wr & inv"} 452 }; 453 454 static const struct { 455 uint16_t bit; 456 const char *msg; 457 } mmsg[] = { 458 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 459 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 460 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 461 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 462 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 463 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 464 }, tmsg[] = { 465 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 466 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 467 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 468 }; 469 uint8_t pciarbsta; 470 uint16_t mstcmd, mstirq, tgtid, tgtirq; 471 uint32_t mstaddr; 472 uint16_t mstack = 0, tgtack = 0; 473 int fatal = 0, i, handled = 0; 474 struct elansc_softc *sc = arg; 475 476 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 477 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 478 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 479 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 480 481 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 482 aprint_error_dev(sc->sc_pex, 483 "grant time-out, GNT%" __PRIuBITS "# asserted\n", 484 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 485 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 486 MMCR_PCIARBSTA_GNT_TO_STA); 487 handled = true; 488 } 489 490 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 491 492 for (i = 0; i < __arraycount(mmsg); i++) { 493 if ((mstirq & mmsg[i].bit) == 0) 494 continue; 495 aprint_error_dev(sc->sc_pex, 496 "%s %08" PRIx32 " master %s\n", 497 cmd[mstcmd].string, mstaddr, mmsg[i].msg); 498 499 mstack |= mmsg[i].bit; 500 if (!cmd[mstcmd].nonfatal) 501 fatal = true; 502 } 503 504 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 505 506 for (i = 0; i < __arraycount(tmsg); i++) { 507 if ((tgtirq & tmsg[i].bit) == 0) 508 continue; 509 aprint_error_dev(sc->sc_pex, "%1x target %s\n", tgtid, 510 tmsg[i].msg); 511 tgtack |= tmsg[i].bit; 512 } 513 514 /* acknowledge interrupts */ 515 if (tgtack != 0) { 516 handled = true; 517 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 518 tgtack); 519 } 520 if (mstack != 0) { 521 handled = true; 522 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 523 mstack); 524 } 525 return fatal ? 0 : (handled ? 1 : 0); 526 } 527 528 #define elansc_print_1(__dev, __sc, __reg) \ 529 do { \ 530 aprint_debug_dev(__dev, \ 531 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 532 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 533 } while (/*CONSTCOND*/0) 534 535 static void 536 elansc_print_par(device_t dev, int i, uint32_t par) 537 { 538 uint32_t addr, sz, unit; 539 const char *tgtstr; 540 541 switch (par & MMCR_PAR_TARGET) { 542 default: 543 case MMCR_PAR_TARGET_OFF: 544 tgtstr = "off"; 545 break; 546 case MMCR_PAR_TARGET_GPIO: 547 tgtstr = "gpio"; 548 break; 549 case MMCR_PAR_TARGET_GPMEM: 550 tgtstr = "gpmem"; 551 break; 552 case MMCR_PAR_TARGET_PCI: 553 tgtstr = "pci"; 554 break; 555 case MMCR_PAR_TARGET_BOOTCS: 556 tgtstr = "bootcs"; 557 break; 558 case MMCR_PAR_TARGET_ROMCS1: 559 tgtstr = "romcs1"; 560 break; 561 case MMCR_PAR_TARGET_ROMCS2: 562 tgtstr = "romcs2"; 563 break; 564 case MMCR_PAR_TARGET_SDRAM: 565 tgtstr = "sdram"; 566 break; 567 } 568 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 569 unit = 1; 570 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 571 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 572 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 573 unit = 64 * 1024; 574 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 575 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 576 } else { 577 unit = 4 * 1024; 578 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 579 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 580 } 581 582 aprint_debug_dev(dev, 583 "PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 584 " start %08" PRIx32 " size %" PRIu32 "\n", 585 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 586 addr * unit, (sz + 1) * unit); 587 } 588 589 static void 590 elansc_print_all_par(device_t dev, 591 bus_space_tag_t memt, bus_space_handle_t memh) 592 { 593 int i; 594 uint32_t par; 595 596 for (i = 0; i < 16; i++) { 597 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 598 elansc_print_par(dev, i, par); 599 } 600 } 601 602 static int 603 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 604 { 605 int i; 606 uint32_t par; 607 608 for (i = 0; i < 16; i++) { 609 610 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 611 612 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 613 break; 614 } 615 if (i == 16) 616 return -1; 617 return i; 618 } 619 620 static void 621 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 622 { 623 uint32_t par; 624 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 625 par &= ~MMCR_PAR_TARGET; 626 par |= MMCR_PAR_TARGET_OFF; 627 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 628 } 629 630 struct pareg { 631 paddr_t start; 632 paddr_t end; 633 }; 634 635 static int 636 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 637 { 638 struct pareg *residue = regions; 639 paddr_t start, end; 640 paddr_t start0, end0; 641 642 start0 = region0->start; 643 end0 = region0->end; 644 645 if (start0 % unit != 0) 646 start = start0 + unit - start0 % unit; 647 else 648 start = start0; 649 650 end = end0 - end0 % unit; 651 652 if (start >= end) 653 return 0; 654 655 residue->start = start; 656 residue->end = end; 657 residue++; 658 659 if (start0 < start) { 660 residue->start = start0; 661 residue->end = start; 662 residue++; 663 } 664 if (end < end0) { 665 residue->start = end; 666 residue->end = end0; 667 residue++; 668 } 669 return residue - regions; 670 } 671 672 static void 673 elansc_protect_text(device_t self, struct elansc_softc *sc) 674 { 675 int i, j, nregion, pidx, tidx = 0, xnregion; 676 uint32_t par; 677 uint32_t protsize, unprotsize; 678 paddr_t start_pa, end_pa; 679 extern char kernel_text, etext; 680 bus_space_tag_t memt; 681 bus_space_handle_t memh; 682 struct pareg region0, regions[3], xregions[3]; 683 684 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 685 686 memt = sc->sc_memt; 687 memh = sc->sc_memh; 688 689 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 690 ®ion0.start) || 691 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 692 ®ion0.end)) 693 return; 694 695 if (&etext - &kernel_text != region0.end - region0.start) { 696 aprint_error_dev(self, "kernel text may not be contiguous\n"); 697 return; 698 } 699 700 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 701 aprint_error_dev(self, "cannot allocate PAR\n"); 702 return; 703 } 704 705 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 706 707 aprint_debug_dev(self, 708 "protect kernel text at physical addresses %p - %p\n", 709 (void *)region0.start, (void *)region0.end); 710 711 nregion = region_paddr_to_par(®ion0, regions, sfkb); 712 if (nregion == 0) { 713 aprint_error_dev(self, "kernel text is unprotected\n"); 714 return; 715 } 716 717 unprotsize = 0; 718 for (i = 1; i < nregion; i++) 719 unprotsize += regions[i].end - regions[i].start; 720 721 start_pa = regions[0].start; 722 end_pa = regions[0].end; 723 724 aprint_debug_dev(self, 725 "actually protect kernel text at physical addresses %p - %p\n", 726 (void *)start_pa, (void *)end_pa); 727 728 aprint_verbose_dev(self, 729 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 730 731 protsize = end_pa - start_pa; 732 733 #if 0 734 /* set PG_SZ, attribute, target, size, address. */ 735 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 736 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 737 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 738 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 739 #else 740 elansc_protect(sc, pidx, start_pa, protsize); 741 #endif 742 743 sc->sc_textpar[tidx++] = pidx; 744 745 unprotsize = 0; 746 for (i = 1; i < nregion; i++) { 747 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 748 if (xnregion == 0) { 749 aprint_verbose_dev(self, "skip region %p - %p\n", 750 (void *)regions[i].start, (void *)regions[i].end); 751 continue; 752 } 753 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 754 unprotsize += regions[i].end - regions[i].start; 755 continue; 756 } 757 elansc_protect(sc, pidx, xregions[0].start, 758 xregions[0].end - xregions[0].start); 759 sc->sc_textpar[tidx++] = pidx; 760 761 aprint_debug_dev(self, 762 "protect add'l kernel text at physical addresses %p - %p\n", 763 (void *)xregions[0].start, (void *)xregions[0].end); 764 765 for (j = 1; j < xnregion; j++) 766 unprotsize += xregions[j].end - xregions[j].start; 767 } 768 aprint_verbose_dev(self, 769 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 770 771 } 772 773 static void 774 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 775 { 776 uint32_t addr_field, blksz, par, size_field; 777 778 /* set attribute, target. */ 779 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 780 781 KASSERT(addr % fkb == 0 && sz % fkb == 0); 782 783 if (addr % sfkb == 0 && sz % sfkb == 0) { 784 par |= MMCR_PAR_PG_SZ; 785 786 size_field = MMCR_PAR_64KB_SZ; 787 addr_field = MMCR_PAR_64KB_ST_ADR; 788 blksz = 64 * 1024; 789 } else { 790 size_field = MMCR_PAR_4KB_SZ; 791 addr_field = MMCR_PAR_4KB_ST_ADR; 792 blksz = 4 * 1024; 793 } 794 795 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 796 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 797 798 /* set size and address. */ 799 par |= __SHIFTIN(sz / blksz - 1, size_field); 800 par |= __SHIFTIN(addr / blksz, addr_field); 801 802 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 803 } 804 805 static int 806 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 807 { 808 int pidx; 809 const paddr_t pg0_paddr = 0; 810 bus_space_tag_t memt; 811 bus_space_handle_t memh; 812 813 memt = sc->sc_memt; 814 memh = sc->sc_memh; 815 816 if (elansc_do_protect_pg0 == 0) 817 return -1; 818 819 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 820 return -1; 821 822 aprint_debug_dev(self, "protect page 0\n"); 823 824 #if 0 825 /* set PG_SZ, attribute, target, size, address. */ 826 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 827 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 828 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 829 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 830 #else 831 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 832 #endif 833 return pidx; 834 } 835 836 static void 837 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 838 { 839 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 840 MMCR_PCIARBSTA_GNT_TO_STA); 841 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 842 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 843 } 844 845 static bool 846 elansc_suspend(device_t dev PMF_FN_ARGS) 847 { 848 bool rc; 849 struct elansc_softc *sc = device_private(dev); 850 851 mutex_enter(&sc->sc_mtx); 852 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 853 mutex_exit(&sc->sc_mtx); 854 if (!rc) 855 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 856 return rc; 857 } 858 859 static bool 860 elansc_resume(device_t dev PMF_FN_ARGS) 861 { 862 struct elansc_softc *sc = device_private(dev); 863 864 mutex_enter(&sc->sc_mtx); 865 /* Set up the watchdog registers with some defaults. */ 866 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 867 868 /* ...and clear it. */ 869 elansc_wdogctl_reset(sc); 870 mutex_exit(&sc->sc_mtx); 871 872 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 873 874 return true; 875 } 876 877 static int 878 elansc_detach(device_t self, int flags) 879 { 880 int rc; 881 struct elansc_softc *sc = device_private(self); 882 883 if ((rc = config_detach_children(self, flags)) != 0) 884 return rc; 885 886 pmf_device_deregister(self); 887 888 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 889 if (rc == ERESTART) 890 rc = EINTR; 891 return rc; 892 } 893 894 mutex_enter(&sc->sc_mtx); 895 896 /* Set up the watchdog registers with some defaults. */ 897 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 898 899 /* ...and clear it. */ 900 elansc_wdogctl_reset(sc); 901 902 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 903 904 mutex_exit(&sc->sc_mtx); 905 mutex_destroy(&sc->sc_mtx); 906 elansc_attached = false; 907 return 0; 908 } 909 910 static void * 911 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 912 { 913 struct pic *pic; 914 void *ih; 915 916 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 917 aprint_error_dev(dev, "PIC for irq %d not found\n", 918 ELAN_IRQ); 919 return NULL; 920 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 921 IST_LEVEL, IPL_HIGH, handler, arg)) == NULL) { 922 aprint_error_dev(dev, 923 "could not establish interrupt\n"); 924 return NULL; 925 } 926 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 927 return ih; 928 } 929 930 static bool 931 elanpex_resume(device_t self PMF_FN_ARGS) 932 { 933 struct elansc_softc *sc = device_private(device_parent(self)); 934 935 elanpex_intr_establish(self, sc); 936 return sc->sc_eih != NULL; 937 } 938 939 static bool 940 elanpex_suspend(device_t self PMF_FN_ARGS) 941 { 942 struct elansc_softc *sc = device_private(device_parent(self)); 943 944 elanpex_intr_disestablish(sc); 945 946 return true; 947 } 948 949 static bool 950 elanpar_resume(device_t self PMF_FN_ARGS) 951 { 952 struct elansc_softc *sc = device_private(device_parent(self)); 953 954 elanpar_intr_establish(self, sc); 955 return sc->sc_pih != NULL; 956 } 957 958 static bool 959 elanpar_suspend(device_t self PMF_FN_ARGS) 960 { 961 struct elansc_softc *sc = device_private(device_parent(self)); 962 963 elanpar_intr_disestablish(sc); 964 965 return true; 966 } 967 968 static void 969 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 970 { 971 uint8_t sysarbctl; 972 uint16_t pcihostmap, mstirq, tgtirq; 973 974 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 975 MMCR_PCIHOSTMAP); 976 /* Priority P2 (Master PIC IR1) */ 977 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 978 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 979 if (elansc_pcinmi) 980 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 981 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 982 pcihostmap); 983 984 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 985 986 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 987 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 988 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 989 990 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 991 992 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 993 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 994 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 995 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 996 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 997 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 998 999 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1000 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1001 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1002 1003 if (elansc_pcinmi) { 1004 sc->sc_eih = nmi_establish(elanpex_intr, sc); 1005 1006 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1007 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1008 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1009 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1010 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1011 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1012 1013 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1014 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1015 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1016 } else 1017 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1018 1019 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1020 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1021 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1022 } 1023 1024 static void 1025 elanpex_attach(device_t parent, device_t self, void *aux) 1026 { 1027 struct elansc_softc *sc = device_private(parent); 1028 1029 aprint_naive(": PCI Exceptions\n"); 1030 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1031 1032 elanpex_intr_establish(self, sc); 1033 1034 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1035 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1036 1037 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1038 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1039 1040 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1041 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1042 1043 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1044 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1045 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1046 1047 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1048 elanpex_shutdown)) 1049 aprint_error_dev(self, "could not establish power hooks\n"); 1050 } 1051 1052 static bool 1053 elanpex_shutdown(device_t self, int flags) 1054 { 1055 struct elansc_softc *sc = device_private(device_parent(self)); 1056 uint8_t sysarbctl; 1057 uint16_t pcihostmap, mstirq, tgtirq; 1058 1059 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1060 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1061 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1062 1063 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1064 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1065 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1066 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1067 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1068 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1069 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1070 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1071 1072 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1073 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1074 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1075 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1076 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1077 1078 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1079 MMCR_PCIHOSTMAP); 1080 /* Priority P2 (Master PIC IR1) */ 1081 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1082 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1083 pcihostmap); 1084 1085 return true; 1086 } 1087 1088 static void 1089 elanpex_intr_disestablish(struct elansc_softc *sc) 1090 { 1091 elanpex_shutdown(sc->sc_pex, 0); 1092 1093 if (elansc_pcinmi) 1094 nmi_disestablish(sc->sc_eih); 1095 else 1096 intr_disestablish(sc->sc_eih); 1097 sc->sc_eih = NULL; 1098 1099 } 1100 1101 static int 1102 elanpex_detach(device_t self, int flags) 1103 { 1104 struct elansc_softc *sc = device_private(device_parent(self)); 1105 1106 pmf_device_deregister(self); 1107 elanpex_intr_disestablish(sc); 1108 1109 return 0; 1110 } 1111 1112 static void 1113 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1114 { 1115 uint8_t adddecctl, wpvmap; 1116 1117 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1118 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1119 if (elansc_wpvnmi) 1120 wpvmap |= MMCR_WPVMAP_INT_NMI; 1121 else 1122 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1123 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1124 1125 /* clear interrupt status */ 1126 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1127 MMCR_WPVSTA_WPV_STA); 1128 1129 /* establish interrupt */ 1130 if (elansc_wpvnmi) 1131 sc->sc_pih = nmi_establish(elanpar_intr, sc); 1132 else 1133 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1134 1135 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1136 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1137 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1138 } 1139 1140 static bool 1141 elanpar_shutdown(device_t self, int flags) 1142 { 1143 int i; 1144 struct elansc_softc *sc = device_private(device_parent(self)); 1145 1146 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1147 if (sc->sc_textpar[i] == -1) 1148 continue; 1149 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1150 sc->sc_textpar[i] = -1; 1151 } 1152 if (sc->sc_pg0par != -1) { 1153 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1154 sc->sc_pg0par = -1; 1155 } 1156 return true; 1157 } 1158 1159 static void 1160 elanpar_deferred_attach(device_t self) 1161 { 1162 struct elansc_softc *sc = device_private(device_parent(self)); 1163 1164 elansc_protect_text(self, sc); 1165 } 1166 1167 static void 1168 elanpar_attach(device_t parent, device_t self, void *aux) 1169 { 1170 struct elansc_softc *sc = device_private(parent); 1171 1172 aprint_naive(": Programmable Address Regions\n"); 1173 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1174 1175 elansc_print_1(self, sc, MMCR_WPVMAP); 1176 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1177 1178 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1179 /* XXX grotty hack to avoid trapping writes by x86_patch() 1180 * to the kernel text on a MULTIPROCESSOR kernel. 1181 */ 1182 config_interrupts(self, elanpar_deferred_attach); 1183 1184 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1185 1186 elanpar_intr_establish(self, sc); 1187 1188 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1189 1190 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1191 elanpar_shutdown)) 1192 aprint_error_dev(self, "could not establish power hooks\n"); 1193 } 1194 1195 static void 1196 elanpar_intr_disestablish(struct elansc_softc *sc) 1197 { 1198 uint8_t adddecctl, wpvmap; 1199 1200 /* disable interrupt, acknowledge it, disestablish our 1201 * handler, unmap it 1202 */ 1203 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1204 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1205 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1206 1207 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1208 MMCR_WPVSTA_WPV_STA); 1209 1210 if (elansc_wpvnmi) 1211 nmi_disestablish(sc->sc_pih); 1212 else 1213 intr_disestablish(sc->sc_pih); 1214 sc->sc_pih = NULL; 1215 1216 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1217 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1218 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1219 } 1220 1221 static int 1222 elanpar_detach(device_t self, int flags) 1223 { 1224 struct elansc_softc *sc = device_private(device_parent(self)); 1225 1226 pmf_device_deregister(self); 1227 1228 elanpar_shutdown(self, 0); 1229 1230 elanpar_intr_disestablish(sc); 1231 1232 return 0; 1233 } 1234 1235 static void 1236 elansc_attach(device_t parent, device_t self, void *aux) 1237 { 1238 struct elansc_softc *sc = device_private(self); 1239 struct pcibus_attach_args *pba = aux; 1240 uint16_t rev; 1241 uint8_t cpuctl, picicr, ressta; 1242 #if NGPIO > 0 1243 struct gpiobus_attach_args gba; 1244 int pin, reg, shift; 1245 uint16_t data; 1246 #endif 1247 1248 sc->sc_dev = self; 1249 1250 sc->sc_pc = pba->pba_pc; 1251 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1252 1253 aprint_naive(": System Controller\n"); 1254 aprint_normal(": AMD Elan SC520 System Controller\n"); 1255 1256 sc->sc_memt = pba->pba_memt; 1257 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1258 &sc->sc_memh) != 0) { 1259 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1260 return; 1261 } 1262 1263 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1264 1265 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1266 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1267 1268 aprint_normal_dev(sc->sc_dev, 1269 "product %d stepping %d.%d, CPU clock %s\n", 1270 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1271 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1272 (rev & REVID_MINSTEP), 1273 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1274 1275 /* 1276 * SC520 rev A1 has a bug that affects the watchdog timer. If 1277 * the GP bus echo mode is enabled, writing to the watchdog control 1278 * register is blocked. 1279 * 1280 * The BIOS in some systems (e.g. the Soekris net4501) enables 1281 * GP bus echo for various reasons, so we need to switch it off 1282 * when we talk to the watchdog timer. 1283 * 1284 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1285 * XXX problem, so we'll just enable it for all Elan SC520s 1286 * XXX for now. --thorpej (at) NetBSD.org 1287 */ 1288 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1289 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1290 sc->sc_echobug = 1; 1291 1292 /* 1293 * Determine cause of the last reset, and issue a warning if it 1294 * was due to watchdog expiry. 1295 */ 1296 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1297 if (ressta & RESSTA_WDT_RST_DET) 1298 aprint_error_dev(sc->sc_dev, 1299 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1300 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1301 1302 elansc_print_1(self, sc, MMCR_MPICMODE); 1303 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1304 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1305 elansc_print_1(self, sc, MMCR_PICICR); 1306 1307 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1308 MMCR_MPICMODE); 1309 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1310 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1311 1312 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1313 picicr = sc->sc_picicr; 1314 if (elansc_pcinmi || elansc_wpvnmi) 1315 picicr |= MMCR_PICICR_NMI_ENB; 1316 #if 0 1317 /* PC/AT compatibility */ 1318 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1319 #endif 1320 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1321 1322 elansc_print_1(self, sc, MMCR_PICICR); 1323 elansc_print_1(self, sc, MMCR_MPICMODE); 1324 1325 mutex_enter(&sc->sc_mtx); 1326 /* Set up the watchdog registers with some defaults. */ 1327 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1328 1329 /* ...and clear it. */ 1330 elansc_wdogctl_reset(sc); 1331 mutex_exit(&sc->sc_mtx); 1332 1333 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1334 aprint_error_dev(self, "could not establish power hooks\n"); 1335 1336 #if NGPIO > 0 1337 /* Initialize GPIO pins array */ 1338 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1339 sc->sc_gpio_pins[pin].pin_num = pin; 1340 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1341 GPIO_PIN_OUTPUT; 1342 1343 /* Read initial state */ 1344 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1345 shift = pin % 16; 1346 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1347 if ((data & (1 << shift)) == 0) 1348 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1349 else 1350 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1351 if (elansc_gpio_pin_read(sc, pin) == 0) 1352 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1353 else 1354 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1355 } 1356 1357 /* Create controller tag */ 1358 sc->sc_gpio_gc.gp_cookie = sc; 1359 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1360 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1361 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1362 1363 gba.gba_gc = &sc->sc_gpio_gc; 1364 gba.gba_pins = sc->sc_gpio_pins; 1365 gba.gba_npins = ELANSC_PIO_NPINS; 1366 1367 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1368 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1369 /* Attach GPIO framework */ 1370 config_found_ia(sc->sc_dev, "gpiobus", &gba, gpiobus_print); 1371 #endif /* NGPIO */ 1372 1373 /* 1374 * Hook up the watchdog timer. 1375 */ 1376 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1377 sc->sc_smw.smw_cookie = sc; 1378 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1379 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1380 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1381 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1382 aprint_error_dev(sc->sc_dev, 1383 "unable to register watchdog with sysmon\n"); 1384 } 1385 elansc_attached = true; 1386 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1387 } 1388 1389 static int 1390 elanpex_match(device_t parent, struct cfdata *match, void *aux) 1391 { 1392 struct elansc_softc *sc = device_private(parent); 1393 1394 return sc->sc_pex == NULL; 1395 } 1396 1397 static int 1398 elanpar_match(device_t parent, struct cfdata *match, void *aux) 1399 { 1400 struct elansc_softc *sc = device_private(parent); 1401 1402 return sc->sc_par == NULL; 1403 } 1404 1405 CFATTACH_DECL_NEW(elanpar, 0, 1406 elanpar_match, elanpar_attach, elanpar_detach, NULL); 1407 1408 CFATTACH_DECL_NEW(elanpex, 0, 1409 elanpex_match, elanpex_attach, elanpex_detach, NULL); 1410 1411 CFATTACH_DECL2_NEW(elansc, sizeof(struct elansc_softc), 1412 elansc_match, elansc_attach, elansc_detach, NULL, NULL, 1413 elansc_childdetached); 1414 1415 #if NGPIO > 0 1416 static int 1417 elansc_gpio_pin_read(void *arg, int pin) 1418 { 1419 struct elansc_softc *sc = arg; 1420 int reg, shift; 1421 uint16_t data; 1422 1423 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1424 shift = pin % 16; 1425 1426 mutex_enter(&sc->sc_mtx); 1427 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1428 mutex_exit(&sc->sc_mtx); 1429 1430 return ((data >> shift) & 0x1); 1431 } 1432 1433 static void 1434 elansc_gpio_pin_write(void *arg, int pin, int value) 1435 { 1436 struct elansc_softc *sc = arg; 1437 int reg, shift; 1438 uint16_t data; 1439 1440 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1441 shift = pin % 16; 1442 1443 mutex_enter(&sc->sc_mtx); 1444 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1445 if (value == 0) 1446 data &= ~(1 << shift); 1447 else if (value == 1) 1448 data |= (1 << shift); 1449 1450 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1451 mutex_exit(&sc->sc_mtx); 1452 } 1453 1454 static void 1455 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1456 { 1457 struct elansc_softc *sc = arg; 1458 int reg, shift; 1459 uint16_t data; 1460 1461 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1462 shift = pin % 16; 1463 mutex_enter(&sc->sc_mtx); 1464 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1465 if (flags & GPIO_PIN_INPUT) 1466 data &= ~(1 << shift); 1467 if (flags & GPIO_PIN_OUTPUT) 1468 data |= (1 << shift); 1469 1470 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1471 mutex_exit(&sc->sc_mtx); 1472 } 1473 #endif /* NGPIO */ 1474
Indexes created Wed Oct 01 13:09:50 GMT 2025