elan520.c revision 1.35
1 /* $NetBSD: elan520.c,v 1.35 2008/05/31 22:37:00 dyoung Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Device driver for the AMD Elan SC520 System Controller. This attaches 34 * where the "pchb" driver might normally attach, and provides support for 35 * extra features on the SC520, such as the watchdog timer and GPIO. 36 * 37 * Information about the GP bus echo bug work-around is from code posted 38 * to the "soekris-tech" mailing list by Jasper Wallace. 39 */ 40 41 #include <sys/cdefs.h> 42 43 __KERNEL_RCSID(0, "$NetBSD: elan520.c,v 1.35 2008/05/31 22:37:00 dyoung Exp $"); 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/time.h> 48 #include <sys/device.h> 49 #include <sys/gpio.h> 50 #include <sys/mutex.h> 51 #include <sys/wdog.h> 52 #include <sys/reboot.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <machine/bus.h> 57 58 #include <dev/pci/pcivar.h> 59 60 #include <dev/pci/pcidevs.h> 61 62 #include "gpio.h" 63 #if NGPIO > 0 64 #include <dev/gpio/gpiovar.h> 65 #endif 66 67 #include <arch/i386/pci/elan520reg.h> 68 69 #include <dev/sysmon/sysmonvar.h> 70 71 #define ELAN_IRQ 1 72 #define PG0_PROT_SIZE PAGE_SIZE 73 74 struct elansc_softc { 75 device_t sc_dev; 76 device_t sc_par; 77 device_t sc_pex; 78 device_t sc_pci; 79 80 pci_chipset_tag_t sc_pc; 81 pcitag_t sc_tag; 82 bus_space_tag_t sc_memt; 83 bus_space_handle_t sc_memh; 84 int sc_echobug; 85 86 kmutex_t sc_mtx; 87 88 struct sysmon_wdog sc_smw; 89 void *sc_eih; 90 void *sc_pih; 91 void *sc_sh; 92 uint8_t sc_mpicmode; 93 uint8_t sc_picicr; 94 int sc_pg0par; 95 int sc_textpar[3]; 96 #if NGPIO > 0 97 /* GPIO interface */ 98 struct gpio_chipset_tag sc_gpio_gc; 99 gpio_pin_t sc_gpio_pins[ELANSC_PIO_NPINS]; 100 #endif 101 }; 102 103 static bool elansc_attached = false; 104 int elansc_wpvnmi = 1; 105 int elansc_pcinmi = 1; 106 int elansc_do_protect_pg0 = 1; 107 108 #if NGPIO > 0 109 static int elansc_gpio_pin_read(void *, int); 110 static void elansc_gpio_pin_write(void *, int, int); 111 static void elansc_gpio_pin_ctl(void *, int, int); 112 #endif 113 114 static void elansc_print_par(device_t, int, uint32_t); 115 116 static void elanpar_intr_establish(device_t, struct elansc_softc *); 117 static void elanpar_intr_disestablish(struct elansc_softc *); 118 static bool elanpar_shutdown(device_t, int); 119 120 static void elanpex_intr_establish(device_t, struct elansc_softc *); 121 static void elanpex_intr_disestablish(struct elansc_softc *); 122 static bool elanpex_shutdown(device_t, int); 123 124 static void elansc_protect(struct elansc_softc *, int, paddr_t, uint32_t); 125 126 static const uint32_t sfkb = 64 * 1024, fkb = 4 * 1024; 127 128 static void 129 elansc_childdetached(device_t self, device_t child) 130 { 131 struct elansc_softc *sc = device_private(self); 132 133 if (child == sc->sc_par) 134 sc->sc_par = NULL; 135 if (child == sc->sc_pex) 136 sc->sc_pex = NULL; 137 if (child == sc->sc_pci) 138 sc->sc_pci = NULL; 139 140 /* elansc does not presently keep a pointer to 141 * the gpio, so there is nothing to do if it is detached. 142 */ 143 } 144 145 static int 146 elansc_match(device_t parent, cfdata_t match, void *aux) 147 { 148 struct pcibus_attach_args *pba = aux; 149 pcitag_t tag; 150 pcireg_t id; 151 152 if (elansc_attached) 153 return 0; 154 155 if (pcimatch(parent, match, aux) == 0) 156 return 0; 157 158 if (pba->pba_bus != 0) 159 return 0; 160 161 tag = pci_make_tag(pba->pba_pc, 0, 0, 0); 162 id = pci_conf_read(pba->pba_pc, tag, PCI_ID_REG); 163 164 if (PCI_VENDOR(id) == PCI_VENDOR_AMD && 165 PCI_PRODUCT(id) == PCI_PRODUCT_AMD_SC520_SC) 166 return 10; 167 168 return 0; 169 } 170 171 /* 172 * Performance tuning for Soekris net4501: 173 * - enable SDRAM write buffer and read prefetching 174 */ 175 #if 0 176 uint8_t dbctl; 177 178 dbctl = bus_space_read_1(memt, memh, MMCR_DBCTL); 179 dbctl &= ~MMCR_DBCTL_WB_WM_MASK; 180 dbctl |= MMCR_DBCTL_WB_WM_16DW; 181 dbctl |= MMCR_DBCTL_WB_ENB | MMCR_DBCTL_RAB_ENB; 182 bus_space_write_1(memt, memh, MMCR_DBCTL, dbctl); 183 #endif 184 185 /* 186 * Performance tuning for PCI bus on the AMD Elan SC520: 187 * - enable concurrent arbitration of PCI and CPU busses 188 * (and PCI buffer) 189 * - enable PCI automatic delayed read transactions and 190 * write posting 191 * - enable PCI read buffer snooping (coherency) 192 */ 193 static void 194 elansc_perf_tune(device_t self, bus_space_tag_t memt, bus_space_handle_t memh) 195 { 196 uint8_t sysarbctl; 197 uint16_t hbctl; 198 const bool concurrency = true; /* concurrent bus arbitration */ 199 200 sysarbctl = bus_space_read_1(memt, memh, MMCR_SYSARBCTL); 201 if ((sysarbctl & MMCR_SYSARBCTL_CNCR_MODE_ENB) != 0) { 202 aprint_debug_dev(self, 203 "concurrent arbitration mode is active\n"); 204 } else if (concurrency) { 205 aprint_verbose_dev(self, "activating concurrent " 206 "arbitration mode\n"); 207 /* activate concurrent bus arbitration */ 208 sysarbctl |= MMCR_SYSARBCTL_CNCR_MODE_ENB; 209 bus_space_write_1(memt, memh, MMCR_SYSARBCTL, sysarbctl); 210 } 211 212 hbctl = bus_space_read_2(memt, memh, MMCR_HBCTL); 213 214 /* target read FIFO snoop */ 215 if ((hbctl & MMCR_HBCTL_T_PURGE_RD_ENB) != 0) 216 aprint_debug_dev(self, "read-FIFO snooping is active\n"); 217 else { 218 aprint_verbose_dev(self, "activating read-FIFO snooping\n"); 219 hbctl |= MMCR_HBCTL_T_PURGE_RD_ENB; 220 } 221 222 if ((hbctl & MMCR_HBCTL_M_WPOST_ENB) != 0) 223 aprint_debug_dev(self, "CPU->PCI write-posting is active\n"); 224 else if (concurrency) { 225 aprint_verbose_dev(self, "activating CPU->PCI write-posting\n"); 226 hbctl |= MMCR_HBCTL_M_WPOST_ENB; 227 } 228 229 /* auto delay read txn: looks safe, but seems to cause 230 * net4526 w/ minipci ath fits 231 */ 232 #if 0 233 if ((hbctl & MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY) != 0) 234 aprint_debug_dev(self, 235 "automatic read transaction delay is active\n"); 236 else { 237 aprint_verbose_dev(self, 238 "activating automatic read transaction delay\n"); 239 hbctl |= MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY; 240 } 241 #endif 242 bus_space_write_2(memt, memh, MMCR_HBCTL, hbctl); 243 } 244 245 static void 246 elansc_wdogctl_write(struct elansc_softc *sc, uint16_t val) 247 { 248 uint8_t echo_mode = 0; /* XXX: gcc */ 249 250 KASSERT(mutex_owned(&sc->sc_mtx)); 251 252 /* Switch off GP bus echo mode if we need to. */ 253 if (sc->sc_echobug) { 254 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 255 MMCR_GPECHO); 256 bus_space_write_1(sc->sc_memt, sc->sc_memh, 257 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 258 } 259 260 /* Unlock the register. */ 261 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 262 WDTMRCTL_UNLOCK1); 263 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 264 WDTMRCTL_UNLOCK2); 265 266 /* Write the value. */ 267 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, val); 268 269 /* Switch GP bus echo mode back. */ 270 if (sc->sc_echobug) 271 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 272 echo_mode); 273 } 274 275 static void 276 elansc_wdogctl_reset(struct elansc_softc *sc) 277 { 278 uint8_t echo_mode = 0/* XXX: gcc */; 279 280 KASSERT(mutex_owned(&sc->sc_mtx)); 281 282 /* Switch off GP bus echo mode if we need to. */ 283 if (sc->sc_echobug) { 284 echo_mode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 285 MMCR_GPECHO); 286 bus_space_write_1(sc->sc_memt, sc->sc_memh, 287 MMCR_GPECHO, echo_mode & ~GPECHO_GP_ECHO_ENB); 288 } 289 290 /* Reset the watchdog. */ 291 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 292 WDTMRCTL_RESET1); 293 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WDTMRCTL, 294 WDTMRCTL_RESET2); 295 296 /* Switch GP bus echo mode back. */ 297 if (sc->sc_echobug) 298 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_GPECHO, 299 echo_mode); 300 } 301 302 static const struct { 303 int period; /* whole seconds */ 304 uint16_t exp; /* exponent select */ 305 } elansc_wdog_periods[] = { 306 { 1, WDTMRCTL_EXP_SEL25 }, 307 { 2, WDTMRCTL_EXP_SEL26 }, 308 { 4, WDTMRCTL_EXP_SEL27 }, 309 { 8, WDTMRCTL_EXP_SEL28 }, 310 { 16, WDTMRCTL_EXP_SEL29 }, 311 { 32, WDTMRCTL_EXP_SEL30 }, 312 { 0, 0 }, 313 }; 314 315 static int 316 elansc_wdog_arm(struct elansc_softc *sc) 317 { 318 struct sysmon_wdog *smw = &sc->sc_smw; 319 int i; 320 uint16_t exp_sel = 0; /* XXX: gcc */ 321 322 KASSERT(mutex_owned(&sc->sc_mtx)); 323 324 if (smw->smw_period == WDOG_PERIOD_DEFAULT) { 325 smw->smw_period = 32; 326 exp_sel = WDTMRCTL_EXP_SEL30; 327 } else { 328 for (i = 0; elansc_wdog_periods[i].period != 0; i++) { 329 if (elansc_wdog_periods[i].period == 330 smw->smw_period) { 331 exp_sel = elansc_wdog_periods[i].exp; 332 break; 333 } 334 } 335 if (elansc_wdog_periods[i].period == 0) 336 return EINVAL; 337 } 338 elansc_wdogctl_write(sc, WDTMRCTL_ENB | 339 WDTMRCTL_WRST_ENB | exp_sel); 340 elansc_wdogctl_reset(sc); 341 return 0; 342 } 343 344 static int 345 elansc_wdog_setmode(struct sysmon_wdog *smw) 346 { 347 struct elansc_softc *sc = smw->smw_cookie; 348 int rc = 0; 349 350 mutex_enter(&sc->sc_mtx); 351 352 if (!device_is_active(sc->sc_dev)) 353 rc = EBUSY; 354 else if ((smw->smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED) { 355 elansc_wdogctl_write(sc, 356 WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 357 } else 358 rc = elansc_wdog_arm(sc); 359 360 mutex_exit(&sc->sc_mtx); 361 return rc; 362 } 363 364 static int 365 elansc_wdog_tickle(struct sysmon_wdog *smw) 366 { 367 struct elansc_softc *sc = smw->smw_cookie; 368 369 mutex_enter(&sc->sc_mtx); 370 elansc_wdogctl_reset(sc); 371 mutex_exit(&sc->sc_mtx); 372 return 0; 373 } 374 375 static const char *elansc_speeds[] = { 376 "(reserved 00)", 377 "100MHz", 378 "133MHz", 379 "(reserved 11)", 380 }; 381 382 static int 383 elanpar_intr(void *arg) 384 { 385 struct elansc_softc *sc = arg; 386 uint16_t wpvsta; 387 unsigned win; 388 uint32_t par; 389 const char *wpvstr; 390 391 wpvsta = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA); 392 393 if ((wpvsta & MMCR_WPVSTA_WPV_STA) == 0) 394 return 0; 395 396 win = __SHIFTOUT(wpvsta, MMCR_WPVSTA_WPV_WINDOW); 397 398 par = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(win)); 399 400 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 401 MMCR_WPVSTA_WPV_STA); 402 403 switch (wpvsta & MMCR_WPVSTA_WPV_MSTR) { 404 case MMCR_WPVSTA_WPV_MSTR_CPU: 405 wpvstr = "cpu"; 406 break; 407 case MMCR_WPVSTA_WPV_MSTR_PCI: 408 wpvstr = "pci"; 409 break; 410 case MMCR_WPVSTA_WPV_MSTR_GP: 411 wpvstr = "gp"; 412 break; 413 default: 414 wpvstr = "unknown"; 415 break; 416 } 417 printf_tolog("%s: %s violated write-protect window %u\n", 418 device_xname(sc->sc_par), wpvstr, win); 419 elansc_print_par(sc->sc_par, win, par); 420 return 0; 421 } 422 423 static int 424 elanpex_intr(void *arg) 425 { 426 static struct { 427 const char *string; 428 bool nonfatal; 429 } cmd[16] = { 430 [0] = {.string = "not latched"} 431 , [1] = {.string = "special cycle"} 432 , [2] = {.string = "i/o read"} 433 , [3] = {.string = "i/o write"} 434 , [4] = {.string = "4"} 435 , [5] = {.string = "5"} 436 , [6] = {.string = "memory rd"} 437 , [7] = {.string = "memory wr"} 438 , [8] = {.string = "8"} 439 , [9] = {.string = "9"} 440 , [10] = {.string = "cfg rd", .nonfatal = true} 441 , [11] = {.string = "cfg wr"} 442 , [12] = {.string = "memory rd mul"} 443 , [13] = {.string = "dual-address cycle"} 444 , [14] = {.string = "memory rd line"} 445 , [15] = {.string = "memory wr & inv"} 446 }; 447 448 static const struct { 449 uint16_t bit; 450 const char *msg; 451 } mmsg[] = { 452 {MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA, "retry timeout"} 453 , {MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA, "target abort"} 454 , {MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA, "abort"} 455 , {MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA, "system error"} 456 , {MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA, "received parity error"} 457 , {MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA, "detected parity error"} 458 }, tmsg[] = { 459 {MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA, "delayed txn timeout"} 460 , {MMCR_HBTGTIRQSTA_T_APER_IRQ_STA, "address parity"} 461 , {MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA, "data parity"} 462 }; 463 uint8_t pciarbsta; 464 uint16_t mstcmd, mstirq, tgtid, tgtirq; 465 uint32_t mstaddr; 466 uint16_t mstack = 0, tgtack = 0; 467 int fatal = 0, i, handled = 0; 468 struct elansc_softc *sc = arg; 469 470 pciarbsta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA); 471 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA); 472 mstaddr = bus_space_read_4(sc->sc_memt, sc->sc_memh, MMCR_MSTINTADD); 473 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA); 474 475 if ((pciarbsta & MMCR_PCIARBSTA_GNT_TO_STA) != 0) { 476 printf_tolog( 477 "%s: grant time-out, GNT%" __PRIuBITS "# asserted\n", 478 device_xname(sc->sc_pex), 479 __SHIFTOUT(pciarbsta, MMCR_PCIARBSTA_GNT_TO_ID)); 480 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PCIARBSTA, 481 MMCR_PCIARBSTA_GNT_TO_STA); 482 handled = true; 483 } 484 485 mstcmd = __SHIFTOUT(mstirq, MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID); 486 487 for (i = 0; i < __arraycount(mmsg); i++) { 488 if ((mstirq & mmsg[i].bit) == 0) 489 continue; 490 printf_tolog("%s: %s %08" PRIx32 " master %s\n", 491 device_xname(sc->sc_pex), cmd[mstcmd].string, mstaddr, 492 mmsg[i].msg); 493 494 mstack |= mmsg[i].bit; 495 if (!cmd[mstcmd].nonfatal) 496 fatal = true; 497 } 498 499 tgtid = __SHIFTOUT(tgtirq, MMCR_HBTGTIRQSTA_T_IRQ_ID); 500 501 for (i = 0; i < __arraycount(tmsg); i++) { 502 if ((tgtirq & tmsg[i].bit) == 0) 503 continue; 504 printf_tolog("%s: %1x target %s\n", device_xname(sc->sc_pex), 505 tgtid, tmsg[i].msg); 506 tgtack |= tmsg[i].bit; 507 } 508 509 /* acknowledge interrupts */ 510 if (tgtack != 0) { 511 handled = true; 512 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQSTA, 513 tgtack); 514 } 515 if (mstack != 0) { 516 handled = true; 517 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQSTA, 518 mstack); 519 } 520 return fatal ? 0 : (handled ? 1 : 0); 521 } 522 523 #define elansc_print_1(__dev, __sc, __reg) \ 524 do { \ 525 aprint_debug_dev(__dev, \ 526 "%s: %s %02" PRIx8 "\n", __func__, #__reg, \ 527 bus_space_read_1((__sc)->sc_memt, (__sc)->sc_memh, __reg)); \ 528 } while (/*CONSTCOND*/0) 529 530 static void 531 elansc_print_par(device_t dev, int i, uint32_t par) 532 { 533 uint32_t addr, sz, unit; 534 const char *tgtstr; 535 536 if ((boothowto & AB_DEBUG) == 0) 537 return; 538 539 switch (par & MMCR_PAR_TARGET) { 540 default: 541 case MMCR_PAR_TARGET_OFF: 542 tgtstr = "off"; 543 break; 544 case MMCR_PAR_TARGET_GPIO: 545 tgtstr = "gpio"; 546 break; 547 case MMCR_PAR_TARGET_GPMEM: 548 tgtstr = "gpmem"; 549 break; 550 case MMCR_PAR_TARGET_PCI: 551 tgtstr = "pci"; 552 break; 553 case MMCR_PAR_TARGET_BOOTCS: 554 tgtstr = "bootcs"; 555 break; 556 case MMCR_PAR_TARGET_ROMCS1: 557 tgtstr = "romcs1"; 558 break; 559 case MMCR_PAR_TARGET_ROMCS2: 560 tgtstr = "romcs2"; 561 break; 562 case MMCR_PAR_TARGET_SDRAM: 563 tgtstr = "sdram"; 564 break; 565 } 566 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_GPIO) { 567 unit = 1; 568 sz = __SHIFTOUT(par, MMCR_PAR_IO_SZ); 569 addr = __SHIFTOUT(par, MMCR_PAR_IO_ST_ADR); 570 } else if ((par & MMCR_PAR_PG_SZ) != 0) { 571 unit = 64 * 1024; 572 sz = __SHIFTOUT(par, MMCR_PAR_64KB_SZ); 573 addr = __SHIFTOUT(par, MMCR_PAR_64KB_ST_ADR); 574 } else { 575 unit = 4 * 1024; 576 sz = __SHIFTOUT(par, MMCR_PAR_4KB_SZ); 577 addr = __SHIFTOUT(par, MMCR_PAR_4KB_ST_ADR); 578 } 579 580 printf_tolog( 581 "%s: PAR[%d] %08" PRIx32 " tgt %s attr %1" __PRIxBITS 582 " start %08" PRIx32 " size %" PRIu32 "\n", device_xname(dev), 583 i, par, tgtstr, __SHIFTOUT(par, MMCR_PAR_ATTR), 584 addr * unit, (sz + 1) * unit); 585 } 586 587 static void 588 elansc_print_all_par(device_t dev, 589 bus_space_tag_t memt, bus_space_handle_t memh) 590 { 591 int i; 592 uint32_t par; 593 594 for (i = 0; i < 16; i++) { 595 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 596 elansc_print_par(dev, i, par); 597 } 598 } 599 600 static int 601 elansc_alloc_par(bus_space_tag_t memt, bus_space_handle_t memh) 602 { 603 int i; 604 uint32_t par; 605 606 for (i = 0; i < 16; i++) { 607 608 par = bus_space_read_4(memt, memh, MMCR_PAR(i)); 609 610 if ((par & MMCR_PAR_TARGET) == MMCR_PAR_TARGET_OFF) 611 break; 612 } 613 if (i == 16) 614 return -1; 615 return i; 616 } 617 618 static void 619 elansc_disable_par(bus_space_tag_t memt, bus_space_handle_t memh, int idx) 620 { 621 uint32_t par; 622 par = bus_space_read_4(memt, memh, MMCR_PAR(idx)); 623 par &= ~MMCR_PAR_TARGET; 624 par |= MMCR_PAR_TARGET_OFF; 625 bus_space_write_4(memt, memh, MMCR_PAR(idx), par); 626 } 627 628 struct pareg { 629 paddr_t start; 630 paddr_t end; 631 }; 632 633 static int 634 region_paddr_to_par(struct pareg *region0, struct pareg *regions, uint32_t unit) 635 { 636 struct pareg *residue = regions; 637 paddr_t start, end; 638 paddr_t start0, end0; 639 640 start0 = region0->start; 641 end0 = region0->end; 642 643 if (start0 % unit != 0) 644 start = start0 + unit - start0 % unit; 645 else 646 start = start0; 647 648 end = end0 - end0 % unit; 649 650 if (start >= end) 651 return 0; 652 653 residue->start = start; 654 residue->end = end; 655 residue++; 656 657 if (start0 < start) { 658 residue->start = start0; 659 residue->end = start; 660 residue++; 661 } 662 if (end < end0) { 663 residue->start = end; 664 residue->end = end0; 665 residue++; 666 } 667 return residue - regions; 668 } 669 670 static void 671 elansc_protect_text(device_t self, struct elansc_softc *sc) 672 { 673 int i, j, nregion, pidx, tidx = 0, xnregion; 674 uint32_t par; 675 uint32_t protsize, unprotsize; 676 paddr_t start_pa, end_pa; 677 extern char kernel_text, etext; 678 bus_space_tag_t memt; 679 bus_space_handle_t memh; 680 struct pareg region0, regions[3], xregions[3]; 681 682 sc->sc_textpar[0] = sc->sc_textpar[1] = sc->sc_textpar[2] = -1; 683 684 memt = sc->sc_memt; 685 memh = sc->sc_memh; 686 687 if (!pmap_extract(pmap_kernel(), (vaddr_t)&kernel_text, 688 ®ion0.start) || 689 !pmap_extract(pmap_kernel(), (vaddr_t)&etext, 690 ®ion0.end)) 691 return; 692 693 if (&etext - &kernel_text != region0.end - region0.start) { 694 aprint_error_dev(self, "kernel text may not be contiguous\n"); 695 return; 696 } 697 698 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 699 aprint_error_dev(self, "cannot allocate PAR\n"); 700 return; 701 } 702 703 par = bus_space_read_4(memt, memh, MMCR_PAR(pidx)); 704 705 aprint_debug_dev(self, 706 "protect kernel text at physical addresses %p - %p\n", 707 (void *)region0.start, (void *)region0.end); 708 709 nregion = region_paddr_to_par(®ion0, regions, sfkb); 710 if (nregion == 0) { 711 aprint_error_dev(self, "kernel text is unprotected\n"); 712 return; 713 } 714 715 unprotsize = 0; 716 for (i = 1; i < nregion; i++) 717 unprotsize += regions[i].end - regions[i].start; 718 719 start_pa = regions[0].start; 720 end_pa = regions[0].end; 721 722 aprint_debug_dev(self, 723 "actually protect kernel text at physical addresses %p - %p\n", 724 (void *)start_pa, (void *)end_pa); 725 726 aprint_verbose_dev(self, 727 "%" PRIu32 " bytes of kernel text are unprotected\n", unprotsize); 728 729 protsize = end_pa - start_pa; 730 731 #if 0 732 /* set PG_SZ, attribute, target, size, address. */ 733 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE | MMCR_PAR_PG_SZ; 734 par |= __SHIFTIN(protsize / sfkb - 1, MMCR_PAR_64KB_SZ); 735 par |= __SHIFTIN(start_pa / sfkb, MMCR_PAR_64KB_ST_ADR); 736 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 737 #else 738 elansc_protect(sc, pidx, start_pa, protsize); 739 #endif 740 741 sc->sc_textpar[tidx++] = pidx; 742 743 unprotsize = 0; 744 for (i = 1; i < nregion; i++) { 745 xnregion = region_paddr_to_par(®ions[i], xregions, fkb); 746 if (xnregion == 0) { 747 aprint_verbose_dev(self, "skip region %p - %p\n", 748 (void *)regions[i].start, (void *)regions[i].end); 749 continue; 750 } 751 if ((pidx = elansc_alloc_par(memt, memh)) == -1) { 752 unprotsize += regions[i].end - regions[i].start; 753 continue; 754 } 755 elansc_protect(sc, pidx, xregions[0].start, 756 xregions[0].end - xregions[0].start); 757 sc->sc_textpar[tidx++] = pidx; 758 759 aprint_debug_dev(self, 760 "protect add'l kernel text at physical addresses %p - %p\n", 761 (void *)xregions[0].start, (void *)xregions[0].end); 762 763 for (j = 1; j < xnregion; j++) 764 unprotsize += xregions[j].end - xregions[j].start; 765 } 766 aprint_verbose_dev(self, 767 "%" PRIu32 " bytes of kernel text still unprotected\n", unprotsize); 768 769 } 770 771 static void 772 elansc_protect(struct elansc_softc *sc, int pidx, paddr_t addr, uint32_t sz) 773 { 774 uint32_t addr_field, blksz, par, size_field; 775 776 /* set attribute, target. */ 777 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 778 779 KASSERT(addr % fkb == 0 && sz % fkb == 0); 780 781 if (addr % sfkb == 0 && sz % sfkb == 0) { 782 par |= MMCR_PAR_PG_SZ; 783 784 size_field = MMCR_PAR_64KB_SZ; 785 addr_field = MMCR_PAR_64KB_ST_ADR; 786 blksz = 64 * 1024; 787 } else { 788 size_field = MMCR_PAR_4KB_SZ; 789 addr_field = MMCR_PAR_4KB_ST_ADR; 790 blksz = 4 * 1024; 791 } 792 793 KASSERT(sz / blksz - 1 <= __SHIFTOUT_MASK(size_field)); 794 KASSERT(addr / blksz <= __SHIFTOUT_MASK(addr_field)); 795 796 /* set size and address. */ 797 par |= __SHIFTIN(sz / blksz - 1, size_field); 798 par |= __SHIFTIN(addr / blksz, addr_field); 799 800 bus_space_write_4(sc->sc_memt, sc->sc_memh, MMCR_PAR(pidx), par); 801 } 802 803 static int 804 elansc_protect_pg0(device_t self, struct elansc_softc *sc) 805 { 806 int pidx; 807 const paddr_t pg0_paddr = 0; 808 bus_space_tag_t memt; 809 bus_space_handle_t memh; 810 811 memt = sc->sc_memt; 812 memh = sc->sc_memh; 813 814 if (elansc_do_protect_pg0 == 0) 815 return -1; 816 817 if ((pidx = elansc_alloc_par(memt, memh)) == -1) 818 return -1; 819 820 aprint_debug_dev(self, "protect page 0\n"); 821 822 #if 0 823 /* set PG_SZ, attribute, target, size, address. */ 824 par = MMCR_PAR_TARGET_SDRAM | MMCR_PAR_ATTR_NOWRITE; 825 par |= __SHIFTIN(PG0_PROT_SIZE / PAGE_SIZE - 1, MMCR_PAR_4KB_SZ); 826 par |= __SHIFTIN(pg0_paddr / PAGE_SIZE, MMCR_PAR_4KB_ST_ADR); 827 bus_space_write_4(memt, memh, MMCR_PAR(pidx), par); 828 #else 829 elansc_protect(sc, pidx, pg0_paddr, PG0_PROT_SIZE); 830 #endif 831 return pidx; 832 } 833 834 static void 835 elanpex_intr_ack(bus_space_tag_t memt, bus_space_handle_t memh) 836 { 837 bus_space_write_1(memt, memh, MMCR_PCIARBSTA, 838 MMCR_PCIARBSTA_GNT_TO_STA); 839 bus_space_write_2(memt, memh, MMCR_HBTGTIRQSTA, MMCR_TGTIRQ_ACT); 840 bus_space_write_2(memt, memh, MMCR_HBMSTIRQSTA, MMCR_MSTIRQ_ACT); 841 } 842 843 static bool 844 elansc_suspend(device_t dev PMF_FN_ARGS) 845 { 846 bool rc; 847 struct elansc_softc *sc = device_private(dev); 848 849 mutex_enter(&sc->sc_mtx); 850 rc = ((sc->sc_smw.smw_mode & WDOG_MODE_MASK) == WDOG_MODE_DISARMED); 851 mutex_exit(&sc->sc_mtx); 852 if (!rc) 853 aprint_debug_dev(dev, "watchdog enabled, suspend forbidden"); 854 return rc; 855 } 856 857 static bool 858 elansc_resume(device_t dev PMF_FN_ARGS) 859 { 860 struct elansc_softc *sc = device_private(dev); 861 862 mutex_enter(&sc->sc_mtx); 863 /* Set up the watchdog registers with some defaults. */ 864 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 865 866 /* ...and clear it. */ 867 elansc_wdogctl_reset(sc); 868 mutex_exit(&sc->sc_mtx); 869 870 elansc_perf_tune(dev, sc->sc_memt, sc->sc_memh); 871 872 return true; 873 } 874 875 static int 876 elansc_detach(device_t self, int flags) 877 { 878 int rc; 879 struct elansc_softc *sc = device_private(self); 880 881 if ((rc = config_detach_children(self, flags)) != 0) 882 return rc; 883 884 pmf_device_deregister(self); 885 886 if ((rc = sysmon_wdog_unregister(&sc->sc_smw)) != 0) { 887 if (rc == ERESTART) 888 rc = EINTR; 889 return rc; 890 } 891 892 mutex_enter(&sc->sc_mtx); 893 894 /* Set up the watchdog registers with some defaults. */ 895 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 896 897 /* ...and clear it. */ 898 elansc_wdogctl_reset(sc); 899 900 mutex_exit(&sc->sc_mtx); 901 mutex_destroy(&sc->sc_mtx); 902 903 bus_space_unmap(sc->sc_memt, sc->sc_memh, PAGE_SIZE); 904 elansc_attached = false; 905 return 0; 906 } 907 908 static void * 909 elansc_intr_establish(device_t dev, int (*handler)(void *), void *arg) 910 { 911 struct pic *pic; 912 void *ih; 913 914 if ((pic = intr_findpic(ELAN_IRQ)) == NULL) { 915 aprint_error_dev(dev, "PIC for irq %d not found\n", 916 ELAN_IRQ); 917 return NULL; 918 } else if ((ih = intr_establish(ELAN_IRQ, pic, ELAN_IRQ, 919 IST_LEVEL, IPL_HIGH, handler, arg, false)) == NULL) { 920 aprint_error_dev(dev, 921 "could not establish interrupt\n"); 922 return NULL; 923 } 924 aprint_verbose_dev(dev, "interrupting at irq %d\n", ELAN_IRQ); 925 return ih; 926 } 927 928 static bool 929 elanpex_resume(device_t self PMF_FN_ARGS) 930 { 931 struct elansc_softc *sc = device_private(device_parent(self)); 932 933 elanpex_intr_establish(self, sc); 934 return sc->sc_eih != NULL; 935 } 936 937 static bool 938 elanpex_suspend(device_t self PMF_FN_ARGS) 939 { 940 struct elansc_softc *sc = device_private(device_parent(self)); 941 942 elanpex_intr_disestablish(sc); 943 944 return true; 945 } 946 947 static bool 948 elanpar_resume(device_t self PMF_FN_ARGS) 949 { 950 struct elansc_softc *sc = device_private(device_parent(self)); 951 952 elanpar_intr_establish(self, sc); 953 return sc->sc_pih != NULL; 954 } 955 956 static bool 957 elanpar_suspend(device_t self PMF_FN_ARGS) 958 { 959 struct elansc_softc *sc = device_private(device_parent(self)); 960 961 elanpar_intr_disestablish(sc); 962 963 return true; 964 } 965 966 static void 967 elanpex_intr_establish(device_t self, struct elansc_softc *sc) 968 { 969 uint8_t sysarbctl; 970 uint16_t pcihostmap, mstirq, tgtirq; 971 972 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 973 MMCR_PCIHOSTMAP); 974 /* Priority P2 (Master PIC IR1) */ 975 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 976 pcihostmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_PCIHOSTMAP_PCI_IRQ_MAP); 977 if (elansc_pcinmi) 978 pcihostmap |= MMCR_PCIHOSTMAP_PCI_NMI_ENB; 979 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 980 pcihostmap); 981 982 elanpex_intr_ack(sc->sc_memt, sc->sc_memh); 983 984 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 985 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 986 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 987 988 sysarbctl |= MMCR_SYSARBCTL_GNT_TO_INT_ENB; 989 990 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 991 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 992 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 993 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 994 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 995 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 996 997 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 998 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 999 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1000 1001 if (elansc_pcinmi) { 1002 sc->sc_eih = nmi_establish(elanpex_intr, sc); 1003 1004 /* Activate NMI instead of maskable interrupts for 1005 * all PCI exceptions: 1006 */ 1007 mstirq |= MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL; 1008 mstirq |= MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL; 1009 mstirq |= MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL; 1010 mstirq |= MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL; 1011 mstirq |= MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL; 1012 mstirq |= MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL; 1013 1014 tgtirq |= MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL; 1015 tgtirq |= MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL; 1016 tgtirq |= MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL; 1017 } else 1018 sc->sc_eih = elansc_intr_establish(self, elanpex_intr, sc); 1019 1020 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1021 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1022 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1023 } 1024 1025 static void 1026 elanpex_attach(device_t parent, device_t self, void *aux) 1027 { 1028 struct elansc_softc *sc = device_private(parent); 1029 1030 aprint_naive(": PCI Exceptions\n"); 1031 aprint_normal(": AMD Elan SC520 PCI Exceptions\n"); 1032 1033 elanpex_intr_establish(self, sc); 1034 1035 aprint_debug_dev(self, "HBMSTIRQCTL %04x\n", 1036 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL)); 1037 1038 aprint_debug_dev(self, "HBTGTIRQCTL %04x\n", 1039 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL)); 1040 1041 aprint_debug_dev(self, "PCIHOSTMAP %04x\n", 1042 bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP)); 1043 1044 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG, 1045 pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG) | 1046 PCI_COMMAND_PARITY_ENABLE|PCI_COMMAND_SERR_ENABLE); 1047 1048 if (!pmf_device_register1(self, elanpex_suspend, elanpex_resume, 1049 elanpex_shutdown)) 1050 aprint_error_dev(self, "could not establish power hooks\n"); 1051 } 1052 1053 static bool 1054 elanpex_shutdown(device_t self, int flags) 1055 { 1056 struct elansc_softc *sc = device_private(device_parent(self)); 1057 uint8_t sysarbctl; 1058 uint16_t pcihostmap, mstirq, tgtirq; 1059 1060 sysarbctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL); 1061 sysarbctl &= ~MMCR_SYSARBCTL_GNT_TO_INT_ENB; 1062 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_SYSARBCTL, sysarbctl); 1063 1064 mstirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL); 1065 mstirq &= ~MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB; 1066 mstirq &= ~MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB; 1067 mstirq &= ~MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB; 1068 mstirq &= ~MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB; 1069 mstirq &= ~MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB; 1070 mstirq &= ~MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB; 1071 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBMSTIRQCTL, mstirq); 1072 1073 tgtirq = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL); 1074 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB; 1075 tgtirq &= ~MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB; 1076 tgtirq &= ~MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB; 1077 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_HBTGTIRQCTL, tgtirq); 1078 1079 pcihostmap = bus_space_read_2(sc->sc_memt, sc->sc_memh, 1080 MMCR_PCIHOSTMAP); 1081 /* Priority P2 (Master PIC IR1) */ 1082 pcihostmap &= ~MMCR_PCIHOSTMAP_PCI_IRQ_MAP; 1083 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_PCIHOSTMAP, 1084 pcihostmap); 1085 1086 return true; 1087 } 1088 1089 static void 1090 elanpex_intr_disestablish(struct elansc_softc *sc) 1091 { 1092 elanpex_shutdown(sc->sc_pex, 0); 1093 1094 if (elansc_pcinmi) 1095 nmi_disestablish(sc->sc_eih); 1096 else 1097 intr_disestablish(sc->sc_eih); 1098 sc->sc_eih = NULL; 1099 1100 } 1101 1102 static int 1103 elanpex_detach(device_t self, int flags) 1104 { 1105 struct elansc_softc *sc = device_private(device_parent(self)); 1106 1107 pmf_device_deregister(self); 1108 elanpex_intr_disestablish(sc); 1109 1110 return 0; 1111 } 1112 1113 static void 1114 elanpar_intr_establish(device_t self, struct elansc_softc *sc) 1115 { 1116 uint8_t adddecctl, wpvmap; 1117 1118 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1119 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1120 if (elansc_wpvnmi) 1121 wpvmap |= MMCR_WPVMAP_INT_NMI; 1122 else 1123 wpvmap |= __SHIFTIN(__BIT(ELAN_IRQ), MMCR_WPVMAP_INT_MAP); 1124 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1125 1126 /* clear interrupt status */ 1127 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1128 MMCR_WPVSTA_WPV_STA); 1129 1130 /* establish interrupt */ 1131 if (elansc_wpvnmi) 1132 sc->sc_pih = nmi_establish(elanpar_intr, sc); 1133 else 1134 sc->sc_pih = elansc_intr_establish(self, elanpar_intr, sc); 1135 1136 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1137 adddecctl |= MMCR_ADDDECCTL_WPV_INT_ENB; 1138 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1139 } 1140 1141 static bool 1142 elanpar_shutdown(device_t self, int flags) 1143 { 1144 int i; 1145 struct elansc_softc *sc = device_private(device_parent(self)); 1146 1147 for (i = 0; i < __arraycount(sc->sc_textpar); i++) { 1148 if (sc->sc_textpar[i] == -1) 1149 continue; 1150 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_textpar[i]); 1151 sc->sc_textpar[i] = -1; 1152 } 1153 if (sc->sc_pg0par != -1) { 1154 elansc_disable_par(sc->sc_memt, sc->sc_memh, sc->sc_pg0par); 1155 sc->sc_pg0par = -1; 1156 } 1157 return true; 1158 } 1159 1160 static void 1161 elanpar_deferred_attach(device_t self) 1162 { 1163 struct elansc_softc *sc = device_private(device_parent(self)); 1164 1165 elansc_protect_text(self, sc); 1166 } 1167 1168 static void 1169 elanpar_attach(device_t parent, device_t self, void *aux) 1170 { 1171 struct elansc_softc *sc = device_private(parent); 1172 1173 aprint_naive(": Programmable Address Regions\n"); 1174 aprint_normal(": AMD Elan SC520 Programmable Address Regions\n"); 1175 1176 elansc_print_1(self, sc, MMCR_WPVMAP); 1177 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1178 1179 sc->sc_pg0par = elansc_protect_pg0(self, sc); 1180 /* XXX grotty hack to avoid trapping writes by x86_patch() 1181 * to the kernel text on a MULTIPROCESSOR kernel. 1182 */ 1183 config_interrupts(self, elanpar_deferred_attach); 1184 1185 elansc_print_all_par(self, sc->sc_memt, sc->sc_memh); 1186 1187 elanpar_intr_establish(self, sc); 1188 1189 elansc_print_1(self, sc, MMCR_ADDDECCTL); 1190 1191 if (!pmf_device_register1(self, elanpar_suspend, elanpar_resume, 1192 elanpar_shutdown)) 1193 aprint_error_dev(self, "could not establish power hooks\n"); 1194 } 1195 1196 static void 1197 elanpar_intr_disestablish(struct elansc_softc *sc) 1198 { 1199 uint8_t adddecctl, wpvmap; 1200 1201 /* disable interrupt, acknowledge it, disestablish our 1202 * handler, unmap it 1203 */ 1204 adddecctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL); 1205 adddecctl &= ~MMCR_ADDDECCTL_WPV_INT_ENB; 1206 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_ADDDECCTL, adddecctl); 1207 1208 bus_space_write_2(sc->sc_memt, sc->sc_memh, MMCR_WPVSTA, 1209 MMCR_WPVSTA_WPV_STA); 1210 1211 if (elansc_wpvnmi) 1212 nmi_disestablish(sc->sc_pih); 1213 else 1214 intr_disestablish(sc->sc_pih); 1215 sc->sc_pih = NULL; 1216 1217 wpvmap = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP); 1218 wpvmap &= ~MMCR_WPVMAP_INT_MAP; 1219 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_WPVMAP, wpvmap); 1220 } 1221 1222 static int 1223 elanpar_detach(device_t self, int flags) 1224 { 1225 struct elansc_softc *sc = device_private(device_parent(self)); 1226 1227 pmf_device_deregister(self); 1228 1229 elanpar_shutdown(self, 0); 1230 1231 elanpar_intr_disestablish(sc); 1232 1233 return 0; 1234 } 1235 1236 static void 1237 elansc_attach(device_t parent, device_t self, void *aux) 1238 { 1239 struct elansc_softc *sc = device_private(self); 1240 struct pcibus_attach_args *pba = aux; 1241 uint16_t rev; 1242 uint8_t cpuctl, picicr, ressta; 1243 #if NGPIO > 0 1244 struct gpiobus_attach_args gba; 1245 int pin, reg, shift; 1246 uint16_t data; 1247 #endif 1248 1249 sc->sc_dev = self; 1250 1251 sc->sc_pc = pba->pba_pc; 1252 sc->sc_tag = pci_make_tag(sc->sc_pc, 0, 0, 0); 1253 1254 aprint_naive(": System Controller\n"); 1255 aprint_normal(": AMD Elan SC520 System Controller\n"); 1256 1257 sc->sc_memt = pba->pba_memt; 1258 if (bus_space_map(sc->sc_memt, MMCR_BASE_ADDR, PAGE_SIZE, 0, 1259 &sc->sc_memh) != 0) { 1260 aprint_error_dev(sc->sc_dev, "unable to map registers\n"); 1261 return; 1262 } 1263 1264 mutex_init(&sc->sc_mtx, MUTEX_DEFAULT, IPL_HIGH); 1265 1266 rev = bus_space_read_2(sc->sc_memt, sc->sc_memh, MMCR_REVID); 1267 cpuctl = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_CPUCTL); 1268 1269 aprint_normal_dev(sc->sc_dev, 1270 "product %d stepping %d.%d, CPU clock %s\n", 1271 (rev & REVID_PRODID) >> REVID_PRODID_SHIFT, 1272 (rev & REVID_MAJSTEP) >> REVID_MAJSTEP_SHIFT, 1273 (rev & REVID_MINSTEP), 1274 elansc_speeds[cpuctl & CPUCTL_CPU_CLK_SPD_MASK]); 1275 1276 /* 1277 * SC520 rev A1 has a bug that affects the watchdog timer. If 1278 * the GP bus echo mode is enabled, writing to the watchdog control 1279 * register is blocked. 1280 * 1281 * The BIOS in some systems (e.g. the Soekris net4501) enables 1282 * GP bus echo for various reasons, so we need to switch it off 1283 * when we talk to the watchdog timer. 1284 * 1285 * XXX The step 1.1 (B1?) in my Soekris net4501 also has this 1286 * XXX problem, so we'll just enable it for all Elan SC520s 1287 * XXX for now. --thorpej (at) NetBSD.org 1288 */ 1289 if (1 || rev == ((PRODID_ELAN_SC520 << REVID_PRODID_SHIFT) | 1290 (0 << REVID_MAJSTEP_SHIFT) | (1))) 1291 sc->sc_echobug = 1; 1292 1293 /* 1294 * Determine cause of the last reset, and issue a warning if it 1295 * was due to watchdog expiry. 1296 */ 1297 ressta = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA); 1298 if (ressta & RESSTA_WDT_RST_DET) 1299 aprint_error_dev(sc->sc_dev, 1300 "WARNING: LAST RESET DUE TO WATCHDOG EXPIRATION!\n"); 1301 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_RESSTA, ressta); 1302 1303 elansc_print_1(self, sc, MMCR_MPICMODE); 1304 elansc_print_1(self, sc, MMCR_SL1PICMODE); 1305 elansc_print_1(self, sc, MMCR_SL2PICMODE); 1306 elansc_print_1(self, sc, MMCR_PICICR); 1307 1308 sc->sc_mpicmode = bus_space_read_1(sc->sc_memt, sc->sc_memh, 1309 MMCR_MPICMODE); 1310 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_MPICMODE, 1311 sc->sc_mpicmode | __BIT(ELAN_IRQ)); 1312 1313 sc->sc_picicr = bus_space_read_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR); 1314 picicr = sc->sc_picicr; 1315 if (elansc_pcinmi || elansc_wpvnmi) 1316 picicr |= MMCR_PICICR_NMI_ENB; 1317 #if 0 1318 /* PC/AT compatibility */ 1319 picicr |= MMCR_PICICR_S1_GINT_MODE|MMCR_PICICR_M_GINT_MODE; 1320 #endif 1321 bus_space_write_1(sc->sc_memt, sc->sc_memh, MMCR_PICICR, picicr); 1322 1323 elansc_print_1(self, sc, MMCR_PICICR); 1324 elansc_print_1(self, sc, MMCR_MPICMODE); 1325 1326 mutex_enter(&sc->sc_mtx); 1327 /* Set up the watchdog registers with some defaults. */ 1328 elansc_wdogctl_write(sc, WDTMRCTL_WRST_ENB | WDTMRCTL_EXP_SEL30); 1329 1330 /* ...and clear it. */ 1331 elansc_wdogctl_reset(sc); 1332 mutex_exit(&sc->sc_mtx); 1333 1334 if (!pmf_device_register(self, elansc_suspend, elansc_resume)) 1335 aprint_error_dev(self, "could not establish power hooks\n"); 1336 1337 #if NGPIO > 0 1338 /* Initialize GPIO pins array */ 1339 for (pin = 0; pin < ELANSC_PIO_NPINS; pin++) { 1340 sc->sc_gpio_pins[pin].pin_num = pin; 1341 sc->sc_gpio_pins[pin].pin_caps = GPIO_PIN_INPUT | 1342 GPIO_PIN_OUTPUT; 1343 1344 /* Read initial state */ 1345 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1346 shift = pin % 16; 1347 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1348 if ((data & (1 << shift)) == 0) 1349 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_INPUT; 1350 else 1351 sc->sc_gpio_pins[pin].pin_flags = GPIO_PIN_OUTPUT; 1352 if (elansc_gpio_pin_read(sc, pin) == 0) 1353 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_LOW; 1354 else 1355 sc->sc_gpio_pins[pin].pin_state = GPIO_PIN_HIGH; 1356 } 1357 1358 /* Create controller tag */ 1359 sc->sc_gpio_gc.gp_cookie = sc; 1360 sc->sc_gpio_gc.gp_pin_read = elansc_gpio_pin_read; 1361 sc->sc_gpio_gc.gp_pin_write = elansc_gpio_pin_write; 1362 sc->sc_gpio_gc.gp_pin_ctl = elansc_gpio_pin_ctl; 1363 1364 gba.gba_gc = &sc->sc_gpio_gc; 1365 gba.gba_pins = sc->sc_gpio_pins; 1366 gba.gba_npins = ELANSC_PIO_NPINS; 1367 1368 sc->sc_par = config_found_ia(sc->sc_dev, "elanparbus", NULL, NULL); 1369 sc->sc_pex = config_found_ia(sc->sc_dev, "elanpexbus", NULL, NULL); 1370 /* Attach GPIO framework */ 1371 config_found_ia(sc->sc_dev, "gpiobus", &gba, gpiobus_print); 1372 #endif /* NGPIO */ 1373 1374 /* 1375 * Hook up the watchdog timer. 1376 */ 1377 sc->sc_smw.smw_name = device_xname(sc->sc_dev); 1378 sc->sc_smw.smw_cookie = sc; 1379 sc->sc_smw.smw_setmode = elansc_wdog_setmode; 1380 sc->sc_smw.smw_tickle = elansc_wdog_tickle; 1381 sc->sc_smw.smw_period = 32; /* actually 32.54 */ 1382 if (sysmon_wdog_register(&sc->sc_smw) != 0) { 1383 aprint_error_dev(sc->sc_dev, 1384 "unable to register watchdog with sysmon\n"); 1385 } 1386 elansc_attached = true; 1387 sc->sc_pci = config_found_ia(self, "pcibus", pba, pcibusprint); 1388 } 1389 1390 static int 1391 elanpex_match(device_t parent, struct cfdata *match, void *aux) 1392 { 1393 struct elansc_softc *sc = device_private(parent); 1394 1395 return sc->sc_pex == NULL; 1396 } 1397 1398 static int 1399 elanpar_match(device_t parent, struct cfdata *match, void *aux) 1400 { 1401 struct elansc_softc *sc = device_private(parent); 1402 1403 return sc->sc_par == NULL; 1404 } 1405 1406 CFATTACH_DECL_NEW(elanpar, 0, 1407 elanpar_match, elanpar_attach, elanpar_detach, NULL); 1408 1409 CFATTACH_DECL_NEW(elanpex, 0, 1410 elanpex_match, elanpex_attach, elanpex_detach, NULL); 1411 1412 CFATTACH_DECL2_NEW(elansc, sizeof(struct elansc_softc), 1413 elansc_match, elansc_attach, elansc_detach, NULL, NULL, 1414 elansc_childdetached); 1415 1416 #if NGPIO > 0 1417 static int 1418 elansc_gpio_pin_read(void *arg, int pin) 1419 { 1420 struct elansc_softc *sc = arg; 1421 int reg, shift; 1422 uint16_t data; 1423 1424 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1425 shift = pin % 16; 1426 1427 mutex_enter(&sc->sc_mtx); 1428 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1429 mutex_exit(&sc->sc_mtx); 1430 1431 return ((data >> shift) & 0x1); 1432 } 1433 1434 static void 1435 elansc_gpio_pin_write(void *arg, int pin, int value) 1436 { 1437 struct elansc_softc *sc = arg; 1438 int reg, shift; 1439 uint16_t data; 1440 1441 reg = (pin < 16 ? MMCR_PIODATA15_0 : MMCR_PIODATA31_16); 1442 shift = pin % 16; 1443 1444 mutex_enter(&sc->sc_mtx); 1445 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1446 if (value == 0) 1447 data &= ~(1 << shift); 1448 else if (value == 1) 1449 data |= (1 << shift); 1450 1451 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1452 mutex_exit(&sc->sc_mtx); 1453 } 1454 1455 static void 1456 elansc_gpio_pin_ctl(void *arg, int pin, int flags) 1457 { 1458 struct elansc_softc *sc = arg; 1459 int reg, shift; 1460 uint16_t data; 1461 1462 reg = (pin < 16 ? MMCR_PIODIR15_0 : MMCR_PIODIR31_16); 1463 shift = pin % 16; 1464 mutex_enter(&sc->sc_mtx); 1465 data = bus_space_read_2(sc->sc_memt, sc->sc_memh, reg); 1466 if (flags & GPIO_PIN_INPUT) 1467 data &= ~(1 << shift); 1468 if (flags & GPIO_PIN_OUTPUT) 1469 data |= (1 << shift); 1470 1471 bus_space_write_2(sc->sc_memt, sc->sc_memh, reg, data); 1472 mutex_exit(&sc->sc_mtx); 1473 } 1474 #endif /* NGPIO */ 1475
Indexes created Mon Sep 29 21:09:56 GMT 2025